1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_IRQ_PARAMS_H__ 27 #define __AMDGPU_DM_IRQ_PARAMS_H__ 28 29 #include "amdgpu_dm_crc.h" 30 31 struct dm_irq_params { 32 u32 last_flip_vblank; 33 struct mod_vrr_params vrr_params; 34 struct dc_stream_state *stream; 35 int active_planes; 36 bool allow_psr_entry; 37 struct mod_freesync_config freesync_config; 38 39 #ifdef CONFIG_DEBUG_FS 40 enum amdgpu_dm_pipe_crc_source crc_src; 41 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 42 struct crc_window_parm crc_window; 43 #endif 44 #endif 45 }; 46 47 #endif /* __AMDGPU_DM_IRQ_PARAMS_H__ */ 48