1 #ifndef __ASM_PARISC_PCI_H
2 #define __ASM_PARISC_PCI_H
3
4 #include <asm/scatterlist.h>
5
6 /*
7 ** HP PCI platforms generally support multiple bus adapters.
8 ** (workstations 1-~4, servers 2-~32)
9 **
10 ** Newer platforms number the busses across PCI bus adapters *sparsely*.
11 ** E.g. 0, 8, 16, ...
12 **
13 ** Under a PCI bus, most HP platforms support PPBs up to two or three
14 ** levels deep. See "Bit3" product line.
15 */
16 #define PCI_MAX_BUSSES 256
17
18 /* [soapbox on]
19 ** Who the hell can develop stuff without ASSERT or VASSERT?
20 ** No one understands all the modules across all platforms.
21 ** For linux add another dimension - processor architectures.
22 **
23 ** This should be a standard/global macro used liberally
24 ** in all code. Every respectable engineer I know in HP
25 ** would support this argument. - grant
26 ** [soapbox off]
27 */
28 #ifdef PCI_DEBUG
29 #define ASSERT(expr) \
30 if(!(expr)) { \
31 printk( "\n" __FILE__ ":%d: Assertion " #expr " failed!\n",__LINE__); \
32 panic(#expr); \
33 }
34 #else
35 #define ASSERT(expr)
36 #endif
37
38
39 /*
40 ** pci_hba_data (aka H2P_OBJECT in HP/UX)
41 **
42 ** This is the "common" or "base" data structure which HBA drivers
43 ** (eg Dino or LBA) are required to place at the top of their own
44 ** dev->sysdata structure. I've heard this called "C inheritance" too.
45 **
46 ** Data needed by pcibios layer belongs here.
47 */
48 struct pci_hba_data {
49 unsigned long base_addr; /* aka Host Physical Address */
50 const struct parisc_device *dev; /* device from PA bus walk */
51 struct pci_bus *hba_bus; /* primary PCI bus below HBA */
52 int hba_num; /* I/O port space access "key" */
53 struct resource bus_num; /* PCI bus numbers */
54 struct resource io_space; /* PIOP */
55 struct resource lmmio_space; /* bus addresses < 4Gb */
56 struct resource elmmio_space; /* additional bus addresses < 4Gb */
57 unsigned long lmmio_space_offset; /* CPU view - PCI view */
58 void * iommu; /* IOMMU this device is under */
59 /* REVISIT - spinlock to protect resources? */
60 };
61
62 #define HBA_DATA(d) ((struct pci_hba_data *) (d))
63
64 /*
65 ** We support 2^16 I/O ports per HBA. These are set up in the form
66 ** 0xbbxxxx, where bb is the bus number and xxxx is the I/O port
67 ** space address.
68 */
69 #define HBA_PORT_SPACE_BITS 16
70
71 #define HBA_PORT_BASE(h) ((h) << HBA_PORT_SPACE_BITS)
72 #define HBA_PORT_SPACE_SIZE (1UL << HBA_PORT_SPACE_BITS)
73
74 #define PCI_PORT_HBA(a) ((a) >> HBA_PORT_SPACE_BITS)
75 #define PCI_PORT_ADDR(a) ((a) & (HBA_PORT_SPACE_SIZE - 1))
76
77 /*
78 ** Convert between PCI (IO_VIEW) addresses and processor (PA_VIEW) addresses.
79 ** Note that we currently support only LMMIO.
80 */
81 #define PCI_BUS_ADDR(hba,a) ((a) - hba->lmmio_space_offset)
82 #define PCI_HOST_ADDR(hba,a) ((a) + hba->lmmio_space_offset)
83
84 /* The PCI address space equals the physical memory address space.
85 The networking and block device layers use this boolean for bounce buffer
86 decisions. */
87 #define PCI_DMA_BUS_IS_PHYS 1
88
89 /*
90 ** KLUGE: linux/pci.h include asm/pci.h BEFORE declaring struct pci_bus
91 ** (This eliminates some of the warnings).
92 */
93 struct pci_bus;
94 struct pci_dev;
95
96 /*
97 ** Most PCI devices (eg Tulip, NCR720) also export the same registers
98 ** to both MMIO and I/O port space. Due to poor performance of I/O Port
99 ** access under HP PCI bus adapters, strongly reccomend use of MMIO
100 ** address space.
101 **
102 ** While I'm at it more PA programming notes:
103 **
104 ** 1) MMIO stores (writes) are posted operations. This means the processor
105 ** gets an "ACK" before the write actually gets to the device. A read
106 ** to the same device (or typically the bus adapter above it) will
107 ** force in-flight write transaction(s) out to the targeted device
108 ** before the read can complete.
109 **
110 ** 2) The Programmed I/O (PIO) data may not always be strongly ordered with
111 ** respect to DMA on all platforms. Ie PIO data can reach the processor
112 ** before in-flight DMA reaches memory. Since most SMP PA platforms
113 ** are I/O coherent, it generally doesn't matter...but sometimes
114 ** it does.
115 **
116 ** I've helped device driver writers debug both types of problems.
117 */
118 struct pci_port_ops {
119 u8 (*inb) (struct pci_hba_data *hba, u16 port);
120 u16 (*inw) (struct pci_hba_data *hba, u16 port);
121 u32 (*inl) (struct pci_hba_data *hba, u16 port);
122 void (*outb) (struct pci_hba_data *hba, u16 port, u8 data);
123 void (*outw) (struct pci_hba_data *hba, u16 port, u16 data);
124 void (*outl) (struct pci_hba_data *hba, u16 port, u32 data);
125 };
126
127
128 struct pci_bios_ops {
129 void (*init)(void);
130 void (*fixup_bus)(struct pci_bus *bus);
131 };
132
133 /*
134 ** See Documentation/DMA-mapping.txt
135 */
136 struct pci_dma_ops {
137 int (*dma_supported)(struct pci_dev *dev, u64 mask);
138 void *(*alloc_consistent)(struct pci_dev *dev, size_t size, dma_addr_t *iova);
139 void (*free_consistent)(struct pci_dev *dev, size_t size, void *vaddr, dma_addr_t iova);
140 dma_addr_t (*map_single)(struct pci_dev *dev, void *addr, size_t size, int direction);
141 void (*unmap_single)(struct pci_dev *dev, dma_addr_t iova, size_t size, int direction);
142 int (*map_sg)(struct pci_dev *dev, struct scatterlist *sg, int nents, int direction);
143 void (*unmap_sg)(struct pci_dev *dev, struct scatterlist *sg, int nhwents, int direction);
144 void (*dma_sync_single)(struct pci_dev *dev, dma_addr_t iova, size_t size, int direction);
145 void (*dma_sync_sg)(struct pci_dev *dev, struct scatterlist *sg, int nelems, int direction);
146 };
147
148
149 /*
150 ** We could live without the hppa_dma_ops indirection if we didn't want
151 ** to support 4 different coherent dma models with one binary (they will
152 ** someday be loadable modules):
153 ** I/O MMU consistent method dma_sync behavior
154 ** ============= ====================== =======================
155 ** a) PA-7x00LC uncachable host memory flush/purge
156 ** b) U2/Uturn cachable host memory NOP
157 ** c) Ike/Astro cachable host memory NOP
158 ** d) EPIC/SAGA memory on EPIC/SAGA flush/reset DMA channel
159 **
160 ** PA-7[13]00LC processors have a GSC bus interface and no I/O MMU.
161 **
162 ** Systems (eg PCX-T workstations) that don't fall into the above
163 ** categories will need to modify the needed drivers to perform
164 ** flush/purge and allocate "regular" cacheable pages for everything.
165 */
166
167 extern struct pci_dma_ops *hppa_dma_ops;
168
169 #ifdef CONFIG_PA11
170 extern struct pci_dma_ops pcxl_dma_ops;
171 extern struct pci_dma_ops pcx_dma_ops;
172 #endif
173
174 /*
175 ** Oops hard if we haven't setup hppa_dma_ops by the time the first driver
176 ** attempts to initialize.
177 ** Since panic() is a (void)(), pci_dma_panic() is needed to satisfy
178 ** the (int)() required by pci_dma_supported() interface.
179 */
pci_dma_panic(char * msg)180 static inline int pci_dma_panic(char *msg)
181 {
182 extern void panic(const char *, ...); /* linux/kernel.h */
183 panic(msg);
184 /* NOTREACHED */
185 return -1;
186 }
187
188 #define pci_dma_supported(p, m) ( \
189 (NULL == hppa_dma_ops) \
190 ? pci_dma_panic("Dynamic DMA support missing...OOPS!\n(Hint: was Astro/Ike/U2/Uturn not claimed?)\n") \
191 : hppa_dma_ops->dma_supported(p,m) \
192 )
193
194 #define pci_alloc_consistent(p, s, a) hppa_dma_ops->alloc_consistent(p,s,a)
195 #define pci_free_consistent(p, s, v, a) hppa_dma_ops->free_consistent(p,s,v,a)
196 #define pci_map_single(p, v, s, d) hppa_dma_ops->map_single(p, v, s, d)
197 #define pci_unmap_single(p, a, s, d) hppa_dma_ops->unmap_single(p, a, s, d)
198 #define pci_map_sg(p, sg, n, d) hppa_dma_ops->map_sg(p, sg, n, d)
199 #define pci_unmap_sg(p, sg, n, d) hppa_dma_ops->unmap_sg(p, sg, n, d)
200
201 /* pci_unmap_{single,page} is not a nop, thus... */
202 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
203 dma_addr_t ADDR_NAME;
204 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
205 __u32 LEN_NAME;
206 #define pci_unmap_addr(PTR, ADDR_NAME) \
207 ((PTR)->ADDR_NAME)
208 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
209 (((PTR)->ADDR_NAME) = (VAL))
210 #define pci_unmap_len(PTR, LEN_NAME) \
211 ((PTR)->LEN_NAME)
212 #define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
213 (((PTR)->LEN_NAME) = (VAL))
214
215 /* For U2/Astro/Ike based platforms (which are fully I/O coherent)
216 ** dma_sync is a NOP. Let's keep the performance path short here.
217 */
218 #define pci_dma_sync_single(p, a, s, d) { if (hppa_dma_ops->dma_sync_single) \
219 hppa_dma_ops->dma_sync_single(p, a, s, d); \
220 }
221 #define pci_dma_sync_sg(p, sg, n, d) { if (hppa_dma_ops->dma_sync_sg) \
222 hppa_dma_ops->dma_sync_sg(p, sg, n, d); \
223 }
224
225 /* No highmem on parisc, plus we have an IOMMU, so mapping pages is easy. */
226 #define pci_map_page(dev, page, off, size, dir) \
227 pci_map_single(dev, (page_address(page) + (off)), size, dir)
228 #define pci_unmap_page(dev,addr,sz,dir) pci_unmap_single(dev,addr,sz,dir)
229
230 /* Don't support DAC yet. */
231 #define pci_dac_dma_supported(pci_dev, mask) (0)
232
233 /*
234 ** Stuff declared in arch/parisc/kernel/pci.c
235 */
236 extern struct pci_port_ops *pci_port;
237 extern struct pci_bios_ops *pci_bios;
238 extern int pci_post_reset_delay; /* delay after de-asserting #RESET */
239 extern int pci_hba_count;
240 extern struct pci_hba_data *parisc_pci_hba[];
241
242 #ifdef CONFIG_PCI
243 extern void pcibios_register_hba(struct pci_hba_data *);
244 extern void pcibios_set_master(struct pci_dev *);
245 extern void pcibios_assign_unassigned_resources(struct pci_bus *);
246 #else
pcibios_register_hba(struct pci_hba_data * x)247 extern inline void pcibios_register_hba(struct pci_hba_data *x)
248 {
249 }
250 #endif
251
252 /*
253 ** used by drivers/pci/pci.c:pci_do_scan_bus()
254 ** 0 == check if bridge is numbered before re-numbering.
255 ** 1 == pci_do_scan_bus() should automatically number all PCI-PCI bridges.
256 **
257 ** REVISIT:
258 ** To date, only alpha sets this to one. We'll need to set this
259 ** to zero for legacy platforms and one for PAT platforms.
260 */
261 #define pcibios_assign_all_busses() (pdc_type == PDC_TYPE_PAT)
262 #define pcibios_scan_all_fns() 0
263
264 #define PCIBIOS_MIN_IO 0x10
265 #define PCIBIOS_MIN_MEM 0x1000 /* NBPG - but pci/setup-res.c dies */
266
267 /* Return the index of the PCI controller for device PDEV. */
268 #define pci_controller_num(PDEV) (0)
269
270 #define GET_IOC(dev) ((struct ioc *)(HBA_DATA(dev->sysdata)->iommu))
271
272 #ifdef CONFIG_IOMMU_CCIO
273 struct parisc_device;
274 struct ioc;
275 void * ccio_get_iommu(const struct parisc_device *dev);
276 struct pci_dev * ccio_get_fake(const struct parisc_device *dev);
277 int ccio_request_resource(const struct parisc_device *dev,
278 struct resource *res);
279 int ccio_allocate_resource(const struct parisc_device *dev,
280 struct resource *res, unsigned long size,
281 unsigned long min, unsigned long max, unsigned long align,
282 void (*alignf)(void *, struct resource *, unsigned long, unsigned long),
283 void *alignf_data);
284 #else /* !CONFIG_IOMMU_CCIO */
285 #define ccio_get_iommu(dev) NULL
286 #define ccio_get_fake(dev) NULL
287 #define ccio_request_resource(dev, res) request_resource(&iomem_resource, res)
288 #define ccio_allocate_resource(dev, res, size, min, max, align, alignf, data) \
289 allocate_resource(&iomem_resource, res, size, min, max, \
290 align, alignf, data)
291 #endif /* !CONFIG_IOMMU_CCIO */
292
293 #ifdef CONFIG_IOMMU_SBA
294 struct parisc_device;
295 void * sba_get_iommu(struct parisc_device *dev);
296 #endif
297
298 #endif /* __ASM_PARISC_PCI_H */
299