1 /*
2 * Product specific probe and attach routines for:
3 * aic7901 and aic7902 SCSI controllers
4 *
5 * Copyright (c) 1994-2001 Justin T. Gibbs.
6 * Copyright (c) 2000-2002 Adaptec Inc.
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
16 * substantially similar to the "NO WARRANTY" disclaimer below
17 * ("Disclaimer") and any redistribution must be conditioned upon
18 * including a substantially similar Disclaimer requirement for further
19 * binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
38 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39 * POSSIBILITY OF SUCH DAMAGES.
40 *
41 * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#75 $
42 *
43 * $FreeBSD$
44 */
45
46 #ifdef __linux__
47 #include "aic79xx_osm.h"
48 #include "aic79xx_inline.h"
49 #else
50 #include <dev/aic7xxx/aic79xx_osm.h>
51 #include <dev/aic7xxx/aic79xx_inline.h>
52 #endif
53
54 static __inline uint64_t
ahd_compose_id(u_int device,u_int vendor,u_int subdevice,u_int subvendor)55 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
56 {
57 uint64_t id;
58
59 id = subvendor
60 | (subdevice << 16)
61 | ((uint64_t)vendor << 32)
62 | ((uint64_t)device << 48);
63
64 return (id);
65 }
66
67 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
68 #define ID_ALL_IROC_MASK 0xFFFFFF7FFFFFFFFFull
69 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
70 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull
71 #define ID_9005_GENERIC_IROC_MASK 0xFFF0FF7F00000000ull
72
73 #define ID_AIC7901 0x800F9005FFFF9005ull
74 #define ID_AHA_29320A 0x8000900500609005ull
75 #define ID_AHA_29320ALP 0x8017900500449005ull
76
77 #define ID_AIC7901A 0x801E9005FFFF9005ull
78 #define ID_AHA_29320 0x8012900500429005ull
79 #define ID_AHA_29320B 0x8013900500439005ull
80 #define ID_AHA_29320LP 0x8014900500449005ull
81
82 #define ID_AIC7902 0x801F9005FFFF9005ull
83 #define ID_AIC7902_B 0x801D9005FFFF9005ull
84 #define ID_AHA_39320 0x8010900500409005ull
85 #define ID_AHA_39320_B 0x8015900500409005ull
86 #define ID_AHA_39320A 0x8016900500409005ull
87 #define ID_AHA_39320D 0x8011900500419005ull
88 #define ID_AHA_39320D_B 0x801C900500419005ull
89 #define ID_AHA_39320D_HP 0x8011900500AC0E11ull
90 #define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull
91 #define ID_AIC7902_PCI_REV_A4 0x3
92 #define ID_AIC7902_PCI_REV_B0 0x10
93 #define SUBID_HP 0x0E11
94
95 #define DEVID_9005_TYPE(id) ((id) & 0xF)
96 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
97 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */
98 #define DEVID_9005_TYPE_IROC 0x8 /* Raid(0,1,10) Card */
99 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
100
101 #define DEVID_9005_MFUNC(id) ((id) & 0x10)
102
103 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000)
104
105 #define SUBID_9005_TYPE(id) ((id) & 0xF)
106 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */
107 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */
108
109 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0)
110
111 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20)
112
113 #define SUBID_9005_SEEPTYPE(id) (((id) & 0x0C0) >> 6)
114 #define SUBID_9005_SEEPTYPE_NONE 0x0
115 #define SUBID_9005_SEEPTYPE_4K 0x1
116
117 static ahd_device_setup_t ahd_aic7901_setup;
118 static ahd_device_setup_t ahd_aic7901A_setup;
119 static ahd_device_setup_t ahd_aic7902_setup;
120
121 struct ahd_pci_identity ahd_pci_ident_table [] =
122 {
123 /* aic7901 based controllers */
124 {
125 ID_AHA_29320A,
126 ID_ALL_MASK,
127 "Adaptec 29320A Ultra320 SCSI adapter",
128 ahd_aic7901_setup
129 },
130 {
131 ID_AHA_29320ALP,
132 ID_ALL_MASK,
133 "Adaptec 29320ALP Ultra320 SCSI adapter",
134 ahd_aic7901_setup
135 },
136 /* aic7901A based controllers */
137 {
138 ID_AHA_29320,
139 ID_ALL_MASK,
140 "Adaptec 29320 Ultra320 SCSI adapter",
141 ahd_aic7901A_setup
142 },
143 {
144 ID_AHA_29320B,
145 ID_ALL_MASK,
146 "Adaptec 29320B Ultra320 SCSI adapter",
147 ahd_aic7901A_setup
148 },
149 {
150 ID_AHA_29320LP,
151 ID_ALL_MASK,
152 "Adaptec 29320LP Ultra320 SCSI adapter",
153 ahd_aic7901A_setup
154 },
155 /* aic7902 based controllers */
156 {
157 ID_AHA_39320,
158 ID_ALL_MASK,
159 "Adaptec 39320 Ultra320 SCSI adapter",
160 ahd_aic7902_setup
161 },
162 {
163 ID_AHA_39320_B,
164 ID_ALL_MASK,
165 "Adaptec 39320 Ultra320 SCSI adapter",
166 ahd_aic7902_setup
167 },
168 {
169 ID_AHA_39320A,
170 ID_ALL_MASK,
171 "Adaptec 39320A Ultra320 SCSI adapter",
172 ahd_aic7902_setup
173 },
174 {
175 ID_AHA_39320D,
176 ID_ALL_MASK,
177 "Adaptec 39320D Ultra320 SCSI adapter",
178 ahd_aic7902_setup
179 },
180 {
181 ID_AHA_39320D_HP,
182 ID_ALL_MASK,
183 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
184 ahd_aic7902_setup
185 },
186 {
187 ID_AHA_39320D_B,
188 ID_ALL_MASK,
189 "Adaptec 39320D Ultra320 SCSI adapter",
190 ahd_aic7902_setup
191 },
192 {
193 ID_AHA_39320D_B_HP,
194 ID_ALL_MASK,
195 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
196 ahd_aic7902_setup
197 },
198 {
199 ID_AHA_29320,
200 ID_ALL_MASK,
201 "Adaptec 29320 Ultra320 SCSI adapter",
202 ahd_aic7902_setup
203 },
204 {
205 ID_AHA_29320B,
206 ID_ALL_MASK,
207 "Adaptec 29320B Ultra320 SCSI adapter",
208 ahd_aic7902_setup
209 },
210 /* Generic chip probes for devices we don't know 'exactly' */
211 {
212 ID_AIC7901 & ID_DEV_VENDOR_MASK,
213 ID_DEV_VENDOR_MASK,
214 "Adaptec AIC7901 Ultra320 SCSI adapter",
215 ahd_aic7901_setup
216 },
217 {
218 ID_AIC7901A & ID_DEV_VENDOR_MASK,
219 ID_DEV_VENDOR_MASK,
220 "Adaptec AIC7901A Ultra320 SCSI adapter",
221 ahd_aic7901A_setup
222 },
223 {
224 ID_AIC7902 & ID_9005_GENERIC_MASK,
225 ID_9005_GENERIC_MASK,
226 "Adaptec AIC7902 Ultra320 SCSI adapter",
227 ahd_aic7902_setup
228 }
229 };
230
231 const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table);
232
233 #define DEVCONFIG 0x40
234 #define PCIXINITPAT 0x0000E000ul
235 #define PCIXINIT_PCI33_66 0x0000E000ul
236 #define PCIXINIT_PCIX50_66 0x0000C000ul
237 #define PCIXINIT_PCIX66_100 0x0000A000ul
238 #define PCIXINIT_PCIX100_133 0x00008000ul
239 #define PCI_BUS_MODES_INDEX(devconfig) \
240 (((devconfig) & PCIXINITPAT) >> 13)
241 static const char *pci_bus_modes[] =
242 {
243 "PCI bus mode unknown",
244 "PCI bus mode unknown",
245 "PCI bus mode unknown",
246 "PCI bus mode unknown",
247 "PCI-X 101-133Mhz",
248 "PCI-X 67-100Mhz",
249 "PCI-X 50-66Mhz",
250 "PCI 33 or 66Mhz"
251 };
252
253 #define TESTMODE 0x00000800ul
254 #define IRDY_RST 0x00000200ul
255 #define FRAME_RST 0x00000100ul
256 #define PCI64BIT 0x00000080ul
257 #define MRDCEN 0x00000040ul
258 #define ENDIANSEL 0x00000020ul
259 #define MIXQWENDIANEN 0x00000008ul
260 #define DACEN 0x00000004ul
261 #define STPWLEVEL 0x00000002ul
262 #define QWENDIANSEL 0x00000001ul
263
264 #define DEVCONFIG1 0x44
265 #define PREQDIS 0x01
266
267 #define CSIZE_LATTIME 0x0c
268 #define CACHESIZE 0x000000fful
269 #define LATTIME 0x0000ff00ul
270
271 static int ahd_check_extport(struct ahd_softc *ahd);
272 static void ahd_configure_termination(struct ahd_softc *ahd,
273 u_int adapter_control);
274 static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat);
275
276 struct ahd_pci_identity *
ahd_find_pci_device(ahd_dev_softc_t pci)277 ahd_find_pci_device(ahd_dev_softc_t pci)
278 {
279 uint64_t full_id;
280 uint16_t device;
281 uint16_t vendor;
282 uint16_t subdevice;
283 uint16_t subvendor;
284 struct ahd_pci_identity *entry;
285 u_int i;
286
287 vendor = ahd_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
288 device = ahd_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
289 subvendor = ahd_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
290 subdevice = ahd_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
291 full_id = ahd_compose_id(device,
292 vendor,
293 subdevice,
294 subvendor);
295
296 for (i = 0; i < ahd_num_pci_devs; i++) {
297 entry = &ahd_pci_ident_table[i];
298 if (entry->full_id == (full_id & entry->id_mask)) {
299 /* Honor exclusion entries. */
300 if (entry->name == NULL)
301 return (NULL);
302 return (entry);
303 }
304 }
305 return (NULL);
306 }
307
308 int
ahd_pci_config(struct ahd_softc * ahd,struct ahd_pci_identity * entry)309 ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry)
310 {
311 struct scb_data *shared_scb_data;
312 u_long l;
313 u_int command;
314 uint32_t devconfig;
315 uint16_t subvendor;
316 int error;
317
318 shared_scb_data = NULL;
319 ahd->description = entry->name;
320 /*
321 * Record if this is an HP board.
322 */
323 subvendor = ahd_pci_read_config(ahd->dev_softc,
324 PCIR_SUBVEND_0, /*bytes*/2);
325 if (subvendor == SUBID_HP)
326 ahd->flags |= AHD_HP_BOARD;
327
328 error = entry->setup(ahd);
329 if (error != 0)
330 return (error);
331
332 devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
333 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) {
334 ahd->chip |= AHD_PCI;
335 /* Disable PCIX workarounds when running in PCI mode. */
336 ahd->bugs &= ~AHD_PCIX_BUG_MASK;
337 } else {
338 ahd->chip |= AHD_PCIX;
339 }
340 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)];
341
342 ahd_power_state_change(ahd, AHD_POWER_STATE_D0);
343
344 error = ahd_pci_map_registers(ahd);
345 if (error != 0)
346 return (error);
347
348 /*
349 * If we need to support high memory, enable dual
350 * address cycles. This bit must be set to enable
351 * high address bit generation even if we are on a
352 * 64bit bus (PCI64BIT set in devconfig).
353 */
354 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) {
355 uint32_t devconfig;
356
357 if (bootverbose)
358 printf("%s: Enabling 39Bit Addressing\n",
359 ahd_name(ahd));
360 devconfig = ahd_pci_read_config(ahd->dev_softc,
361 DEVCONFIG, /*bytes*/4);
362 devconfig |= DACEN;
363 ahd_pci_write_config(ahd->dev_softc, DEVCONFIG,
364 devconfig, /*bytes*/4);
365 }
366
367 /* Ensure busmastering is enabled */
368 command = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
369 command |= PCIM_CMD_BUSMASTEREN;
370 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
371
372 error = ahd_softc_init(ahd);
373 if (error != 0)
374 return (error);
375
376 ahd->bus_intr = ahd_pci_intr;
377
378 error = ahd_reset(ahd, /*reinit*/FALSE);
379 if (error != 0)
380 return (ENXIO);
381
382 ahd->pci_cachesize =
383 ahd_pci_read_config(ahd->dev_softc, CSIZE_LATTIME,
384 /*bytes*/1) & CACHESIZE;
385 ahd->pci_cachesize *= 4;
386
387 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
388 /* See if we have a SEEPROM and perform auto-term */
389 error = ahd_check_extport(ahd);
390 if (error != 0)
391 return (error);
392
393 /* Core initialization */
394 error = ahd_init(ahd);
395 if (error != 0)
396 return (error);
397
398 /*
399 * Allow interrupts now that we are completely setup.
400 */
401 error = ahd_pci_map_int(ahd);
402 if (error != 0)
403 return (error);
404
405 ahd_list_lock(&l);
406 /*
407 * Link this softc in with all other ahd instances.
408 */
409 ahd_softc_insert(ahd);
410 ahd_list_unlock(&l);
411 return (0);
412 }
413
414 /*
415 * Perform some simple tests that should catch situations where
416 * our registers are invalidly mapped.
417 */
418 int
ahd_pci_test_register_access(struct ahd_softc * ahd)419 ahd_pci_test_register_access(struct ahd_softc *ahd)
420 {
421 uint32_t cmd;
422 u_int targpcistat;
423 u_int pci_status1;
424 int error;
425 uint8_t hcntrl;
426
427 error = EIO;
428
429 /*
430 * Enable PCI error interrupt status, but suppress NMIs
431 * generated by SERR raised due to target aborts.
432 */
433 cmd = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
434 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
435 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
436
437 /*
438 * First a simple test to see if any
439 * registers can be read. Reading
440 * HCNTRL has no side effects and has
441 * at least one bit that is guaranteed to
442 * be zero so it is a good register to
443 * use for this test.
444 */
445 hcntrl = ahd_inb(ahd, HCNTRL);
446 if (hcntrl == 0xFF)
447 goto fail;
448
449 /*
450 * Next create a situation where write combining
451 * or read prefetching could be initiated by the
452 * CPU or host bridge. Our device does not support
453 * either, so look for data corruption and/or flaged
454 * PCI errors. First pause without causing another
455 * chip reset.
456 */
457 hcntrl &= ~CHIPRST;
458 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE);
459 while (ahd_is_paused(ahd) == 0)
460 ;
461
462 /* Clear any PCI errors that occurred before our driver attached. */
463 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
464 targpcistat = ahd_inb(ahd, TARGPCISTAT);
465 ahd_outb(ahd, TARGPCISTAT, targpcistat);
466 pci_status1 = ahd_pci_read_config(ahd->dev_softc,
467 PCIR_STATUS + 1, /*bytes*/1);
468 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
469 pci_status1, /*bytes*/1);
470 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
471 ahd_outb(ahd, CLRINT, CLRPCIINT);
472
473 ahd_outb(ahd, SEQCTL0, PERRORDIS);
474 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa);
475 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa)
476 goto fail;
477
478 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
479 u_int targpcistat;
480
481 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
482 targpcistat = ahd_inb(ahd, TARGPCISTAT);
483 if ((targpcistat & STA) != 0)
484 goto fail;
485 }
486
487 error = 0;
488
489 fail:
490 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
491
492 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
493 targpcistat = ahd_inb(ahd, TARGPCISTAT);
494
495 /* Silently clear any latched errors. */
496 ahd_outb(ahd, TARGPCISTAT, targpcistat);
497 pci_status1 = ahd_pci_read_config(ahd->dev_softc,
498 PCIR_STATUS + 1, /*bytes*/1);
499 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
500 pci_status1, /*bytes*/1);
501 ahd_outb(ahd, CLRINT, CLRPCIINT);
502 }
503 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS);
504 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
505 return (error);
506 }
507
508 /*
509 * Check the external port logic for a serial eeprom
510 * and termination/cable detection contrls.
511 */
512 static int
ahd_check_extport(struct ahd_softc * ahd)513 ahd_check_extport(struct ahd_softc *ahd)
514 {
515 struct vpd_config vpd;
516 struct seeprom_config *sc;
517 u_int adapter_control;
518 int have_seeprom;
519 int error;
520
521 sc = ahd->seep_config;
522 have_seeprom = ahd_acquire_seeprom(ahd);
523 if (have_seeprom) {
524 u_int start_addr;
525
526 /*
527 * Fetch VPD for this function and parse it.
528 */
529 if (bootverbose)
530 printf("%s: Reading VPD from SEEPROM...",
531 ahd_name(ahd));
532
533 /* Address is always in units of 16bit words */
534 start_addr = ((2 * sizeof(*sc))
535 + (sizeof(vpd) * (ahd->channel - 'A'))) / 2;
536
537 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd,
538 start_addr, sizeof(vpd)/2,
539 /*bytestream*/TRUE);
540 if (error == 0)
541 error = ahd_parse_vpddata(ahd, &vpd);
542 if (bootverbose)
543 printf("%s: VPD parsing %s\n",
544 ahd_name(ahd),
545 error == 0 ? "successful" : "failed");
546
547 if (bootverbose)
548 printf("%s: Reading SEEPROM...", ahd_name(ahd));
549
550 /* Address is always in units of 16bit words */
551 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A');
552
553 error = ahd_read_seeprom(ahd, (uint16_t *)sc,
554 start_addr, sizeof(*sc)/2,
555 /*bytestream*/FALSE);
556
557 if (error != 0) {
558 printf("Unable to read SEEPROM\n");
559 have_seeprom = 0;
560 } else {
561 have_seeprom = ahd_verify_cksum(sc);
562
563 if (bootverbose) {
564 if (have_seeprom == 0)
565 printf ("checksum error\n");
566 else
567 printf ("done.\n");
568 }
569 }
570 ahd_release_seeprom(ahd);
571 }
572
573 if (!have_seeprom) {
574 u_int nvram_scb;
575
576 /*
577 * Pull scratch ram settings and treat them as
578 * if they are the contents of an seeprom if
579 * the 'ADPT', 'BIOS', or 'ASPI' signature is found
580 * in SCB 0xFF. We manually compose the data as 16bit
581 * values to avoid endian issues.
582 */
583 ahd_set_scbptr(ahd, 0xFF);
584 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET);
585 if (nvram_scb != 0xFF
586 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
587 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D'
588 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
589 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T')
590 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B'
591 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I'
592 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O'
593 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S')
594 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
595 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S'
596 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
597 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) {
598 uint16_t *sc_data;
599 int i;
600
601 ahd_set_scbptr(ahd, nvram_scb);
602 sc_data = (uint16_t *)sc;
603 for (i = 0; i < 64; i += 2)
604 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i);
605 have_seeprom = ahd_verify_cksum(sc);
606 if (have_seeprom)
607 ahd->flags |= AHD_SCB_CONFIG_USED;
608 }
609 }
610
611 #if AHD_DEBUG
612 if (have_seeprom != 0
613 && (ahd_debug & AHD_DUMP_SEEPROM) != 0) {
614 uint16_t *sc_data;
615 int i;
616
617 printf("%s: Seeprom Contents:", ahd_name(ahd));
618 sc_data = (uint16_t *)sc;
619 for (i = 0; i < (sizeof(*sc)); i += 2)
620 printf("\n\t0x%.4x", sc_data[i]);
621 printf("\n");
622 }
623 #endif
624
625 if (!have_seeprom) {
626 if (bootverbose)
627 printf("%s: No SEEPROM available.\n", ahd_name(ahd));
628 ahd->flags |= AHD_USEDEFAULTS;
629 error = ahd_default_config(ahd);
630 adapter_control = CFAUTOTERM|CFSEAUTOTERM;
631 free(ahd->seep_config, M_DEVBUF);
632 ahd->seep_config = NULL;
633 } else {
634 error = ahd_parse_cfgdata(ahd, sc);
635 adapter_control = sc->adapter_control;
636 }
637 if (error != 0)
638 return (error);
639
640 ahd_configure_termination(ahd, adapter_control);
641
642 return (0);
643 }
644
645 static void
ahd_configure_termination(struct ahd_softc * ahd,u_int adapter_control)646 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control)
647 {
648 int error;
649 u_int sxfrctl1;
650 uint8_t termctl;
651 uint32_t devconfig;
652
653 devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
654 devconfig &= ~STPWLEVEL;
655 if ((ahd->flags & AHD_STPWLEVEL_A) != 0)
656 devconfig |= STPWLEVEL;
657 if (bootverbose)
658 printf("%s: STPWLEVEL is %s\n",
659 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off");
660 ahd_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
661
662 /* Make sure current sensing is off. */
663 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) {
664 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0);
665 }
666
667 /*
668 * Read to sense. Write to set.
669 */
670 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl);
671 if ((adapter_control & CFAUTOTERM) == 0) {
672 if (bootverbose)
673 printf("%s: Manual Primary Termination\n",
674 ahd_name(ahd));
675 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH);
676 if ((adapter_control & CFSTERM) != 0)
677 termctl |= FLX_TERMCTL_ENPRILOW;
678 if ((adapter_control & CFWSTERM) != 0)
679 termctl |= FLX_TERMCTL_ENPRIHIGH;
680 } else if (error != 0) {
681 printf("%s: Primary Auto-Term Sensing failed! "
682 "Using Defaults.\n", ahd_name(ahd));
683 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH;
684 }
685
686 if ((adapter_control & CFSEAUTOTERM) == 0) {
687 if (bootverbose)
688 printf("%s: Manual Secondary Termination\n",
689 ahd_name(ahd));
690 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH);
691 if ((adapter_control & CFSELOWTERM) != 0)
692 termctl |= FLX_TERMCTL_ENSECLOW;
693 if ((adapter_control & CFSEHIGHTERM) != 0)
694 termctl |= FLX_TERMCTL_ENSECHIGH;
695 } else if (error != 0) {
696 printf("%s: Secondary Auto-Term Sensing failed! "
697 "Using Defaults.\n", ahd_name(ahd));
698 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH;
699 }
700
701 /*
702 * Now set the termination based on what we found.
703 */
704 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN;
705 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) {
706 ahd->flags |= AHD_TERM_ENB_A;
707 sxfrctl1 |= STPWEN;
708 }
709 /* Must set the latch once in order to be effective. */
710 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
711 ahd_outb(ahd, SXFRCTL1, sxfrctl1);
712
713 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl);
714 if (error != 0) {
715 printf("%s: Unable to set termination settings!\n",
716 ahd_name(ahd));
717 } else if (bootverbose) {
718 printf("%s: Primary High byte termination %sabled\n",
719 ahd_name(ahd),
720 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis");
721
722 printf("%s: Primary Low byte termination %sabled\n",
723 ahd_name(ahd),
724 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis");
725
726 printf("%s: Secondary High byte termination %sabled\n",
727 ahd_name(ahd),
728 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis");
729
730 printf("%s: Secondary Low byte termination %sabled\n",
731 ahd_name(ahd),
732 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis");
733 }
734 return;
735 }
736
737 #define DPE 0x80
738 #define SSE 0x40
739 #define RMA 0x20
740 #define RTA 0x10
741 #define STA 0x08
742 #define DPR 0x01
743
744 static const char *split_status_source[] =
745 {
746 "DFF0",
747 "DFF1",
748 "OVLY",
749 "CMC",
750 };
751
752 static const char *pci_status_source[] =
753 {
754 "DFF0",
755 "DFF1",
756 "SG",
757 "CMC",
758 "OVLY",
759 "NONE",
760 "MSI",
761 "TARG"
762 };
763
764 static const char *split_status_strings[] =
765 {
766 "%s: Received split response in %s.\n",
767 "%s: Received split completion error message in %s\n",
768 "%s: Receive overrun in %s\n",
769 "%s: Count not complete in %s\n",
770 "%s: Split completion data bucket in %s\n",
771 "%s: Split completion address error in %s\n",
772 "%s: Split completion byte count error in %s\n",
773 "%s: Signaled Target-abort to early terminate a split in %s\n"
774 };
775
776 static const char *pci_status_strings[] =
777 {
778 "%s: Data Parity Error has been reported via PERR# in %s\n",
779 "%s: Target initial wait state error in %s\n",
780 "%s: Split completion read data parity error in %s\n",
781 "%s: Split completion address attribute parity error in %s\n",
782 "%s: Received a Target Abort in %s\n",
783 "%s: Received a Master Abort in %s\n",
784 "%s: Signal System Error Detected in %s\n",
785 "%s: Address or Write Phase Parity Error Detected in %s.\n"
786 };
787
788 void
ahd_pci_intr(struct ahd_softc * ahd)789 ahd_pci_intr(struct ahd_softc *ahd)
790 {
791 uint8_t pci_status[8];
792 ahd_mode_state saved_modes;
793 u_int pci_status1;
794 u_int intstat;
795 u_int i;
796 u_int reg;
797
798 intstat = ahd_inb(ahd, INTSTAT);
799
800 if ((intstat & SPLTINT) != 0)
801 ahd_pci_split_intr(ahd, intstat);
802
803 if ((intstat & PCIINT) == 0)
804 return;
805
806 printf("%s: PCI error Interrupt\n", ahd_name(ahd));
807 saved_modes = ahd_save_modes(ahd);
808 ahd_dump_card_state(ahd);
809 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
810 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) {
811
812 if (i == 5)
813 continue;
814 pci_status[i] = ahd_inb(ahd, reg);
815 /* Clear latched errors. So our interrupt deasserts. */
816 ahd_outb(ahd, reg, pci_status[i]);
817 }
818
819 for (i = 0; i < 8; i++) {
820 u_int bit;
821
822 if (i == 5)
823 continue;
824
825 for (bit = 0; bit < 8; bit++) {
826
827 if ((pci_status[i] & (0x1 << bit)) != 0) {
828 static const char *s;
829
830 s = pci_status_strings[bit];
831 if (i == 7/*TARG*/ && bit == 3)
832 s = "%s: Signaled Target Abort\n";
833 printf(s, ahd_name(ahd), pci_status_source[i]);
834 }
835 }
836 }
837 pci_status1 = ahd_pci_read_config(ahd->dev_softc,
838 PCIR_STATUS + 1, /*bytes*/1);
839 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
840 pci_status1, /*bytes*/1);
841 ahd_restore_modes(ahd, saved_modes);
842 ahd_outb(ahd, CLRINT, CLRPCIINT);
843 ahd_unpause(ahd);
844 }
845
846 static void
ahd_pci_split_intr(struct ahd_softc * ahd,u_int intstat)847 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat)
848 {
849 uint8_t split_status[4];
850 uint8_t split_status1[4];
851 uint8_t sg_split_status[2];
852 uint8_t sg_split_status1[2];
853 ahd_mode_state saved_modes;
854 u_int i;
855 uint16_t pcix_status;
856
857 /*
858 * Check for splits in all modes. Modes 0 and 1
859 * additionally have SG engine splits to look at.
860 */
861 pcix_status = ahd_pci_read_config(ahd->dev_softc, PCIXR_STATUS,
862 /*bytes*/2);
863 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n",
864 ahd_name(ahd), pcix_status);
865 saved_modes = ahd_save_modes(ahd);
866 for (i = 0; i < 4; i++) {
867 ahd_set_modes(ahd, i, i);
868
869 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0);
870 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1);
871 /* Clear latched errors. So our interrupt deasserts. */
872 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]);
873 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]);
874 if (i > 1)
875 continue;
876 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0);
877 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1);
878 /* Clear latched errors. So our interrupt deasserts. */
879 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]);
880 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]);
881 }
882
883 for (i = 0; i < 4; i++) {
884 u_int bit;
885
886 for (bit = 0; bit < 8; bit++) {
887
888 if ((split_status[i] & (0x1 << bit)) != 0) {
889 static const char *s;
890
891 s = split_status_strings[bit];
892 printf(s, ahd_name(ahd),
893 split_status_source[i]);
894 }
895
896 if (i > 1)
897 continue;
898
899 if ((sg_split_status[i] & (0x1 << bit)) != 0) {
900 static const char *s;
901
902 s = split_status_strings[bit];
903 printf(s, ahd_name(ahd), "SG");
904 }
905 }
906 }
907 /*
908 * Clear PCI-X status bits.
909 */
910 ahd_pci_write_config(ahd->dev_softc, PCIXR_STATUS,
911 pcix_status, /*bytes*/2);
912 ahd_outb(ahd, CLRINT, CLRSPLTINT);
913 ahd_restore_modes(ahd, saved_modes);
914 }
915
916 static int
ahd_aic7901_setup(struct ahd_softc * ahd)917 ahd_aic7901_setup(struct ahd_softc *ahd)
918 {
919 int error;
920
921 error = ahd_aic7902_setup(ahd);
922 if (error != 0)
923 return (error);
924 ahd->chip = AHD_AIC7901;
925 return (0);
926 }
927
928 static int
ahd_aic7901A_setup(struct ahd_softc * ahd)929 ahd_aic7901A_setup(struct ahd_softc *ahd)
930 {
931 int error;
932
933 error = ahd_aic7902_setup(ahd);
934 if (error != 0)
935 return (error);
936 ahd->chip = AHD_AIC7901A;
937 return (0);
938 }
939
940 static int
ahd_aic7902_setup(struct ahd_softc * ahd)941 ahd_aic7902_setup(struct ahd_softc *ahd)
942 {
943 ahd_dev_softc_t pci;
944 u_int rev;
945
946 pci = ahd->dev_softc;
947 rev = ahd_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
948 if (rev < ID_AIC7902_PCI_REV_A4) {
949 printf("%s: Unable to attach to unsupported chip revision %d\n",
950 ahd_name(ahd), rev);
951 ahd_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2);
952 return (ENXIO);
953 }
954 ahd->channel = ahd_get_pci_function(pci) + 'A';
955 ahd->chip = AHD_AIC7902;
956 ahd->features = AHD_AIC7902_FE;
957 if (rev < ID_AIC7902_PCI_REV_B0) {
958 /*
959 * Enable A series workarounds.
960 */
961 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG
962 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG
963 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG
964 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG
965 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG
966 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG
967 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG
968 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG
969 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG
970 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG
971 | AHD_FAINT_LED_BUG;
972
973 /*
974 * IO Cell paramter setup.
975 */
976 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
977
978 if ((ahd->flags & AHD_HP_BOARD) == 0)
979 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA);
980 } else {
981 u_int devconfig1;
982
983 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS
984 | AHD_NEW_DFCNTRL_OPTS;
985 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_ABORT_LQI_BUG
986 | AHD_INTCOLLISION_BUG|AHD_EARLY_REQ_BUG;
987
988 /*
989 * IO Cell paramter setup.
990 */
991 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
992 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB);
993 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF);
994
995 /*
996 * Set the PREQDIS bit for H2B which disables some workaround
997 * that doesn't work on regular PCI busses.
998 * XXX - Find out exactly what this does from the hardware
999 * folks!
1000 */
1001 devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
1002 ahd_pci_write_config(pci, DEVCONFIG1,
1003 devconfig1|PREQDIS, /*bytes*/1);
1004 devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
1005 }
1006
1007 return (0);
1008 }
1009