1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Implement the AER root port service driver. The driver registers an IRQ
4 * handler. When a root port triggers an AER interrupt, the IRQ handler
5 * collects root port status and schedules work.
6 *
7 * Copyright (C) 2006 Intel Corp.
8 * Tom Long Nguyen (tom.l.nguyen@intel.com)
9 * Zhang Yanmin (yanmin.zhang@intel.com)
10 *
11 * (C) Copyright 2009 Hewlett-Packard Development Company, L.P.
12 * Andrew Patterson <andrew.patterson@hp.com>
13 */
14
15 #define pr_fmt(fmt) "AER: " fmt
16 #define dev_fmt pr_fmt
17
18 #include <linux/bitops.h>
19 #include <linux/cper.h>
20 #include <linux/pci.h>
21 #include <linux/pci-acpi.h>
22 #include <linux/sched.h>
23 #include <linux/kernel.h>
24 #include <linux/errno.h>
25 #include <linux/pm.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/kfifo.h>
30 #include <linux/slab.h>
31 #include <acpi/apei.h>
32 #include <ras/ras_event.h>
33
34 #include "../pci.h"
35 #include "portdrv.h"
36
37 #define AER_ERROR_SOURCES_MAX 128
38
39 #define AER_MAX_TYPEOF_COR_ERRS 16 /* as per PCI_ERR_COR_STATUS */
40 #define AER_MAX_TYPEOF_UNCOR_ERRS 27 /* as per PCI_ERR_UNCOR_STATUS*/
41
42 struct aer_err_source {
43 unsigned int status;
44 unsigned int id;
45 };
46
47 struct aer_rpc {
48 struct pci_dev *rpd; /* Root Port device */
49 DECLARE_KFIFO(aer_fifo, struct aer_err_source, AER_ERROR_SOURCES_MAX);
50 };
51
52 /* AER stats for the device */
53 struct aer_stats {
54
55 /*
56 * Fields for all AER capable devices. They indicate the errors
57 * "as seen by this device". Note that this may mean that if an
58 * end point is causing problems, the AER counters may increment
59 * at its link partner (e.g. root port) because the errors will be
60 * "seen" by the link partner and not the problematic end point
61 * itself (which may report all counters as 0 as it never saw any
62 * problems).
63 */
64 /* Counters for different type of correctable errors */
65 u64 dev_cor_errs[AER_MAX_TYPEOF_COR_ERRS];
66 /* Counters for different type of fatal uncorrectable errors */
67 u64 dev_fatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS];
68 /* Counters for different type of nonfatal uncorrectable errors */
69 u64 dev_nonfatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS];
70 /* Total number of ERR_COR sent by this device */
71 u64 dev_total_cor_errs;
72 /* Total number of ERR_FATAL sent by this device */
73 u64 dev_total_fatal_errs;
74 /* Total number of ERR_NONFATAL sent by this device */
75 u64 dev_total_nonfatal_errs;
76
77 /*
78 * Fields for Root ports & root complex event collectors only, these
79 * indicate the total number of ERR_COR, ERR_FATAL, and ERR_NONFATAL
80 * messages received by the root port / event collector, INCLUDING the
81 * ones that are generated internally (by the rootport itself)
82 */
83 u64 rootport_total_cor_errs;
84 u64 rootport_total_fatal_errs;
85 u64 rootport_total_nonfatal_errs;
86 };
87
88 #define AER_LOG_TLP_MASKS (PCI_ERR_UNC_POISON_TLP| \
89 PCI_ERR_UNC_ECRC| \
90 PCI_ERR_UNC_UNSUP| \
91 PCI_ERR_UNC_COMP_ABORT| \
92 PCI_ERR_UNC_UNX_COMP| \
93 PCI_ERR_UNC_MALF_TLP)
94
95 #define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \
96 PCI_EXP_RTCTL_SENFEE| \
97 PCI_EXP_RTCTL_SEFEE)
98 #define ROOT_PORT_INTR_ON_MESG_MASK (PCI_ERR_ROOT_CMD_COR_EN| \
99 PCI_ERR_ROOT_CMD_NONFATAL_EN| \
100 PCI_ERR_ROOT_CMD_FATAL_EN)
101 #define ERR_COR_ID(d) (d & 0xffff)
102 #define ERR_UNCOR_ID(d) (d >> 16)
103
104 #define AER_ERR_STATUS_MASK (PCI_ERR_ROOT_UNCOR_RCV | \
105 PCI_ERR_ROOT_COR_RCV | \
106 PCI_ERR_ROOT_MULTI_COR_RCV | \
107 PCI_ERR_ROOT_MULTI_UNCOR_RCV)
108
109 static int pcie_aer_disable;
110 static pci_ers_result_t aer_root_reset(struct pci_dev *dev);
111
pci_no_aer(void)112 void pci_no_aer(void)
113 {
114 pcie_aer_disable = 1;
115 }
116
pci_aer_available(void)117 bool pci_aer_available(void)
118 {
119 return !pcie_aer_disable && pci_msi_enabled();
120 }
121
122 #ifdef CONFIG_PCIE_ECRC
123
124 #define ECRC_POLICY_DEFAULT 0 /* ECRC set by BIOS */
125 #define ECRC_POLICY_OFF 1 /* ECRC off for performance */
126 #define ECRC_POLICY_ON 2 /* ECRC on for data integrity */
127
128 static int ecrc_policy = ECRC_POLICY_DEFAULT;
129
130 static const char * const ecrc_policy_str[] = {
131 [ECRC_POLICY_DEFAULT] = "bios",
132 [ECRC_POLICY_OFF] = "off",
133 [ECRC_POLICY_ON] = "on"
134 };
135
136 /**
137 * enable_ecrc_checking - enable PCIe ECRC checking for a device
138 * @dev: the PCI device
139 *
140 * Returns 0 on success, or negative on failure.
141 */
enable_ecrc_checking(struct pci_dev * dev)142 static int enable_ecrc_checking(struct pci_dev *dev)
143 {
144 int aer = dev->aer_cap;
145 u32 reg32;
146
147 if (!aer)
148 return -ENODEV;
149
150 pci_read_config_dword(dev, aer + PCI_ERR_CAP, ®32);
151 if (reg32 & PCI_ERR_CAP_ECRC_GENC)
152 reg32 |= PCI_ERR_CAP_ECRC_GENE;
153 if (reg32 & PCI_ERR_CAP_ECRC_CHKC)
154 reg32 |= PCI_ERR_CAP_ECRC_CHKE;
155 pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32);
156
157 return 0;
158 }
159
160 /**
161 * disable_ecrc_checking - disables PCIe ECRC checking for a device
162 * @dev: the PCI device
163 *
164 * Returns 0 on success, or negative on failure.
165 */
disable_ecrc_checking(struct pci_dev * dev)166 static int disable_ecrc_checking(struct pci_dev *dev)
167 {
168 int aer = dev->aer_cap;
169 u32 reg32;
170
171 if (!aer)
172 return -ENODEV;
173
174 pci_read_config_dword(dev, aer + PCI_ERR_CAP, ®32);
175 reg32 &= ~(PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE);
176 pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32);
177
178 return 0;
179 }
180
181 /**
182 * pcie_set_ecrc_checking - set/unset PCIe ECRC checking for a device based on global policy
183 * @dev: the PCI device
184 */
pcie_set_ecrc_checking(struct pci_dev * dev)185 void pcie_set_ecrc_checking(struct pci_dev *dev)
186 {
187 switch (ecrc_policy) {
188 case ECRC_POLICY_DEFAULT:
189 return;
190 case ECRC_POLICY_OFF:
191 disable_ecrc_checking(dev);
192 break;
193 case ECRC_POLICY_ON:
194 enable_ecrc_checking(dev);
195 break;
196 default:
197 return;
198 }
199 }
200
201 /**
202 * pcie_ecrc_get_policy - parse kernel command-line ecrc option
203 * @str: ECRC policy from kernel command line to use
204 */
pcie_ecrc_get_policy(char * str)205 void pcie_ecrc_get_policy(char *str)
206 {
207 int i;
208
209 i = match_string(ecrc_policy_str, ARRAY_SIZE(ecrc_policy_str), str);
210 if (i < 0)
211 return;
212
213 ecrc_policy = i;
214 }
215 #endif /* CONFIG_PCIE_ECRC */
216
217 #define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \
218 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE)
219
pcie_aer_is_native(struct pci_dev * dev)220 int pcie_aer_is_native(struct pci_dev *dev)
221 {
222 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
223
224 if (!dev->aer_cap)
225 return 0;
226
227 return pcie_ports_native || host->native_aer;
228 }
229
pci_enable_pcie_error_reporting(struct pci_dev * dev)230 int pci_enable_pcie_error_reporting(struct pci_dev *dev)
231 {
232 int rc;
233
234 if (!pcie_aer_is_native(dev))
235 return -EIO;
236
237 rc = pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS);
238 return pcibios_err_to_errno(rc);
239 }
240 EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting);
241
pci_disable_pcie_error_reporting(struct pci_dev * dev)242 int pci_disable_pcie_error_reporting(struct pci_dev *dev)
243 {
244 int rc;
245
246 if (!pcie_aer_is_native(dev))
247 return -EIO;
248
249 rc = pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS);
250 return pcibios_err_to_errno(rc);
251 }
252 EXPORT_SYMBOL_GPL(pci_disable_pcie_error_reporting);
253
pci_aer_clear_nonfatal_status(struct pci_dev * dev)254 int pci_aer_clear_nonfatal_status(struct pci_dev *dev)
255 {
256 int aer = dev->aer_cap;
257 u32 status, sev;
258
259 if (!pcie_aer_is_native(dev))
260 return -EIO;
261
262 /* Clear status bits for ERR_NONFATAL errors only */
263 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
264 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);
265 status &= ~sev;
266 if (status)
267 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
268
269 return 0;
270 }
271 EXPORT_SYMBOL_GPL(pci_aer_clear_nonfatal_status);
272
pci_aer_clear_fatal_status(struct pci_dev * dev)273 void pci_aer_clear_fatal_status(struct pci_dev *dev)
274 {
275 int aer = dev->aer_cap;
276 u32 status, sev;
277
278 if (!pcie_aer_is_native(dev))
279 return;
280
281 /* Clear status bits for ERR_FATAL errors only */
282 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
283 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);
284 status &= sev;
285 if (status)
286 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
287 }
288
289 /**
290 * pci_aer_raw_clear_status - Clear AER error registers.
291 * @dev: the PCI device
292 *
293 * Clearing AER error status registers unconditionally, regardless of
294 * whether they're owned by firmware or the OS.
295 *
296 * Returns 0 on success, or negative on failure.
297 */
pci_aer_raw_clear_status(struct pci_dev * dev)298 int pci_aer_raw_clear_status(struct pci_dev *dev)
299 {
300 int aer = dev->aer_cap;
301 u32 status;
302 int port_type;
303
304 if (!aer)
305 return -EIO;
306
307 port_type = pci_pcie_type(dev);
308 if (port_type == PCI_EXP_TYPE_ROOT_PORT ||
309 port_type == PCI_EXP_TYPE_RC_EC) {
310 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, &status);
311 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, status);
312 }
313
314 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);
315 pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, status);
316
317 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
318 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
319
320 return 0;
321 }
322
pci_aer_clear_status(struct pci_dev * dev)323 int pci_aer_clear_status(struct pci_dev *dev)
324 {
325 if (!pcie_aer_is_native(dev))
326 return -EIO;
327
328 return pci_aer_raw_clear_status(dev);
329 }
330
pci_save_aer_state(struct pci_dev * dev)331 void pci_save_aer_state(struct pci_dev *dev)
332 {
333 int aer = dev->aer_cap;
334 struct pci_cap_saved_state *save_state;
335 u32 *cap;
336
337 if (!aer)
338 return;
339
340 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR);
341 if (!save_state)
342 return;
343
344 cap = &save_state->cap.data[0];
345 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, cap++);
346 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, cap++);
347 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, cap++);
348 pci_read_config_dword(dev, aer + PCI_ERR_CAP, cap++);
349 if (pcie_cap_has_rtctl(dev))
350 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, cap++);
351 }
352
pci_restore_aer_state(struct pci_dev * dev)353 void pci_restore_aer_state(struct pci_dev *dev)
354 {
355 int aer = dev->aer_cap;
356 struct pci_cap_saved_state *save_state;
357 u32 *cap;
358
359 if (!aer)
360 return;
361
362 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR);
363 if (!save_state)
364 return;
365
366 cap = &save_state->cap.data[0];
367 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, *cap++);
368 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, *cap++);
369 pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, *cap++);
370 pci_write_config_dword(dev, aer + PCI_ERR_CAP, *cap++);
371 if (pcie_cap_has_rtctl(dev))
372 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, *cap++);
373 }
374
pci_aer_init(struct pci_dev * dev)375 void pci_aer_init(struct pci_dev *dev)
376 {
377 int n;
378
379 dev->aer_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
380 if (!dev->aer_cap)
381 return;
382
383 dev->aer_stats = kzalloc(sizeof(struct aer_stats), GFP_KERNEL);
384
385 /*
386 * We save/restore PCI_ERR_UNCOR_MASK, PCI_ERR_UNCOR_SEVER,
387 * PCI_ERR_COR_MASK, and PCI_ERR_CAP. Root and Root Complex Event
388 * Collectors also implement PCI_ERR_ROOT_COMMAND (PCIe r5.0, sec
389 * 7.8.4).
390 */
391 n = pcie_cap_has_rtctl(dev) ? 5 : 4;
392 pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_ERR, sizeof(u32) * n);
393
394 pci_aer_clear_status(dev);
395 }
396
pci_aer_exit(struct pci_dev * dev)397 void pci_aer_exit(struct pci_dev *dev)
398 {
399 kfree(dev->aer_stats);
400 dev->aer_stats = NULL;
401 }
402
403 #define AER_AGENT_RECEIVER 0
404 #define AER_AGENT_REQUESTER 1
405 #define AER_AGENT_COMPLETER 2
406 #define AER_AGENT_TRANSMITTER 3
407
408 #define AER_AGENT_REQUESTER_MASK(t) ((t == AER_CORRECTABLE) ? \
409 0 : (PCI_ERR_UNC_COMP_TIME|PCI_ERR_UNC_UNSUP))
410 #define AER_AGENT_COMPLETER_MASK(t) ((t == AER_CORRECTABLE) ? \
411 0 : PCI_ERR_UNC_COMP_ABORT)
412 #define AER_AGENT_TRANSMITTER_MASK(t) ((t == AER_CORRECTABLE) ? \
413 (PCI_ERR_COR_REP_ROLL|PCI_ERR_COR_REP_TIMER) : 0)
414
415 #define AER_GET_AGENT(t, e) \
416 ((e & AER_AGENT_COMPLETER_MASK(t)) ? AER_AGENT_COMPLETER : \
417 (e & AER_AGENT_REQUESTER_MASK(t)) ? AER_AGENT_REQUESTER : \
418 (e & AER_AGENT_TRANSMITTER_MASK(t)) ? AER_AGENT_TRANSMITTER : \
419 AER_AGENT_RECEIVER)
420
421 #define AER_PHYSICAL_LAYER_ERROR 0
422 #define AER_DATA_LINK_LAYER_ERROR 1
423 #define AER_TRANSACTION_LAYER_ERROR 2
424
425 #define AER_PHYSICAL_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
426 PCI_ERR_COR_RCVR : 0)
427 #define AER_DATA_LINK_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
428 (PCI_ERR_COR_BAD_TLP| \
429 PCI_ERR_COR_BAD_DLLP| \
430 PCI_ERR_COR_REP_ROLL| \
431 PCI_ERR_COR_REP_TIMER) : PCI_ERR_UNC_DLP)
432
433 #define AER_GET_LAYER_ERROR(t, e) \
434 ((e & AER_PHYSICAL_LAYER_ERROR_MASK(t)) ? AER_PHYSICAL_LAYER_ERROR : \
435 (e & AER_DATA_LINK_LAYER_ERROR_MASK(t)) ? AER_DATA_LINK_LAYER_ERROR : \
436 AER_TRANSACTION_LAYER_ERROR)
437
438 /*
439 * AER error strings
440 */
441 static const char *aer_error_severity_string[] = {
442 "Uncorrected (Non-Fatal)",
443 "Uncorrected (Fatal)",
444 "Corrected"
445 };
446
447 static const char *aer_error_layer[] = {
448 "Physical Layer",
449 "Data Link Layer",
450 "Transaction Layer"
451 };
452
453 static const char *aer_correctable_error_string[] = {
454 "RxErr", /* Bit Position 0 */
455 NULL,
456 NULL,
457 NULL,
458 NULL,
459 NULL,
460 "BadTLP", /* Bit Position 6 */
461 "BadDLLP", /* Bit Position 7 */
462 "Rollover", /* Bit Position 8 */
463 NULL,
464 NULL,
465 NULL,
466 "Timeout", /* Bit Position 12 */
467 "NonFatalErr", /* Bit Position 13 */
468 "CorrIntErr", /* Bit Position 14 */
469 "HeaderOF", /* Bit Position 15 */
470 NULL, /* Bit Position 16 */
471 NULL, /* Bit Position 17 */
472 NULL, /* Bit Position 18 */
473 NULL, /* Bit Position 19 */
474 NULL, /* Bit Position 20 */
475 NULL, /* Bit Position 21 */
476 NULL, /* Bit Position 22 */
477 NULL, /* Bit Position 23 */
478 NULL, /* Bit Position 24 */
479 NULL, /* Bit Position 25 */
480 NULL, /* Bit Position 26 */
481 NULL, /* Bit Position 27 */
482 NULL, /* Bit Position 28 */
483 NULL, /* Bit Position 29 */
484 NULL, /* Bit Position 30 */
485 NULL, /* Bit Position 31 */
486 };
487
488 static const char *aer_uncorrectable_error_string[] = {
489 "Undefined", /* Bit Position 0 */
490 NULL,
491 NULL,
492 NULL,
493 "DLP", /* Bit Position 4 */
494 "SDES", /* Bit Position 5 */
495 NULL,
496 NULL,
497 NULL,
498 NULL,
499 NULL,
500 NULL,
501 "TLP", /* Bit Position 12 */
502 "FCP", /* Bit Position 13 */
503 "CmpltTO", /* Bit Position 14 */
504 "CmpltAbrt", /* Bit Position 15 */
505 "UnxCmplt", /* Bit Position 16 */
506 "RxOF", /* Bit Position 17 */
507 "MalfTLP", /* Bit Position 18 */
508 "ECRC", /* Bit Position 19 */
509 "UnsupReq", /* Bit Position 20 */
510 "ACSViol", /* Bit Position 21 */
511 "UncorrIntErr", /* Bit Position 22 */
512 "BlockedTLP", /* Bit Position 23 */
513 "AtomicOpBlocked", /* Bit Position 24 */
514 "TLPBlockedErr", /* Bit Position 25 */
515 "PoisonTLPBlocked", /* Bit Position 26 */
516 NULL, /* Bit Position 27 */
517 NULL, /* Bit Position 28 */
518 NULL, /* Bit Position 29 */
519 NULL, /* Bit Position 30 */
520 NULL, /* Bit Position 31 */
521 };
522
523 static const char *aer_agent_string[] = {
524 "Receiver ID",
525 "Requester ID",
526 "Completer ID",
527 "Transmitter ID"
528 };
529
530 #define aer_stats_dev_attr(name, stats_array, strings_array, \
531 total_string, total_field) \
532 static ssize_t \
533 name##_show(struct device *dev, struct device_attribute *attr, \
534 char *buf) \
535 { \
536 unsigned int i; \
537 struct pci_dev *pdev = to_pci_dev(dev); \
538 u64 *stats = pdev->aer_stats->stats_array; \
539 size_t len = 0; \
540 \
541 for (i = 0; i < ARRAY_SIZE(pdev->aer_stats->stats_array); i++) {\
542 if (strings_array[i]) \
543 len += sysfs_emit_at(buf, len, "%s %llu\n", \
544 strings_array[i], \
545 stats[i]); \
546 else if (stats[i]) \
547 len += sysfs_emit_at(buf, len, \
548 #stats_array "_bit[%d] %llu\n",\
549 i, stats[i]); \
550 } \
551 len += sysfs_emit_at(buf, len, "TOTAL_%s %llu\n", total_string, \
552 pdev->aer_stats->total_field); \
553 return len; \
554 } \
555 static DEVICE_ATTR_RO(name)
556
557 aer_stats_dev_attr(aer_dev_correctable, dev_cor_errs,
558 aer_correctable_error_string, "ERR_COR",
559 dev_total_cor_errs);
560 aer_stats_dev_attr(aer_dev_fatal, dev_fatal_errs,
561 aer_uncorrectable_error_string, "ERR_FATAL",
562 dev_total_fatal_errs);
563 aer_stats_dev_attr(aer_dev_nonfatal, dev_nonfatal_errs,
564 aer_uncorrectable_error_string, "ERR_NONFATAL",
565 dev_total_nonfatal_errs);
566
567 #define aer_stats_rootport_attr(name, field) \
568 static ssize_t \
569 name##_show(struct device *dev, struct device_attribute *attr, \
570 char *buf) \
571 { \
572 struct pci_dev *pdev = to_pci_dev(dev); \
573 return sysfs_emit(buf, "%llu\n", pdev->aer_stats->field); \
574 } \
575 static DEVICE_ATTR_RO(name)
576
577 aer_stats_rootport_attr(aer_rootport_total_err_cor,
578 rootport_total_cor_errs);
579 aer_stats_rootport_attr(aer_rootport_total_err_fatal,
580 rootport_total_fatal_errs);
581 aer_stats_rootport_attr(aer_rootport_total_err_nonfatal,
582 rootport_total_nonfatal_errs);
583
584 static struct attribute *aer_stats_attrs[] __ro_after_init = {
585 &dev_attr_aer_dev_correctable.attr,
586 &dev_attr_aer_dev_fatal.attr,
587 &dev_attr_aer_dev_nonfatal.attr,
588 &dev_attr_aer_rootport_total_err_cor.attr,
589 &dev_attr_aer_rootport_total_err_fatal.attr,
590 &dev_attr_aer_rootport_total_err_nonfatal.attr,
591 NULL
592 };
593
aer_stats_attrs_are_visible(struct kobject * kobj,struct attribute * a,int n)594 static umode_t aer_stats_attrs_are_visible(struct kobject *kobj,
595 struct attribute *a, int n)
596 {
597 struct device *dev = kobj_to_dev(kobj);
598 struct pci_dev *pdev = to_pci_dev(dev);
599
600 if (!pdev->aer_stats)
601 return 0;
602
603 if ((a == &dev_attr_aer_rootport_total_err_cor.attr ||
604 a == &dev_attr_aer_rootport_total_err_fatal.attr ||
605 a == &dev_attr_aer_rootport_total_err_nonfatal.attr) &&
606 ((pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT) &&
607 (pci_pcie_type(pdev) != PCI_EXP_TYPE_RC_EC)))
608 return 0;
609
610 return a->mode;
611 }
612
613 const struct attribute_group aer_stats_attr_group = {
614 .attrs = aer_stats_attrs,
615 .is_visible = aer_stats_attrs_are_visible,
616 };
617
pci_dev_aer_stats_incr(struct pci_dev * pdev,struct aer_err_info * info)618 static void pci_dev_aer_stats_incr(struct pci_dev *pdev,
619 struct aer_err_info *info)
620 {
621 unsigned long status = info->status & ~info->mask;
622 int i, max = -1;
623 u64 *counter = NULL;
624 struct aer_stats *aer_stats = pdev->aer_stats;
625
626 if (!aer_stats)
627 return;
628
629 switch (info->severity) {
630 case AER_CORRECTABLE:
631 aer_stats->dev_total_cor_errs++;
632 counter = &aer_stats->dev_cor_errs[0];
633 max = AER_MAX_TYPEOF_COR_ERRS;
634 break;
635 case AER_NONFATAL:
636 aer_stats->dev_total_nonfatal_errs++;
637 counter = &aer_stats->dev_nonfatal_errs[0];
638 max = AER_MAX_TYPEOF_UNCOR_ERRS;
639 break;
640 case AER_FATAL:
641 aer_stats->dev_total_fatal_errs++;
642 counter = &aer_stats->dev_fatal_errs[0];
643 max = AER_MAX_TYPEOF_UNCOR_ERRS;
644 break;
645 }
646
647 for_each_set_bit(i, &status, max)
648 counter[i]++;
649 }
650
pci_rootport_aer_stats_incr(struct pci_dev * pdev,struct aer_err_source * e_src)651 static void pci_rootport_aer_stats_incr(struct pci_dev *pdev,
652 struct aer_err_source *e_src)
653 {
654 struct aer_stats *aer_stats = pdev->aer_stats;
655
656 if (!aer_stats)
657 return;
658
659 if (e_src->status & PCI_ERR_ROOT_COR_RCV)
660 aer_stats->rootport_total_cor_errs++;
661
662 if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) {
663 if (e_src->status & PCI_ERR_ROOT_FATAL_RCV)
664 aer_stats->rootport_total_fatal_errs++;
665 else
666 aer_stats->rootport_total_nonfatal_errs++;
667 }
668 }
669
__print_tlp_header(struct pci_dev * dev,struct aer_header_log_regs * t)670 static void __print_tlp_header(struct pci_dev *dev,
671 struct aer_header_log_regs *t)
672 {
673 pci_err(dev, " TLP Header: %08x %08x %08x %08x\n",
674 t->dw0, t->dw1, t->dw2, t->dw3);
675 }
676
__aer_print_error(struct pci_dev * dev,struct aer_err_info * info)677 static void __aer_print_error(struct pci_dev *dev,
678 struct aer_err_info *info)
679 {
680 const char **strings;
681 unsigned long status = info->status & ~info->mask;
682 const char *level, *errmsg;
683 int i;
684
685 if (info->severity == AER_CORRECTABLE) {
686 strings = aer_correctable_error_string;
687 level = KERN_WARNING;
688 } else {
689 strings = aer_uncorrectable_error_string;
690 level = KERN_ERR;
691 }
692
693 for_each_set_bit(i, &status, 32) {
694 errmsg = strings[i];
695 if (!errmsg)
696 errmsg = "Unknown Error Bit";
697
698 pci_printk(level, dev, " [%2d] %-22s%s\n", i, errmsg,
699 info->first_error == i ? " (First)" : "");
700 }
701 pci_dev_aer_stats_incr(dev, info);
702 }
703
aer_print_error(struct pci_dev * dev,struct aer_err_info * info)704 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info)
705 {
706 int layer, agent;
707 int id = ((dev->bus->number << 8) | dev->devfn);
708 const char *level;
709
710 if (!info->status) {
711 pci_err(dev, "PCIe Bus Error: severity=%s, type=Inaccessible, (Unregistered Agent ID)\n",
712 aer_error_severity_string[info->severity]);
713 goto out;
714 }
715
716 layer = AER_GET_LAYER_ERROR(info->severity, info->status);
717 agent = AER_GET_AGENT(info->severity, info->status);
718
719 level = (info->severity == AER_CORRECTABLE) ? KERN_WARNING : KERN_ERR;
720
721 pci_printk(level, dev, "PCIe Bus Error: severity=%s, type=%s, (%s)\n",
722 aer_error_severity_string[info->severity],
723 aer_error_layer[layer], aer_agent_string[agent]);
724
725 pci_printk(level, dev, " device [%04x:%04x] error status/mask=%08x/%08x\n",
726 dev->vendor, dev->device, info->status, info->mask);
727
728 __aer_print_error(dev, info);
729
730 if (info->tlp_header_valid)
731 __print_tlp_header(dev, &info->tlp);
732
733 out:
734 if (info->id && info->error_dev_num > 1 && info->id == id)
735 pci_err(dev, " Error of this Agent is reported first\n");
736
737 trace_aer_event(dev_name(&dev->dev), (info->status & ~info->mask),
738 info->severity, info->tlp_header_valid, &info->tlp);
739 }
740
aer_print_port_info(struct pci_dev * dev,struct aer_err_info * info)741 static void aer_print_port_info(struct pci_dev *dev, struct aer_err_info *info)
742 {
743 u8 bus = info->id >> 8;
744 u8 devfn = info->id & 0xff;
745
746 pci_info(dev, "%s%s error received: %04x:%02x:%02x.%d\n",
747 info->multi_error_valid ? "Multiple " : "",
748 aer_error_severity_string[info->severity],
749 pci_domain_nr(dev->bus), bus, PCI_SLOT(devfn),
750 PCI_FUNC(devfn));
751 }
752
753 #ifdef CONFIG_ACPI_APEI_PCIEAER
cper_severity_to_aer(int cper_severity)754 int cper_severity_to_aer(int cper_severity)
755 {
756 switch (cper_severity) {
757 case CPER_SEV_RECOVERABLE:
758 return AER_NONFATAL;
759 case CPER_SEV_FATAL:
760 return AER_FATAL;
761 default:
762 return AER_CORRECTABLE;
763 }
764 }
765 EXPORT_SYMBOL_GPL(cper_severity_to_aer);
766
cper_print_aer(struct pci_dev * dev,int aer_severity,struct aer_capability_regs * aer)767 void cper_print_aer(struct pci_dev *dev, int aer_severity,
768 struct aer_capability_regs *aer)
769 {
770 int layer, agent, tlp_header_valid = 0;
771 u32 status, mask;
772 struct aer_err_info info;
773
774 if (aer_severity == AER_CORRECTABLE) {
775 status = aer->cor_status;
776 mask = aer->cor_mask;
777 } else {
778 status = aer->uncor_status;
779 mask = aer->uncor_mask;
780 tlp_header_valid = status & AER_LOG_TLP_MASKS;
781 }
782
783 layer = AER_GET_LAYER_ERROR(aer_severity, status);
784 agent = AER_GET_AGENT(aer_severity, status);
785
786 memset(&info, 0, sizeof(info));
787 info.severity = aer_severity;
788 info.status = status;
789 info.mask = mask;
790 info.first_error = PCI_ERR_CAP_FEP(aer->cap_control);
791
792 pci_err(dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status, mask);
793 __aer_print_error(dev, &info);
794 pci_err(dev, "aer_layer=%s, aer_agent=%s\n",
795 aer_error_layer[layer], aer_agent_string[agent]);
796
797 if (aer_severity != AER_CORRECTABLE)
798 pci_err(dev, "aer_uncor_severity: 0x%08x\n",
799 aer->uncor_severity);
800
801 if (tlp_header_valid)
802 __print_tlp_header(dev, &aer->header_log);
803
804 trace_aer_event(dev_name(&dev->dev), (status & ~mask),
805 aer_severity, tlp_header_valid, &aer->header_log);
806 }
807 #endif
808
809 /**
810 * add_error_device - list device to be handled
811 * @e_info: pointer to error info
812 * @dev: pointer to pci_dev to be added
813 */
add_error_device(struct aer_err_info * e_info,struct pci_dev * dev)814 static int add_error_device(struct aer_err_info *e_info, struct pci_dev *dev)
815 {
816 if (e_info->error_dev_num < AER_MAX_MULTI_ERR_DEVICES) {
817 e_info->dev[e_info->error_dev_num] = pci_dev_get(dev);
818 e_info->error_dev_num++;
819 return 0;
820 }
821 return -ENOSPC;
822 }
823
824 /**
825 * is_error_source - check whether the device is source of reported error
826 * @dev: pointer to pci_dev to be checked
827 * @e_info: pointer to reported error info
828 */
is_error_source(struct pci_dev * dev,struct aer_err_info * e_info)829 static bool is_error_source(struct pci_dev *dev, struct aer_err_info *e_info)
830 {
831 int aer = dev->aer_cap;
832 u32 status, mask;
833 u16 reg16;
834
835 /*
836 * When bus id is equal to 0, it might be a bad id
837 * reported by root port.
838 */
839 if ((PCI_BUS_NUM(e_info->id) != 0) &&
840 !(dev->bus->bus_flags & PCI_BUS_FLAGS_NO_AERSID)) {
841 /* Device ID match? */
842 if (e_info->id == ((dev->bus->number << 8) | dev->devfn))
843 return true;
844
845 /* Continue id comparing if there is no multiple error */
846 if (!e_info->multi_error_valid)
847 return false;
848 }
849
850 /*
851 * When either
852 * 1) bus id is equal to 0. Some ports might lose the bus
853 * id of error source id;
854 * 2) bus flag PCI_BUS_FLAGS_NO_AERSID is set
855 * 3) There are multiple errors and prior ID comparing fails;
856 * We check AER status registers to find possible reporter.
857 */
858 if (atomic_read(&dev->enable_cnt) == 0)
859 return false;
860
861 /* Check if AER is enabled */
862 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, ®16);
863 if (!(reg16 & PCI_EXP_AER_FLAGS))
864 return false;
865
866 if (!aer)
867 return false;
868
869 /* Check if error is recorded */
870 if (e_info->severity == AER_CORRECTABLE) {
871 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);
872 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask);
873 } else {
874 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
875 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask);
876 }
877 if (status & ~mask)
878 return true;
879
880 return false;
881 }
882
find_device_iter(struct pci_dev * dev,void * data)883 static int find_device_iter(struct pci_dev *dev, void *data)
884 {
885 struct aer_err_info *e_info = (struct aer_err_info *)data;
886
887 if (is_error_source(dev, e_info)) {
888 /* List this device */
889 if (add_error_device(e_info, dev)) {
890 /* We cannot handle more... Stop iteration */
891 /* TODO: Should print error message here? */
892 return 1;
893 }
894
895 /* If there is only a single error, stop iteration */
896 if (!e_info->multi_error_valid)
897 return 1;
898 }
899 return 0;
900 }
901
902 /**
903 * find_source_device - search through device hierarchy for source device
904 * @parent: pointer to Root Port pci_dev data structure
905 * @e_info: including detailed error information such like id
906 *
907 * Return true if found.
908 *
909 * Invoked by DPC when error is detected at the Root Port.
910 * Caller of this function must set id, severity, and multi_error_valid of
911 * struct aer_err_info pointed by @e_info properly. This function must fill
912 * e_info->error_dev_num and e_info->dev[], based on the given information.
913 */
find_source_device(struct pci_dev * parent,struct aer_err_info * e_info)914 static bool find_source_device(struct pci_dev *parent,
915 struct aer_err_info *e_info)
916 {
917 struct pci_dev *dev = parent;
918 int result;
919
920 /* Must reset in this function */
921 e_info->error_dev_num = 0;
922
923 /* Is Root Port an agent that sends error message? */
924 result = find_device_iter(dev, e_info);
925 if (result)
926 return true;
927
928 if (pci_pcie_type(parent) == PCI_EXP_TYPE_RC_EC)
929 pcie_walk_rcec(parent, find_device_iter, e_info);
930 else
931 pci_walk_bus(parent->subordinate, find_device_iter, e_info);
932
933 if (!e_info->error_dev_num) {
934 pci_info(parent, "can't find device of ID%04x\n", e_info->id);
935 return false;
936 }
937 return true;
938 }
939
940 /**
941 * handle_error_source - handle logging error into an event log
942 * @dev: pointer to pci_dev data structure of error source device
943 * @info: comprehensive error information
944 *
945 * Invoked when an error being detected by Root Port.
946 */
handle_error_source(struct pci_dev * dev,struct aer_err_info * info)947 static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info)
948 {
949 int aer = dev->aer_cap;
950
951 if (info->severity == AER_CORRECTABLE) {
952 /*
953 * Correctable error does not need software intervention.
954 * No need to go through error recovery process.
955 */
956 if (aer)
957 pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS,
958 info->status);
959 if (pcie_aer_is_native(dev))
960 pcie_clear_device_status(dev);
961 } else if (info->severity == AER_NONFATAL)
962 pcie_do_recovery(dev, pci_channel_io_normal, aer_root_reset);
963 else if (info->severity == AER_FATAL)
964 pcie_do_recovery(dev, pci_channel_io_frozen, aer_root_reset);
965 pci_dev_put(dev);
966 }
967
968 #ifdef CONFIG_ACPI_APEI_PCIEAER
969
970 #define AER_RECOVER_RING_ORDER 4
971 #define AER_RECOVER_RING_SIZE (1 << AER_RECOVER_RING_ORDER)
972
973 struct aer_recover_entry {
974 u8 bus;
975 u8 devfn;
976 u16 domain;
977 int severity;
978 struct aer_capability_regs *regs;
979 };
980
981 static DEFINE_KFIFO(aer_recover_ring, struct aer_recover_entry,
982 AER_RECOVER_RING_SIZE);
983
aer_recover_work_func(struct work_struct * work)984 static void aer_recover_work_func(struct work_struct *work)
985 {
986 struct aer_recover_entry entry;
987 struct pci_dev *pdev;
988
989 while (kfifo_get(&aer_recover_ring, &entry)) {
990 pdev = pci_get_domain_bus_and_slot(entry.domain, entry.bus,
991 entry.devfn);
992 if (!pdev) {
993 pr_err("no pci_dev for %04x:%02x:%02x.%x\n",
994 entry.domain, entry.bus,
995 PCI_SLOT(entry.devfn), PCI_FUNC(entry.devfn));
996 continue;
997 }
998 cper_print_aer(pdev, entry.severity, entry.regs);
999 if (entry.severity == AER_NONFATAL)
1000 pcie_do_recovery(pdev, pci_channel_io_normal,
1001 aer_root_reset);
1002 else if (entry.severity == AER_FATAL)
1003 pcie_do_recovery(pdev, pci_channel_io_frozen,
1004 aer_root_reset);
1005 pci_dev_put(pdev);
1006 }
1007 }
1008
1009 /*
1010 * Mutual exclusion for writers of aer_recover_ring, reader side don't
1011 * need lock, because there is only one reader and lock is not needed
1012 * between reader and writer.
1013 */
1014 static DEFINE_SPINLOCK(aer_recover_ring_lock);
1015 static DECLARE_WORK(aer_recover_work, aer_recover_work_func);
1016
aer_recover_queue(int domain,unsigned int bus,unsigned int devfn,int severity,struct aer_capability_regs * aer_regs)1017 void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
1018 int severity, struct aer_capability_regs *aer_regs)
1019 {
1020 struct aer_recover_entry entry = {
1021 .bus = bus,
1022 .devfn = devfn,
1023 .domain = domain,
1024 .severity = severity,
1025 .regs = aer_regs,
1026 };
1027
1028 if (kfifo_in_spinlocked(&aer_recover_ring, &entry, 1,
1029 &aer_recover_ring_lock))
1030 schedule_work(&aer_recover_work);
1031 else
1032 pr_err("buffer overflow in recovery for %04x:%02x:%02x.%x\n",
1033 domain, bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
1034 }
1035 EXPORT_SYMBOL_GPL(aer_recover_queue);
1036 #endif
1037
1038 /**
1039 * aer_get_device_error_info - read error status from dev and store it to info
1040 * @dev: pointer to the device expected to have a error record
1041 * @info: pointer to structure to store the error record
1042 *
1043 * Return 1 on success, 0 on error.
1044 *
1045 * Note that @info is reused among all error devices. Clear fields properly.
1046 */
aer_get_device_error_info(struct pci_dev * dev,struct aer_err_info * info)1047 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info)
1048 {
1049 int type = pci_pcie_type(dev);
1050 int aer = dev->aer_cap;
1051 int temp;
1052
1053 /* Must reset in this function */
1054 info->status = 0;
1055 info->tlp_header_valid = 0;
1056
1057 /* The device might not support AER */
1058 if (!aer)
1059 return 0;
1060
1061 if (info->severity == AER_CORRECTABLE) {
1062 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS,
1063 &info->status);
1064 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK,
1065 &info->mask);
1066 if (!(info->status & ~info->mask))
1067 return 0;
1068 } else if (type == PCI_EXP_TYPE_ROOT_PORT ||
1069 type == PCI_EXP_TYPE_RC_EC ||
1070 type == PCI_EXP_TYPE_DOWNSTREAM ||
1071 info->severity == AER_NONFATAL) {
1072
1073 /* Link is still healthy for IO reads */
1074 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS,
1075 &info->status);
1076 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK,
1077 &info->mask);
1078 if (!(info->status & ~info->mask))
1079 return 0;
1080
1081 /* Get First Error Pointer */
1082 pci_read_config_dword(dev, aer + PCI_ERR_CAP, &temp);
1083 info->first_error = PCI_ERR_CAP_FEP(temp);
1084
1085 if (info->status & AER_LOG_TLP_MASKS) {
1086 info->tlp_header_valid = 1;
1087 pci_read_config_dword(dev,
1088 aer + PCI_ERR_HEADER_LOG, &info->tlp.dw0);
1089 pci_read_config_dword(dev,
1090 aer + PCI_ERR_HEADER_LOG + 4, &info->tlp.dw1);
1091 pci_read_config_dword(dev,
1092 aer + PCI_ERR_HEADER_LOG + 8, &info->tlp.dw2);
1093 pci_read_config_dword(dev,
1094 aer + PCI_ERR_HEADER_LOG + 12, &info->tlp.dw3);
1095 }
1096 }
1097
1098 return 1;
1099 }
1100
aer_process_err_devices(struct aer_err_info * e_info)1101 static inline void aer_process_err_devices(struct aer_err_info *e_info)
1102 {
1103 int i;
1104
1105 /* Report all before handle them, not to lost records by reset etc. */
1106 for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) {
1107 if (aer_get_device_error_info(e_info->dev[i], e_info))
1108 aer_print_error(e_info->dev[i], e_info);
1109 }
1110 for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) {
1111 if (aer_get_device_error_info(e_info->dev[i], e_info))
1112 handle_error_source(e_info->dev[i], e_info);
1113 }
1114 }
1115
1116 /**
1117 * aer_isr_one_error - consume an error detected by root port
1118 * @rpc: pointer to the root port which holds an error
1119 * @e_src: pointer to an error source
1120 */
aer_isr_one_error(struct aer_rpc * rpc,struct aer_err_source * e_src)1121 static void aer_isr_one_error(struct aer_rpc *rpc,
1122 struct aer_err_source *e_src)
1123 {
1124 struct pci_dev *pdev = rpc->rpd;
1125 struct aer_err_info e_info;
1126
1127 pci_rootport_aer_stats_incr(pdev, e_src);
1128
1129 /*
1130 * There is a possibility that both correctable error and
1131 * uncorrectable error being logged. Report correctable error first.
1132 */
1133 if (e_src->status & PCI_ERR_ROOT_COR_RCV) {
1134 e_info.id = ERR_COR_ID(e_src->id);
1135 e_info.severity = AER_CORRECTABLE;
1136
1137 if (e_src->status & PCI_ERR_ROOT_MULTI_COR_RCV)
1138 e_info.multi_error_valid = 1;
1139 else
1140 e_info.multi_error_valid = 0;
1141 aer_print_port_info(pdev, &e_info);
1142
1143 if (find_source_device(pdev, &e_info))
1144 aer_process_err_devices(&e_info);
1145 }
1146
1147 if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) {
1148 e_info.id = ERR_UNCOR_ID(e_src->id);
1149
1150 if (e_src->status & PCI_ERR_ROOT_FATAL_RCV)
1151 e_info.severity = AER_FATAL;
1152 else
1153 e_info.severity = AER_NONFATAL;
1154
1155 if (e_src->status & PCI_ERR_ROOT_MULTI_UNCOR_RCV)
1156 e_info.multi_error_valid = 1;
1157 else
1158 e_info.multi_error_valid = 0;
1159
1160 aer_print_port_info(pdev, &e_info);
1161
1162 if (find_source_device(pdev, &e_info))
1163 aer_process_err_devices(&e_info);
1164 }
1165 }
1166
1167 /**
1168 * aer_isr - consume errors detected by root port
1169 * @irq: IRQ assigned to Root Port
1170 * @context: pointer to Root Port data structure
1171 *
1172 * Invoked, as DPC, when root port records new detected error
1173 */
aer_isr(int irq,void * context)1174 static irqreturn_t aer_isr(int irq, void *context)
1175 {
1176 struct pcie_device *dev = (struct pcie_device *)context;
1177 struct aer_rpc *rpc = get_service_data(dev);
1178 struct aer_err_source e_src;
1179
1180 if (kfifo_is_empty(&rpc->aer_fifo))
1181 return IRQ_NONE;
1182
1183 while (kfifo_get(&rpc->aer_fifo, &e_src))
1184 aer_isr_one_error(rpc, &e_src);
1185 return IRQ_HANDLED;
1186 }
1187
1188 /**
1189 * aer_irq - Root Port's ISR
1190 * @irq: IRQ assigned to Root Port
1191 * @context: pointer to Root Port data structure
1192 *
1193 * Invoked when Root Port detects AER messages.
1194 */
aer_irq(int irq,void * context)1195 static irqreturn_t aer_irq(int irq, void *context)
1196 {
1197 struct pcie_device *pdev = (struct pcie_device *)context;
1198 struct aer_rpc *rpc = get_service_data(pdev);
1199 struct pci_dev *rp = rpc->rpd;
1200 int aer = rp->aer_cap;
1201 struct aer_err_source e_src = {};
1202
1203 pci_read_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, &e_src.status);
1204 if (!(e_src.status & AER_ERR_STATUS_MASK))
1205 return IRQ_NONE;
1206
1207 pci_read_config_dword(rp, aer + PCI_ERR_ROOT_ERR_SRC, &e_src.id);
1208 pci_write_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, e_src.status);
1209
1210 if (!kfifo_put(&rpc->aer_fifo, e_src))
1211 return IRQ_HANDLED;
1212
1213 return IRQ_WAKE_THREAD;
1214 }
1215
set_device_error_reporting(struct pci_dev * dev,void * data)1216 static int set_device_error_reporting(struct pci_dev *dev, void *data)
1217 {
1218 bool enable = *((bool *)data);
1219 int type = pci_pcie_type(dev);
1220
1221 if ((type == PCI_EXP_TYPE_ROOT_PORT) ||
1222 (type == PCI_EXP_TYPE_RC_EC) ||
1223 (type == PCI_EXP_TYPE_UPSTREAM) ||
1224 (type == PCI_EXP_TYPE_DOWNSTREAM)) {
1225 if (enable)
1226 pci_enable_pcie_error_reporting(dev);
1227 else
1228 pci_disable_pcie_error_reporting(dev);
1229 }
1230
1231 if (enable)
1232 pcie_set_ecrc_checking(dev);
1233
1234 return 0;
1235 }
1236
1237 /**
1238 * set_downstream_devices_error_reporting - enable/disable the error reporting bits on the root port and its downstream ports.
1239 * @dev: pointer to root port's pci_dev data structure
1240 * @enable: true = enable error reporting, false = disable error reporting.
1241 */
set_downstream_devices_error_reporting(struct pci_dev * dev,bool enable)1242 static void set_downstream_devices_error_reporting(struct pci_dev *dev,
1243 bool enable)
1244 {
1245 set_device_error_reporting(dev, &enable);
1246
1247 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC)
1248 pcie_walk_rcec(dev, set_device_error_reporting, &enable);
1249 else if (dev->subordinate)
1250 pci_walk_bus(dev->subordinate, set_device_error_reporting,
1251 &enable);
1252
1253 }
1254
1255 /**
1256 * aer_enable_rootport - enable Root Port's interrupts when receiving messages
1257 * @rpc: pointer to a Root Port data structure
1258 *
1259 * Invoked when PCIe bus loads AER service driver.
1260 */
aer_enable_rootport(struct aer_rpc * rpc)1261 static void aer_enable_rootport(struct aer_rpc *rpc)
1262 {
1263 struct pci_dev *pdev = rpc->rpd;
1264 int aer = pdev->aer_cap;
1265 u16 reg16;
1266 u32 reg32;
1267
1268 /* Clear PCIe Capability's Device Status */
1269 pcie_capability_read_word(pdev, PCI_EXP_DEVSTA, ®16);
1270 pcie_capability_write_word(pdev, PCI_EXP_DEVSTA, reg16);
1271
1272 /* Disable system error generation in response to error messages */
1273 pcie_capability_clear_word(pdev, PCI_EXP_RTCTL,
1274 SYSTEM_ERROR_INTR_ON_MESG_MASK);
1275
1276 /* Clear error status */
1277 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, ®32);
1278 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32);
1279 pci_read_config_dword(pdev, aer + PCI_ERR_COR_STATUS, ®32);
1280 pci_write_config_dword(pdev, aer + PCI_ERR_COR_STATUS, reg32);
1281 pci_read_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, ®32);
1282 pci_write_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, reg32);
1283
1284 /*
1285 * Enable error reporting for the root port device and downstream port
1286 * devices.
1287 */
1288 set_downstream_devices_error_reporting(pdev, true);
1289
1290 /* Enable Root Port's interrupt in response to error messages */
1291 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, ®32);
1292 reg32 |= ROOT_PORT_INTR_ON_MESG_MASK;
1293 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32);
1294 }
1295
1296 /**
1297 * aer_disable_rootport - disable Root Port's interrupts when receiving messages
1298 * @rpc: pointer to a Root Port data structure
1299 *
1300 * Invoked when PCIe bus unloads AER service driver.
1301 */
aer_disable_rootport(struct aer_rpc * rpc)1302 static void aer_disable_rootport(struct aer_rpc *rpc)
1303 {
1304 struct pci_dev *pdev = rpc->rpd;
1305 int aer = pdev->aer_cap;
1306 u32 reg32;
1307
1308 /*
1309 * Disable error reporting for the root port device and downstream port
1310 * devices.
1311 */
1312 set_downstream_devices_error_reporting(pdev, false);
1313
1314 /* Disable Root's interrupt in response to error messages */
1315 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, ®32);
1316 reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK;
1317 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32);
1318
1319 /* Clear Root's error status reg */
1320 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, ®32);
1321 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32);
1322 }
1323
1324 /**
1325 * aer_remove - clean up resources
1326 * @dev: pointer to the pcie_dev data structure
1327 *
1328 * Invoked when PCI Express bus unloads or AER probe fails.
1329 */
aer_remove(struct pcie_device * dev)1330 static void aer_remove(struct pcie_device *dev)
1331 {
1332 struct aer_rpc *rpc = get_service_data(dev);
1333
1334 aer_disable_rootport(rpc);
1335 }
1336
1337 /**
1338 * aer_probe - initialize resources
1339 * @dev: pointer to the pcie_dev data structure
1340 *
1341 * Invoked when PCI Express bus loads AER service driver.
1342 */
aer_probe(struct pcie_device * dev)1343 static int aer_probe(struct pcie_device *dev)
1344 {
1345 int status;
1346 struct aer_rpc *rpc;
1347 struct device *device = &dev->device;
1348 struct pci_dev *port = dev->port;
1349
1350 BUILD_BUG_ON(ARRAY_SIZE(aer_correctable_error_string) <
1351 AER_MAX_TYPEOF_COR_ERRS);
1352 BUILD_BUG_ON(ARRAY_SIZE(aer_uncorrectable_error_string) <
1353 AER_MAX_TYPEOF_UNCOR_ERRS);
1354
1355 /* Limit to Root Ports or Root Complex Event Collectors */
1356 if ((pci_pcie_type(port) != PCI_EXP_TYPE_RC_EC) &&
1357 (pci_pcie_type(port) != PCI_EXP_TYPE_ROOT_PORT))
1358 return -ENODEV;
1359
1360 rpc = devm_kzalloc(device, sizeof(struct aer_rpc), GFP_KERNEL);
1361 if (!rpc)
1362 return -ENOMEM;
1363
1364 rpc->rpd = port;
1365 INIT_KFIFO(rpc->aer_fifo);
1366 set_service_data(dev, rpc);
1367
1368 status = devm_request_threaded_irq(device, dev->irq, aer_irq, aer_isr,
1369 IRQF_SHARED, "aerdrv", dev);
1370 if (status) {
1371 pci_err(port, "request AER IRQ %d failed\n", dev->irq);
1372 return status;
1373 }
1374
1375 aer_enable_rootport(rpc);
1376 pci_info(port, "enabled with IRQ %d\n", dev->irq);
1377 return 0;
1378 }
1379
1380 /**
1381 * aer_root_reset - reset Root Port hierarchy, RCEC, or RCiEP
1382 * @dev: pointer to Root Port, RCEC, or RCiEP
1383 *
1384 * Invoked by Port Bus driver when performing reset.
1385 */
aer_root_reset(struct pci_dev * dev)1386 static pci_ers_result_t aer_root_reset(struct pci_dev *dev)
1387 {
1388 int type = pci_pcie_type(dev);
1389 struct pci_dev *root;
1390 int aer;
1391 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
1392 u32 reg32;
1393 int rc;
1394
1395 /*
1396 * Only Root Ports and RCECs have AER Root Command and Root Status
1397 * registers. If "dev" is an RCiEP, the relevant registers are in
1398 * the RCEC.
1399 */
1400 if (type == PCI_EXP_TYPE_RC_END)
1401 root = dev->rcec;
1402 else
1403 root = pcie_find_root_port(dev);
1404
1405 /*
1406 * If the platform retained control of AER, an RCiEP may not have
1407 * an RCEC visible to us, so dev->rcec ("root") may be NULL. In
1408 * that case, firmware is responsible for these registers.
1409 */
1410 aer = root ? root->aer_cap : 0;
1411
1412 if ((host->native_aer || pcie_ports_native) && aer) {
1413 /* Disable Root's interrupt in response to error messages */
1414 pci_read_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, ®32);
1415 reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK;
1416 pci_write_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, reg32);
1417 }
1418
1419 if (type == PCI_EXP_TYPE_RC_EC || type == PCI_EXP_TYPE_RC_END) {
1420 rc = pcie_reset_flr(dev, PCI_RESET_DO_RESET);
1421 if (!rc)
1422 pci_info(dev, "has been reset\n");
1423 else
1424 pci_info(dev, "not reset (no FLR support: %d)\n", rc);
1425 } else {
1426 rc = pci_bus_error_reset(dev);
1427 pci_info(dev, "%s Port link has been reset (%d)\n",
1428 pci_is_root_bus(dev->bus) ? "Root" : "Downstream", rc);
1429 }
1430
1431 if ((host->native_aer || pcie_ports_native) && aer) {
1432 /* Clear Root Error Status */
1433 pci_read_config_dword(root, aer + PCI_ERR_ROOT_STATUS, ®32);
1434 pci_write_config_dword(root, aer + PCI_ERR_ROOT_STATUS, reg32);
1435
1436 /* Enable Root Port's interrupt in response to error messages */
1437 pci_read_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, ®32);
1438 reg32 |= ROOT_PORT_INTR_ON_MESG_MASK;
1439 pci_write_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, reg32);
1440 }
1441
1442 return rc ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1443 }
1444
1445 static struct pcie_port_service_driver aerdriver = {
1446 .name = "aer",
1447 .port_type = PCIE_ANY_PORT,
1448 .service = PCIE_PORT_SERVICE_AER,
1449
1450 .probe = aer_probe,
1451 .remove = aer_remove,
1452 };
1453
1454 /**
1455 * pcie_aer_init - register AER root service driver
1456 *
1457 * Invoked when AER root service driver is loaded.
1458 */
pcie_aer_init(void)1459 int __init pcie_aer_init(void)
1460 {
1461 if (!pci_aer_available())
1462 return -ENXIO;
1463 return pcie_port_service_register(&aerdriver);
1464 }
1465