1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 *
6 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
7 */
8
9 #include <linux/ascii85.h>
10 #include <linux/interconnect.h>
11 #include <linux/qcom_scm.h>
12 #include <linux/kernel.h>
13 #include <linux/of_address.h>
14 #include <linux/pm_opp.h>
15 #include <linux/slab.h>
16 #include <linux/soc/qcom/mdt_loader.h>
17 #include <linux/nvmem-consumer.h>
18 #include <soc/qcom/ocmem.h>
19 #include "adreno_gpu.h"
20 #include "a6xx_gpu.h"
21 #include "msm_gem.h"
22 #include "msm_mmu.h"
23
24 static u64 address_space_size = 0;
25 MODULE_PARM_DESC(address_space_size, "Override for size of processes private GPU address space");
26 module_param(address_space_size, ullong, 0600);
27
28 static bool zap_available = true;
29
zap_shader_load_mdt(struct msm_gpu * gpu,const char * fwname,u32 pasid)30 static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname,
31 u32 pasid)
32 {
33 struct device *dev = &gpu->pdev->dev;
34 const struct firmware *fw;
35 const char *signed_fwname = NULL;
36 struct device_node *np, *mem_np;
37 struct resource r;
38 phys_addr_t mem_phys;
39 ssize_t mem_size;
40 void *mem_region = NULL;
41 int ret;
42
43 if (!IS_ENABLED(CONFIG_ARCH_QCOM)) {
44 zap_available = false;
45 return -EINVAL;
46 }
47
48 np = of_get_child_by_name(dev->of_node, "zap-shader");
49 if (!np) {
50 zap_available = false;
51 return -ENODEV;
52 }
53
54 mem_np = of_parse_phandle(np, "memory-region", 0);
55 of_node_put(np);
56 if (!mem_np) {
57 zap_available = false;
58 return -EINVAL;
59 }
60
61 ret = of_address_to_resource(mem_np, 0, &r);
62 of_node_put(mem_np);
63 if (ret)
64 return ret;
65
66 mem_phys = r.start;
67
68 /*
69 * Check for a firmware-name property. This is the new scheme
70 * to handle firmware that may be signed with device specific
71 * keys, allowing us to have a different zap fw path for different
72 * devices.
73 *
74 * If the firmware-name property is found, we bypass the
75 * adreno_request_fw() mechanism, because we don't need to handle
76 * the /lib/firmware/qcom/... vs /lib/firmware/... case.
77 *
78 * If the firmware-name property is not found, for backwards
79 * compatibility we fall back to the fwname from the gpulist
80 * table.
81 */
82 of_property_read_string_index(np, "firmware-name", 0, &signed_fwname);
83 if (signed_fwname) {
84 fwname = signed_fwname;
85 ret = request_firmware_direct(&fw, fwname, gpu->dev->dev);
86 if (ret)
87 fw = ERR_PTR(ret);
88 } else if (fwname) {
89 /* Request the MDT file from the default location: */
90 fw = adreno_request_fw(to_adreno_gpu(gpu), fwname);
91 } else {
92 /*
93 * For new targets, we require the firmware-name property,
94 * if a zap-shader is required, rather than falling back
95 * to a firmware name specified in gpulist.
96 *
97 * Because the firmware is signed with a (potentially)
98 * device specific key, having the name come from gpulist
99 * was a bad idea, and is only provided for backwards
100 * compatibility for older targets.
101 */
102 return -ENODEV;
103 }
104
105 if (IS_ERR(fw)) {
106 DRM_DEV_ERROR(dev, "Unable to load %s\n", fwname);
107 return PTR_ERR(fw);
108 }
109
110 /* Figure out how much memory we need */
111 mem_size = qcom_mdt_get_size(fw);
112 if (mem_size < 0) {
113 ret = mem_size;
114 goto out;
115 }
116
117 if (mem_size > resource_size(&r)) {
118 DRM_DEV_ERROR(dev,
119 "memory region is too small to load the MDT\n");
120 ret = -E2BIG;
121 goto out;
122 }
123
124 /* Allocate memory for the firmware image */
125 mem_region = memremap(mem_phys, mem_size, MEMREMAP_WC);
126 if (!mem_region) {
127 ret = -ENOMEM;
128 goto out;
129 }
130
131 /*
132 * Load the rest of the MDT
133 *
134 * Note that we could be dealing with two different paths, since
135 * with upstream linux-firmware it would be in a qcom/ subdir..
136 * adreno_request_fw() handles this, but qcom_mdt_load() does
137 * not. But since we've already gotten through adreno_request_fw()
138 * we know which of the two cases it is:
139 */
140 if (signed_fwname || (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY)) {
141 ret = qcom_mdt_load(dev, fw, fwname, pasid,
142 mem_region, mem_phys, mem_size, NULL);
143 } else {
144 char *newname;
145
146 newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname);
147
148 ret = qcom_mdt_load(dev, fw, newname, pasid,
149 mem_region, mem_phys, mem_size, NULL);
150 kfree(newname);
151 }
152 if (ret)
153 goto out;
154
155 /* Send the image to the secure world */
156 ret = qcom_scm_pas_auth_and_reset(pasid);
157
158 /*
159 * If the scm call returns -EOPNOTSUPP we assume that this target
160 * doesn't need/support the zap shader so quietly fail
161 */
162 if (ret == -EOPNOTSUPP)
163 zap_available = false;
164 else if (ret)
165 DRM_DEV_ERROR(dev, "Unable to authorize the image\n");
166
167 out:
168 if (mem_region)
169 memunmap(mem_region);
170
171 release_firmware(fw);
172
173 return ret;
174 }
175
adreno_zap_shader_load(struct msm_gpu * gpu,u32 pasid)176 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid)
177 {
178 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
179 struct platform_device *pdev = gpu->pdev;
180
181 /* Short cut if we determine the zap shader isn't available/needed */
182 if (!zap_available)
183 return -ENODEV;
184
185 /* We need SCM to be able to load the firmware */
186 if (!qcom_scm_is_available()) {
187 DRM_DEV_ERROR(&pdev->dev, "SCM is not available\n");
188 return -EPROBE_DEFER;
189 }
190
191 return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid);
192 }
193
adreno_set_llc_attributes(struct iommu_domain * iommu)194 void adreno_set_llc_attributes(struct iommu_domain *iommu)
195 {
196 iommu_set_pgtable_quirks(iommu, IO_PGTABLE_QUIRK_ARM_OUTER_WBWA);
197 }
198
199 struct msm_gem_address_space *
adreno_iommu_create_address_space(struct msm_gpu * gpu,struct platform_device * pdev)200 adreno_iommu_create_address_space(struct msm_gpu *gpu,
201 struct platform_device *pdev)
202 {
203 struct iommu_domain *iommu;
204 struct msm_mmu *mmu;
205 struct msm_gem_address_space *aspace;
206 u64 start, size;
207
208 iommu = iommu_domain_alloc(&platform_bus_type);
209 if (!iommu)
210 return NULL;
211
212 mmu = msm_iommu_new(&pdev->dev, iommu);
213 if (IS_ERR(mmu)) {
214 iommu_domain_free(iommu);
215 return ERR_CAST(mmu);
216 }
217
218 /*
219 * Use the aperture start or SZ_16M, whichever is greater. This will
220 * ensure that we align with the allocated pagetable range while still
221 * allowing room in the lower 32 bits for GMEM and whatnot
222 */
223 start = max_t(u64, SZ_16M, iommu->geometry.aperture_start);
224 size = iommu->geometry.aperture_end - start + 1;
225
226 aspace = msm_gem_address_space_create(mmu, "gpu",
227 start & GENMASK_ULL(48, 0), size);
228
229 if (IS_ERR(aspace) && !IS_ERR(mmu))
230 mmu->funcs->destroy(mmu);
231
232 return aspace;
233 }
234
adreno_private_address_space_size(struct msm_gpu * gpu)235 u64 adreno_private_address_space_size(struct msm_gpu *gpu)
236 {
237 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
238
239 if (address_space_size)
240 return address_space_size;
241
242 if (adreno_gpu->info->address_space_size)
243 return adreno_gpu->info->address_space_size;
244
245 return SZ_4G;
246 }
247
adreno_get_param(struct msm_gpu * gpu,struct msm_file_private * ctx,uint32_t param,uint64_t * value,uint32_t * len)248 int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
249 uint32_t param, uint64_t *value, uint32_t *len)
250 {
251 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
252
253 /* No pointer params yet */
254 if (*len != 0)
255 return -EINVAL;
256
257 switch (param) {
258 case MSM_PARAM_GPU_ID:
259 *value = adreno_gpu->info->revn;
260 return 0;
261 case MSM_PARAM_GMEM_SIZE:
262 *value = adreno_gpu->gmem;
263 return 0;
264 case MSM_PARAM_GMEM_BASE:
265 *value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0;
266 return 0;
267 case MSM_PARAM_CHIP_ID:
268 *value = (uint64_t)adreno_gpu->rev.patchid |
269 ((uint64_t)adreno_gpu->rev.minor << 8) |
270 ((uint64_t)adreno_gpu->rev.major << 16) |
271 ((uint64_t)adreno_gpu->rev.core << 24);
272 if (!adreno_gpu->info->revn)
273 *value |= ((uint64_t) adreno_gpu->speedbin) << 32;
274 return 0;
275 case MSM_PARAM_MAX_FREQ:
276 *value = adreno_gpu->base.fast_rate;
277 return 0;
278 case MSM_PARAM_TIMESTAMP:
279 if (adreno_gpu->funcs->get_timestamp) {
280 int ret;
281
282 pm_runtime_get_sync(&gpu->pdev->dev);
283 ret = adreno_gpu->funcs->get_timestamp(gpu, value);
284 pm_runtime_put_autosuspend(&gpu->pdev->dev);
285
286 return ret;
287 }
288 return -EINVAL;
289 case MSM_PARAM_PRIORITIES:
290 *value = gpu->nr_rings * NR_SCHED_PRIORITIES;
291 return 0;
292 case MSM_PARAM_PP_PGTABLE:
293 *value = 0;
294 return 0;
295 case MSM_PARAM_FAULTS:
296 if (ctx->aspace)
297 *value = gpu->global_faults + ctx->aspace->faults;
298 else
299 *value = gpu->global_faults;
300 return 0;
301 case MSM_PARAM_SUSPENDS:
302 *value = gpu->suspend_count;
303 return 0;
304 case MSM_PARAM_VA_START:
305 if (ctx->aspace == gpu->aspace)
306 return -EINVAL;
307 *value = ctx->aspace->va_start;
308 return 0;
309 case MSM_PARAM_VA_SIZE:
310 if (ctx->aspace == gpu->aspace)
311 return -EINVAL;
312 *value = ctx->aspace->va_size;
313 return 0;
314 default:
315 DBG("%s: invalid param: %u", gpu->name, param);
316 return -EINVAL;
317 }
318 }
319
adreno_set_param(struct msm_gpu * gpu,struct msm_file_private * ctx,uint32_t param,uint64_t value,uint32_t len)320 int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
321 uint32_t param, uint64_t value, uint32_t len)
322 {
323 switch (param) {
324 case MSM_PARAM_COMM:
325 case MSM_PARAM_CMDLINE:
326 /* kstrdup_quotable_cmdline() limits to PAGE_SIZE, so
327 * that should be a reasonable upper bound
328 */
329 if (len > PAGE_SIZE)
330 return -EINVAL;
331 break;
332 default:
333 if (len != 0)
334 return -EINVAL;
335 }
336
337 switch (param) {
338 case MSM_PARAM_COMM:
339 case MSM_PARAM_CMDLINE: {
340 char *str, **paramp;
341
342 str = kmalloc(len + 1, GFP_KERNEL);
343 if (!str)
344 return -ENOMEM;
345
346 if (copy_from_user(str, u64_to_user_ptr(value), len)) {
347 kfree(str);
348 return -EFAULT;
349 }
350
351 /* Ensure string is null terminated: */
352 str[len] = '\0';
353
354 mutex_lock(&gpu->lock);
355
356 if (param == MSM_PARAM_COMM) {
357 paramp = &ctx->comm;
358 } else {
359 paramp = &ctx->cmdline;
360 }
361
362 kfree(*paramp);
363 *paramp = str;
364
365 mutex_unlock(&gpu->lock);
366
367 return 0;
368 }
369 case MSM_PARAM_SYSPROF:
370 if (!capable(CAP_SYS_ADMIN))
371 return -EPERM;
372 return msm_file_private_set_sysprof(ctx, gpu, value);
373 default:
374 DBG("%s: invalid param: %u", gpu->name, param);
375 return -EINVAL;
376 }
377 }
378
379 const struct firmware *
adreno_request_fw(struct adreno_gpu * adreno_gpu,const char * fwname)380 adreno_request_fw(struct adreno_gpu *adreno_gpu, const char *fwname)
381 {
382 struct drm_device *drm = adreno_gpu->base.dev;
383 const struct firmware *fw = NULL;
384 char *newname;
385 int ret;
386
387 newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname);
388 if (!newname)
389 return ERR_PTR(-ENOMEM);
390
391 /*
392 * Try first to load from qcom/$fwfile using a direct load (to avoid
393 * a potential timeout waiting for usermode helper)
394 */
395 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
396 (adreno_gpu->fwloc == FW_LOCATION_NEW)) {
397
398 ret = request_firmware_direct(&fw, newname, drm->dev);
399 if (!ret) {
400 DRM_DEV_INFO(drm->dev, "loaded %s from new location\n",
401 newname);
402 adreno_gpu->fwloc = FW_LOCATION_NEW;
403 goto out;
404 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
405 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
406 newname, ret);
407 fw = ERR_PTR(ret);
408 goto out;
409 }
410 }
411
412 /*
413 * Then try the legacy location without qcom/ prefix
414 */
415 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
416 (adreno_gpu->fwloc == FW_LOCATION_LEGACY)) {
417
418 ret = request_firmware_direct(&fw, fwname, drm->dev);
419 if (!ret) {
420 DRM_DEV_INFO(drm->dev, "loaded %s from legacy location\n",
421 newname);
422 adreno_gpu->fwloc = FW_LOCATION_LEGACY;
423 goto out;
424 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
425 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
426 fwname, ret);
427 fw = ERR_PTR(ret);
428 goto out;
429 }
430 }
431
432 /*
433 * Finally fall back to request_firmware() for cases where the
434 * usermode helper is needed (I think mainly android)
435 */
436 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
437 (adreno_gpu->fwloc == FW_LOCATION_HELPER)) {
438
439 ret = request_firmware(&fw, newname, drm->dev);
440 if (!ret) {
441 DRM_DEV_INFO(drm->dev, "loaded %s with helper\n",
442 newname);
443 adreno_gpu->fwloc = FW_LOCATION_HELPER;
444 goto out;
445 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
446 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
447 newname, ret);
448 fw = ERR_PTR(ret);
449 goto out;
450 }
451 }
452
453 DRM_DEV_ERROR(drm->dev, "failed to load %s\n", fwname);
454 fw = ERR_PTR(-ENOENT);
455 out:
456 kfree(newname);
457 return fw;
458 }
459
adreno_load_fw(struct adreno_gpu * adreno_gpu)460 int adreno_load_fw(struct adreno_gpu *adreno_gpu)
461 {
462 int i;
463
464 for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) {
465 const struct firmware *fw;
466
467 if (!adreno_gpu->info->fw[i])
468 continue;
469
470 /* Skip if the firmware has already been loaded */
471 if (adreno_gpu->fw[i])
472 continue;
473
474 fw = adreno_request_fw(adreno_gpu, adreno_gpu->info->fw[i]);
475 if (IS_ERR(fw))
476 return PTR_ERR(fw);
477
478 adreno_gpu->fw[i] = fw;
479 }
480
481 return 0;
482 }
483
adreno_fw_create_bo(struct msm_gpu * gpu,const struct firmware * fw,u64 * iova)484 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
485 const struct firmware *fw, u64 *iova)
486 {
487 struct drm_gem_object *bo;
488 void *ptr;
489
490 ptr = msm_gem_kernel_new(gpu->dev, fw->size - 4,
491 MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova);
492
493 if (IS_ERR(ptr))
494 return ERR_CAST(ptr);
495
496 memcpy(ptr, &fw->data[4], fw->size - 4);
497
498 msm_gem_put_vaddr(bo);
499
500 return bo;
501 }
502
adreno_hw_init(struct msm_gpu * gpu)503 int adreno_hw_init(struct msm_gpu *gpu)
504 {
505 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
506 int ret, i;
507
508 VERB("%s", gpu->name);
509
510 ret = adreno_load_fw(adreno_gpu);
511 if (ret)
512 return ret;
513
514 for (i = 0; i < gpu->nr_rings; i++) {
515 struct msm_ringbuffer *ring = gpu->rb[i];
516
517 if (!ring)
518 continue;
519
520 ring->cur = ring->start;
521 ring->next = ring->start;
522 ring->memptrs->rptr = 0;
523
524 /* Detect and clean up an impossible fence, ie. if GPU managed
525 * to scribble something invalid, we don't want that to confuse
526 * us into mistakingly believing that submits have completed.
527 */
528 if (fence_before(ring->fctx->last_fence, ring->memptrs->fence)) {
529 ring->memptrs->fence = ring->fctx->last_fence;
530 }
531 }
532
533 return 0;
534 }
535
536 /* Use this helper to read rptr, since a430 doesn't update rptr in memory */
get_rptr(struct adreno_gpu * adreno_gpu,struct msm_ringbuffer * ring)537 static uint32_t get_rptr(struct adreno_gpu *adreno_gpu,
538 struct msm_ringbuffer *ring)
539 {
540 struct msm_gpu *gpu = &adreno_gpu->base;
541
542 return gpu->funcs->get_rptr(gpu, ring);
543 }
544
adreno_active_ring(struct msm_gpu * gpu)545 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu)
546 {
547 return gpu->rb[0];
548 }
549
adreno_recover(struct msm_gpu * gpu)550 void adreno_recover(struct msm_gpu *gpu)
551 {
552 struct drm_device *dev = gpu->dev;
553 int ret;
554
555 // XXX pm-runtime?? we *need* the device to be off after this
556 // so maybe continuing to call ->pm_suspend/resume() is better?
557
558 gpu->funcs->pm_suspend(gpu);
559 gpu->funcs->pm_resume(gpu);
560
561 ret = msm_gpu_hw_init(gpu);
562 if (ret) {
563 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret);
564 /* hmm, oh well? */
565 }
566 }
567
adreno_flush(struct msm_gpu * gpu,struct msm_ringbuffer * ring,u32 reg)568 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg)
569 {
570 uint32_t wptr;
571
572 /* Copy the shadow to the actual register */
573 ring->cur = ring->next;
574
575 /*
576 * Mask wptr value that we calculate to fit in the HW range. This is
577 * to account for the possibility that the last command fit exactly into
578 * the ringbuffer and rb->next hasn't wrapped to zero yet
579 */
580 wptr = get_wptr(ring);
581
582 /* ensure writes to ringbuffer have hit system memory: */
583 mb();
584
585 gpu_write(gpu, reg, wptr);
586 }
587
adreno_idle(struct msm_gpu * gpu,struct msm_ringbuffer * ring)588 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
589 {
590 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
591 uint32_t wptr = get_wptr(ring);
592
593 /* wait for CP to drain ringbuffer: */
594 if (!spin_until(get_rptr(adreno_gpu, ring) == wptr))
595 return true;
596
597 /* TODO maybe we need to reset GPU here to recover from hang? */
598 DRM_ERROR("%s: timeout waiting to drain ringbuffer %d rptr/wptr = %X/%X\n",
599 gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr);
600
601 return false;
602 }
603
adreno_gpu_state_get(struct msm_gpu * gpu,struct msm_gpu_state * state)604 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state)
605 {
606 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
607 int i, count = 0;
608
609 WARN_ON(!mutex_is_locked(&gpu->lock));
610
611 kref_init(&state->ref);
612
613 ktime_get_real_ts64(&state->time);
614
615 for (i = 0; i < gpu->nr_rings; i++) {
616 int size = 0, j;
617
618 state->ring[i].fence = gpu->rb[i]->memptrs->fence;
619 state->ring[i].iova = gpu->rb[i]->iova;
620 state->ring[i].seqno = gpu->rb[i]->fctx->last_fence;
621 state->ring[i].rptr = get_rptr(adreno_gpu, gpu->rb[i]);
622 state->ring[i].wptr = get_wptr(gpu->rb[i]);
623
624 /* Copy at least 'wptr' dwords of the data */
625 size = state->ring[i].wptr;
626
627 /* After wptr find the last non zero dword to save space */
628 for (j = state->ring[i].wptr; j < MSM_GPU_RINGBUFFER_SZ >> 2; j++)
629 if (gpu->rb[i]->start[j])
630 size = j + 1;
631
632 if (size) {
633 state->ring[i].data = kvmalloc(size << 2, GFP_KERNEL);
634 if (state->ring[i].data) {
635 memcpy(state->ring[i].data, gpu->rb[i]->start, size << 2);
636 state->ring[i].data_size = size << 2;
637 }
638 }
639 }
640
641 /* Some targets prefer to collect their own registers */
642 if (!adreno_gpu->registers)
643 return 0;
644
645 /* Count the number of registers */
646 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2)
647 count += adreno_gpu->registers[i + 1] -
648 adreno_gpu->registers[i] + 1;
649
650 state->registers = kcalloc(count * 2, sizeof(u32), GFP_KERNEL);
651 if (state->registers) {
652 int pos = 0;
653
654 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
655 u32 start = adreno_gpu->registers[i];
656 u32 end = adreno_gpu->registers[i + 1];
657 u32 addr;
658
659 for (addr = start; addr <= end; addr++) {
660 state->registers[pos++] = addr;
661 state->registers[pos++] = gpu_read(gpu, addr);
662 }
663 }
664
665 state->nr_registers = count;
666 }
667
668 return 0;
669 }
670
adreno_gpu_state_destroy(struct msm_gpu_state * state)671 void adreno_gpu_state_destroy(struct msm_gpu_state *state)
672 {
673 int i;
674
675 for (i = 0; i < ARRAY_SIZE(state->ring); i++)
676 kvfree(state->ring[i].data);
677
678 for (i = 0; state->bos && i < state->nr_bos; i++)
679 kvfree(state->bos[i].data);
680
681 kfree(state->bos);
682 kfree(state->comm);
683 kfree(state->cmd);
684 kfree(state->registers);
685 }
686
adreno_gpu_state_kref_destroy(struct kref * kref)687 static void adreno_gpu_state_kref_destroy(struct kref *kref)
688 {
689 struct msm_gpu_state *state = container_of(kref,
690 struct msm_gpu_state, ref);
691
692 adreno_gpu_state_destroy(state);
693 kfree(state);
694 }
695
adreno_gpu_state_put(struct msm_gpu_state * state)696 int adreno_gpu_state_put(struct msm_gpu_state *state)
697 {
698 if (IS_ERR_OR_NULL(state))
699 return 1;
700
701 return kref_put(&state->ref, adreno_gpu_state_kref_destroy);
702 }
703
704 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
705
adreno_gpu_ascii85_encode(u32 * src,size_t len)706 static char *adreno_gpu_ascii85_encode(u32 *src, size_t len)
707 {
708 void *buf;
709 size_t buf_itr = 0, buffer_size;
710 char out[ASCII85_BUFSZ];
711 long l;
712 int i;
713
714 if (!src || !len)
715 return NULL;
716
717 l = ascii85_encode_len(len);
718
719 /*
720 * Ascii85 outputs either a 5 byte string or a 1 byte string. So we
721 * account for the worst case of 5 bytes per dword plus the 1 for '\0'
722 */
723 buffer_size = (l * 5) + 1;
724
725 buf = kvmalloc(buffer_size, GFP_KERNEL);
726 if (!buf)
727 return NULL;
728
729 for (i = 0; i < l; i++)
730 buf_itr += scnprintf(buf + buf_itr, buffer_size - buf_itr, "%s",
731 ascii85_encode(src[i], out));
732
733 return buf;
734 }
735
736 /* len is expected to be in bytes
737 *
738 * WARNING: *ptr should be allocated with kvmalloc or friends. It can be free'd
739 * with kvfree() and replaced with a newly kvmalloc'd buffer on the first call
740 * when the unencoded raw data is encoded
741 */
adreno_show_object(struct drm_printer * p,void ** ptr,int len,bool * encoded)742 void adreno_show_object(struct drm_printer *p, void **ptr, int len,
743 bool *encoded)
744 {
745 if (!*ptr || !len)
746 return;
747
748 if (!*encoded) {
749 long datalen, i;
750 u32 *buf = *ptr;
751
752 /*
753 * Only dump the non-zero part of the buffer - rarely will
754 * any data completely fill the entire allocated size of
755 * the buffer.
756 */
757 for (datalen = 0, i = 0; i < len >> 2; i++)
758 if (buf[i])
759 datalen = ((i + 1) << 2);
760
761 /*
762 * If we reach here, then the originally captured binary buffer
763 * will be replaced with the ascii85 encoded string
764 */
765 *ptr = adreno_gpu_ascii85_encode(buf, datalen);
766
767 kvfree(buf);
768
769 *encoded = true;
770 }
771
772 if (!*ptr)
773 return;
774
775 drm_puts(p, " data: !!ascii85 |\n");
776 drm_puts(p, " ");
777
778 drm_puts(p, *ptr);
779
780 drm_puts(p, "\n");
781 }
782
adreno_show(struct msm_gpu * gpu,struct msm_gpu_state * state,struct drm_printer * p)783 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
784 struct drm_printer *p)
785 {
786 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
787 int i;
788
789 if (IS_ERR_OR_NULL(state))
790 return;
791
792 drm_printf(p, "revision: %d (%d.%d.%d.%d)\n",
793 adreno_gpu->info->revn, adreno_gpu->rev.core,
794 adreno_gpu->rev.major, adreno_gpu->rev.minor,
795 adreno_gpu->rev.patchid);
796 /*
797 * If this is state collected due to iova fault, so fault related info
798 *
799 * TTBR0 would not be zero, so this is a good way to distinguish
800 */
801 if (state->fault_info.ttbr0) {
802 const struct msm_gpu_fault_info *info = &state->fault_info;
803
804 drm_puts(p, "fault-info:\n");
805 drm_printf(p, " - ttbr0=%.16llx\n", info->ttbr0);
806 drm_printf(p, " - iova=%.16lx\n", info->iova);
807 drm_printf(p, " - dir=%s\n", info->flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ");
808 drm_printf(p, " - type=%s\n", info->type);
809 drm_printf(p, " - source=%s\n", info->block);
810 }
811
812 drm_printf(p, "rbbm-status: 0x%08x\n", state->rbbm_status);
813
814 drm_puts(p, "ringbuffer:\n");
815
816 for (i = 0; i < gpu->nr_rings; i++) {
817 drm_printf(p, " - id: %d\n", i);
818 drm_printf(p, " iova: 0x%016llx\n", state->ring[i].iova);
819 drm_printf(p, " last-fence: %u\n", state->ring[i].seqno);
820 drm_printf(p, " retired-fence: %u\n", state->ring[i].fence);
821 drm_printf(p, " rptr: %u\n", state->ring[i].rptr);
822 drm_printf(p, " wptr: %u\n", state->ring[i].wptr);
823 drm_printf(p, " size: %u\n", MSM_GPU_RINGBUFFER_SZ);
824
825 adreno_show_object(p, &state->ring[i].data,
826 state->ring[i].data_size, &state->ring[i].encoded);
827 }
828
829 if (state->bos) {
830 drm_puts(p, "bos:\n");
831
832 for (i = 0; i < state->nr_bos; i++) {
833 drm_printf(p, " - iova: 0x%016llx\n",
834 state->bos[i].iova);
835 drm_printf(p, " size: %zd\n", state->bos[i].size);
836 drm_printf(p, " name: %-32s\n", state->bos[i].name);
837
838 adreno_show_object(p, &state->bos[i].data,
839 state->bos[i].size, &state->bos[i].encoded);
840 }
841 }
842
843 if (state->nr_registers) {
844 drm_puts(p, "registers:\n");
845
846 for (i = 0; i < state->nr_registers; i++) {
847 drm_printf(p, " - { offset: 0x%04x, value: 0x%08x }\n",
848 state->registers[i * 2] << 2,
849 state->registers[(i * 2) + 1]);
850 }
851 }
852 }
853 #endif
854
855 /* Dump common gpu status and scratch registers on any hang, to make
856 * the hangcheck logs more useful. The scratch registers seem always
857 * safe to read when GPU has hung (unlike some other regs, depending
858 * on how the GPU hung), and they are useful to match up to cmdstream
859 * dumps when debugging hangs:
860 */
adreno_dump_info(struct msm_gpu * gpu)861 void adreno_dump_info(struct msm_gpu *gpu)
862 {
863 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
864 int i;
865
866 printk("revision: %d (%d.%d.%d.%d)\n",
867 adreno_gpu->info->revn, adreno_gpu->rev.core,
868 adreno_gpu->rev.major, adreno_gpu->rev.minor,
869 adreno_gpu->rev.patchid);
870
871 for (i = 0; i < gpu->nr_rings; i++) {
872 struct msm_ringbuffer *ring = gpu->rb[i];
873
874 printk("rb %d: fence: %d/%d\n", i,
875 ring->memptrs->fence,
876 ring->fctx->last_fence);
877
878 printk("rptr: %d\n", get_rptr(adreno_gpu, ring));
879 printk("rb wptr: %d\n", get_wptr(ring));
880 }
881 }
882
883 /* would be nice to not have to duplicate the _show() stuff with printk(): */
adreno_dump(struct msm_gpu * gpu)884 void adreno_dump(struct msm_gpu *gpu)
885 {
886 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
887 int i;
888
889 if (!adreno_gpu->registers)
890 return;
891
892 /* dump these out in a form that can be parsed by demsm: */
893 printk("IO:region %s 00000000 00020000\n", gpu->name);
894 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
895 uint32_t start = adreno_gpu->registers[i];
896 uint32_t end = adreno_gpu->registers[i+1];
897 uint32_t addr;
898
899 for (addr = start; addr <= end; addr++) {
900 uint32_t val = gpu_read(gpu, addr);
901 printk("IO:R %08x %08x\n", addr<<2, val);
902 }
903 }
904 }
905
ring_freewords(struct msm_ringbuffer * ring)906 static uint32_t ring_freewords(struct msm_ringbuffer *ring)
907 {
908 struct adreno_gpu *adreno_gpu = to_adreno_gpu(ring->gpu);
909 uint32_t size = MSM_GPU_RINGBUFFER_SZ >> 2;
910 /* Use ring->next to calculate free size */
911 uint32_t wptr = ring->next - ring->start;
912 uint32_t rptr = get_rptr(adreno_gpu, ring);
913 return (rptr + (size - 1) - wptr) % size;
914 }
915
adreno_wait_ring(struct msm_ringbuffer * ring,uint32_t ndwords)916 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords)
917 {
918 if (spin_until(ring_freewords(ring) >= ndwords))
919 DRM_DEV_ERROR(ring->gpu->dev->dev,
920 "timeout waiting for space in ringbuffer %d\n",
921 ring->id);
922 }
923
924 /* Get legacy powerlevels from qcom,gpu-pwrlevels and populate the opp table */
adreno_get_legacy_pwrlevels(struct device * dev)925 static int adreno_get_legacy_pwrlevels(struct device *dev)
926 {
927 struct device_node *child, *node;
928 int ret;
929
930 node = of_get_compatible_child(dev->of_node, "qcom,gpu-pwrlevels");
931 if (!node) {
932 DRM_DEV_DEBUG(dev, "Could not find the GPU powerlevels\n");
933 return -ENXIO;
934 }
935
936 for_each_child_of_node(node, child) {
937 unsigned int val;
938
939 ret = of_property_read_u32(child, "qcom,gpu-freq", &val);
940 if (ret)
941 continue;
942
943 /*
944 * Skip the intentionally bogus clock value found at the bottom
945 * of most legacy frequency tables
946 */
947 if (val != 27000000)
948 dev_pm_opp_add(dev, val, 0);
949 }
950
951 of_node_put(node);
952
953 return 0;
954 }
955
adreno_get_pwrlevels(struct device * dev,struct msm_gpu * gpu)956 static void adreno_get_pwrlevels(struct device *dev,
957 struct msm_gpu *gpu)
958 {
959 unsigned long freq = ULONG_MAX;
960 struct dev_pm_opp *opp;
961 int ret;
962
963 gpu->fast_rate = 0;
964
965 /* You down with OPP? */
966 if (!of_find_property(dev->of_node, "operating-points-v2", NULL))
967 ret = adreno_get_legacy_pwrlevels(dev);
968 else {
969 ret = devm_pm_opp_of_add_table(dev);
970 if (ret)
971 DRM_DEV_ERROR(dev, "Unable to set the OPP table\n");
972 }
973
974 if (!ret) {
975 /* Find the fastest defined rate */
976 opp = dev_pm_opp_find_freq_floor(dev, &freq);
977 if (!IS_ERR(opp)) {
978 gpu->fast_rate = freq;
979 dev_pm_opp_put(opp);
980 }
981 }
982
983 if (!gpu->fast_rate) {
984 dev_warn(dev,
985 "Could not find a clock rate. Using a reasonable default\n");
986 /* Pick a suitably safe clock speed for any target */
987 gpu->fast_rate = 200000000;
988 }
989
990 DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate);
991 }
992
adreno_gpu_ocmem_init(struct device * dev,struct adreno_gpu * adreno_gpu,struct adreno_ocmem * adreno_ocmem)993 int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
994 struct adreno_ocmem *adreno_ocmem)
995 {
996 struct ocmem_buf *ocmem_hdl;
997 struct ocmem *ocmem;
998
999 ocmem = of_get_ocmem(dev);
1000 if (IS_ERR(ocmem)) {
1001 if (PTR_ERR(ocmem) == -ENODEV) {
1002 /*
1003 * Return success since either the ocmem property was
1004 * not specified in device tree, or ocmem support is
1005 * not compiled into the kernel.
1006 */
1007 return 0;
1008 }
1009
1010 return PTR_ERR(ocmem);
1011 }
1012
1013 ocmem_hdl = ocmem_allocate(ocmem, OCMEM_GRAPHICS, adreno_gpu->gmem);
1014 if (IS_ERR(ocmem_hdl))
1015 return PTR_ERR(ocmem_hdl);
1016
1017 adreno_ocmem->ocmem = ocmem;
1018 adreno_ocmem->base = ocmem_hdl->addr;
1019 adreno_ocmem->hdl = ocmem_hdl;
1020 adreno_gpu->gmem = ocmem_hdl->len;
1021
1022 return 0;
1023 }
1024
adreno_gpu_ocmem_cleanup(struct adreno_ocmem * adreno_ocmem)1025 void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem)
1026 {
1027 if (adreno_ocmem && adreno_ocmem->base)
1028 ocmem_free(adreno_ocmem->ocmem, OCMEM_GRAPHICS,
1029 adreno_ocmem->hdl);
1030 }
1031
adreno_read_speedbin(struct device * dev,u32 * speedbin)1032 int adreno_read_speedbin(struct device *dev, u32 *speedbin)
1033 {
1034 return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin);
1035 }
1036
adreno_gpu_init(struct drm_device * drm,struct platform_device * pdev,struct adreno_gpu * adreno_gpu,const struct adreno_gpu_funcs * funcs,int nr_rings)1037 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
1038 struct adreno_gpu *adreno_gpu,
1039 const struct adreno_gpu_funcs *funcs, int nr_rings)
1040 {
1041 struct device *dev = &pdev->dev;
1042 struct adreno_platform_config *config = dev->platform_data;
1043 struct msm_gpu_config adreno_gpu_config = { 0 };
1044 struct msm_gpu *gpu = &adreno_gpu->base;
1045 struct adreno_rev *rev = &config->rev;
1046 const char *gpu_name;
1047 u32 speedbin;
1048
1049 adreno_gpu->funcs = funcs;
1050 adreno_gpu->info = adreno_info(config->rev);
1051 adreno_gpu->gmem = adreno_gpu->info->gmem;
1052 adreno_gpu->revn = adreno_gpu->info->revn;
1053 adreno_gpu->rev = *rev;
1054
1055 if (adreno_read_speedbin(dev, &speedbin) || !speedbin)
1056 speedbin = 0xffff;
1057 adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
1058
1059 gpu_name = adreno_gpu->info->name;
1060 if (!gpu_name) {
1061 gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%d.%d.%d.%d",
1062 rev->core, rev->major, rev->minor,
1063 rev->patchid);
1064 if (!gpu_name)
1065 return -ENOMEM;
1066 }
1067
1068 adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
1069
1070 adreno_gpu_config.nr_rings = nr_rings;
1071
1072 adreno_get_pwrlevels(dev, gpu);
1073
1074 pm_runtime_set_autosuspend_delay(dev,
1075 adreno_gpu->info->inactive_period);
1076 pm_runtime_use_autosuspend(dev);
1077
1078 return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
1079 gpu_name, &adreno_gpu_config);
1080 }
1081
adreno_gpu_cleanup(struct adreno_gpu * adreno_gpu)1082 void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu)
1083 {
1084 struct msm_gpu *gpu = &adreno_gpu->base;
1085 struct msm_drm_private *priv = gpu->dev->dev_private;
1086 unsigned int i;
1087
1088 for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++)
1089 release_firmware(adreno_gpu->fw[i]);
1090
1091 if (pm_runtime_enabled(&priv->gpu_pdev->dev))
1092 pm_runtime_disable(&priv->gpu_pdev->dev);
1093
1094 msm_gpu_cleanup(&adreno_gpu->base);
1095 }
1096