1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // Copyright(c) 2020 Intel Corporation. All rights reserved.
4 //
5 // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
6 //
7 
8 /*
9  * Hardware interface for audio DSP on Tigerlake.
10  */
11 
12 #include <sound/sof/ext_manifest4.h>
13 #include "../ipc4-priv.h"
14 #include "../ops.h"
15 #include "hda.h"
16 #include "hda-ipc.h"
17 #include "../sof-audio.h"
18 
19 static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = {
20 	{"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
21 	{"pp", HDA_DSP_PP_BAR,  0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
22 	{"dsp", HDA_DSP_BAR,  0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
23 };
24 
tgl_dsp_core_get(struct snd_sof_dev * sdev,int core)25 static int tgl_dsp_core_get(struct snd_sof_dev *sdev, int core)
26 {
27 	const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
28 
29 	/* power up primary core if not already powered up and return */
30 	if (core == SOF_DSP_PRIMARY_CORE)
31 		return hda_dsp_enable_core(sdev, BIT(core));
32 
33 	if (pm_ops->set_core_state)
34 		return pm_ops->set_core_state(sdev, core, true);
35 
36 	return 0;
37 }
38 
tgl_dsp_core_put(struct snd_sof_dev * sdev,int core)39 static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core)
40 {
41 	const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
42 
43 	/* power down primary core and return */
44 	if (core == SOF_DSP_PRIMARY_CORE)
45 		return hda_dsp_core_reset_power_down(sdev, BIT(core));
46 
47 	if (pm_ops->set_core_state)
48 		return pm_ops->set_core_state(sdev, core, false);
49 
50 	return 0;
51 }
52 
53 /* Tigerlake ops */
54 struct snd_sof_dsp_ops sof_tgl_ops;
55 EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
56 
sof_tgl_ops_init(struct snd_sof_dev * sdev)57 int sof_tgl_ops_init(struct snd_sof_dev *sdev)
58 {
59 	/* common defaults */
60 	memcpy(&sof_tgl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));
61 
62 	/* probe/remove/shutdown */
63 	sof_tgl_ops.shutdown	= hda_dsp_shutdown_dma_flush;
64 
65 	if (sdev->pdata->ipc_type == SOF_IPC) {
66 		/* doorbell */
67 		sof_tgl_ops.irq_thread	= cnl_ipc_irq_thread;
68 
69 		/* ipc */
70 		sof_tgl_ops.send_msg	= cnl_ipc_send_msg;
71 
72 		/* debug */
73 		sof_tgl_ops.ipc_dump	= cnl_ipc_dump;
74 	}
75 
76 	if (sdev->pdata->ipc_type == SOF_INTEL_IPC4) {
77 		struct sof_ipc4_fw_data *ipc4_data;
78 
79 		sdev->private = devm_kzalloc(sdev->dev, sizeof(*ipc4_data), GFP_KERNEL);
80 		if (!sdev->private)
81 			return -ENOMEM;
82 
83 		ipc4_data = sdev->private;
84 		ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET;
85 
86 		ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2;
87 
88 		/* doorbell */
89 		sof_tgl_ops.irq_thread	= cnl_ipc4_irq_thread;
90 
91 		/* ipc */
92 		sof_tgl_ops.send_msg	= cnl_ipc4_send_msg;
93 
94 		/* debug */
95 		sof_tgl_ops.ipc_dump	= cnl_ipc4_dump;
96 	}
97 
98 	/* set DAI driver ops */
99 	hda_set_dai_drv_ops(sdev, &sof_tgl_ops);
100 
101 	/* debug */
102 	sof_tgl_ops.debug_map	= tgl_dsp_debugfs;
103 	sof_tgl_ops.debug_map_count	= ARRAY_SIZE(tgl_dsp_debugfs);
104 
105 	/* pre/post fw run */
106 	sof_tgl_ops.post_fw_run = hda_dsp_post_fw_run;
107 
108 	/* firmware run */
109 	sof_tgl_ops.run = hda_dsp_cl_boot_firmware_iccmax;
110 
111 	/* dsp core get/put */
112 	sof_tgl_ops.core_get = tgl_dsp_core_get;
113 	sof_tgl_ops.core_put = tgl_dsp_core_put;
114 
115 	return 0;
116 };
117 EXPORT_SYMBOL_NS(sof_tgl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
118 
119 const struct sof_intel_dsp_desc tgl_chip_info = {
120 	/* Tigerlake , Alderlake */
121 	.cores_num = 4,
122 	.init_core_mask = 1,
123 	.host_managed_cores_mask = BIT(0),
124 	.ipc_req = CNL_DSP_REG_HIPCIDR,
125 	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
126 	.ipc_ack = CNL_DSP_REG_HIPCIDA,
127 	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
128 	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
129 	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
130 	.rom_init_timeout	= 300,
131 	.ssp_count = TGL_SSP_COUNT,
132 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
133 	.sdw_shim_base = SDW_SHIM_BASE,
134 	.sdw_alh_base = SDW_ALH_BASE,
135 	.check_sdw_irq	= hda_common_check_sdw_irq,
136 	.check_ipc_irq	= hda_dsp_check_ipc_irq,
137 	.cl_init = cl_dsp_init,
138 	.power_down_dsp = hda_power_down_dsp,
139 	.disable_interrupts = hda_dsp_disable_interrupts,
140 	.hw_ip_version = SOF_INTEL_CAVS_2_5,
141 };
142 EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
143 
144 const struct sof_intel_dsp_desc tglh_chip_info = {
145 	/* Tigerlake-H */
146 	.cores_num = 2,
147 	.init_core_mask = 1,
148 	.host_managed_cores_mask = BIT(0),
149 	.ipc_req = CNL_DSP_REG_HIPCIDR,
150 	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
151 	.ipc_ack = CNL_DSP_REG_HIPCIDA,
152 	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
153 	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
154 	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
155 	.rom_init_timeout	= 300,
156 	.ssp_count = TGL_SSP_COUNT,
157 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
158 	.sdw_shim_base = SDW_SHIM_BASE,
159 	.sdw_alh_base = SDW_ALH_BASE,
160 	.check_sdw_irq	= hda_common_check_sdw_irq,
161 	.check_ipc_irq	= hda_dsp_check_ipc_irq,
162 	.cl_init = cl_dsp_init,
163 	.power_down_dsp = hda_power_down_dsp,
164 	.disable_interrupts = hda_dsp_disable_interrupts,
165 	.hw_ip_version = SOF_INTEL_CAVS_2_5,
166 };
167 EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
168 
169 const struct sof_intel_dsp_desc ehl_chip_info = {
170 	/* Elkhartlake */
171 	.cores_num = 4,
172 	.init_core_mask = 1,
173 	.host_managed_cores_mask = BIT(0),
174 	.ipc_req = CNL_DSP_REG_HIPCIDR,
175 	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
176 	.ipc_ack = CNL_DSP_REG_HIPCIDA,
177 	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
178 	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
179 	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
180 	.rom_init_timeout	= 300,
181 	.ssp_count = TGL_SSP_COUNT,
182 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
183 	.sdw_shim_base = SDW_SHIM_BASE,
184 	.sdw_alh_base = SDW_ALH_BASE,
185 	.check_sdw_irq	= hda_common_check_sdw_irq,
186 	.check_ipc_irq	= hda_dsp_check_ipc_irq,
187 	.cl_init = cl_dsp_init,
188 	.power_down_dsp = hda_power_down_dsp,
189 	.disable_interrupts = hda_dsp_disable_interrupts,
190 	.hw_ip_version = SOF_INTEL_CAVS_2_5,
191 };
192 EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
193 
194 const struct sof_intel_dsp_desc adls_chip_info = {
195 	/* Alderlake-S */
196 	.cores_num = 2,
197 	.init_core_mask = BIT(0),
198 	.host_managed_cores_mask = BIT(0),
199 	.ipc_req = CNL_DSP_REG_HIPCIDR,
200 	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
201 	.ipc_ack = CNL_DSP_REG_HIPCIDA,
202 	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
203 	.ipc_ctl = CNL_DSP_REG_HIPCCTL,
204 	.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
205 	.rom_init_timeout	= 300,
206 	.ssp_count = TGL_SSP_COUNT,
207 	.ssp_base_offset = CNL_SSP_BASE_OFFSET,
208 	.sdw_shim_base = SDW_SHIM_BASE,
209 	.sdw_alh_base = SDW_ALH_BASE,
210 	.check_sdw_irq	= hda_common_check_sdw_irq,
211 	.check_ipc_irq	= hda_dsp_check_ipc_irq,
212 	.cl_init = cl_dsp_init,
213 	.power_down_dsp = hda_power_down_dsp,
214 	.disable_interrupts = hda_dsp_disable_interrupts,
215 	.hw_ip_version = SOF_INTEL_CAVS_2_5,
216 };
217 EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
218