1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
2 /* Copyright(c) 2014 - 2021 Intel Corporation */
3 #include <adf_accel_devices.h>
4 #include <adf_clock.h>
5 #include <adf_common_drv.h>
6 #include <adf_gen2_config.h>
7 #include <adf_gen2_dc.h>
8 #include <adf_gen2_hw_data.h>
9 #include <adf_gen2_pfvf.h>
10 #include "adf_c3xxx_hw_data.h"
11 #include "adf_heartbeat.h"
12 #include "icp_qat_hw.h"
13
14 /* Worker thread to service arbiter mappings */
15 static const u32 thrd_to_arb_map[ADF_C3XXX_MAX_ACCELENGINES] = {
16 0x12222AAA, 0x11222AAA, 0x12222AAA,
17 0x11222AAA, 0x12222AAA, 0x11222AAA
18 };
19
20 static struct adf_hw_device_class c3xxx_class = {
21 .name = ADF_C3XXX_DEVICE_NAME,
22 .type = DEV_C3XXX,
23 .instances = 0
24 };
25
get_accel_mask(struct adf_hw_device_data * self)26 static u32 get_accel_mask(struct adf_hw_device_data *self)
27 {
28 u32 straps = self->straps;
29 u32 fuses = self->fuses;
30 u32 accel;
31
32 accel = ~(fuses | straps) >> ADF_C3XXX_ACCELERATORS_REG_OFFSET;
33 accel &= ADF_C3XXX_ACCELERATORS_MASK;
34
35 return accel;
36 }
37
get_ae_mask(struct adf_hw_device_data * self)38 static u32 get_ae_mask(struct adf_hw_device_data *self)
39 {
40 u32 straps = self->straps;
41 u32 fuses = self->fuses;
42 unsigned long disabled;
43 u32 ae_disable;
44 int accel;
45
46 /* If an accel is disabled, then disable the corresponding two AEs */
47 disabled = ~get_accel_mask(self) & ADF_C3XXX_ACCELERATORS_MASK;
48 ae_disable = BIT(1) | BIT(0);
49 for_each_set_bit(accel, &disabled, ADF_C3XXX_MAX_ACCELERATORS)
50 straps |= ae_disable << (accel << 1);
51
52 return ~(fuses | straps) & ADF_C3XXX_ACCELENGINES_MASK;
53 }
54
get_ts_clock(struct adf_hw_device_data * self)55 static u32 get_ts_clock(struct adf_hw_device_data *self)
56 {
57 /*
58 * Timestamp update interval is 16 AE clock ticks for c3xxx.
59 */
60 return self->clock_frequency / 16;
61 }
62
measure_clock(struct adf_accel_dev * accel_dev)63 static int measure_clock(struct adf_accel_dev *accel_dev)
64 {
65 u32 frequency;
66 int ret;
67
68 ret = adf_dev_measure_clock(accel_dev, &frequency, ADF_C3XXX_MIN_AE_FREQ,
69 ADF_C3XXX_MAX_AE_FREQ);
70 if (ret)
71 return ret;
72
73 accel_dev->hw_device->clock_frequency = frequency;
74 return 0;
75 }
76
get_misc_bar_id(struct adf_hw_device_data * self)77 static u32 get_misc_bar_id(struct adf_hw_device_data *self)
78 {
79 return ADF_C3XXX_PMISC_BAR;
80 }
81
get_etr_bar_id(struct adf_hw_device_data * self)82 static u32 get_etr_bar_id(struct adf_hw_device_data *self)
83 {
84 return ADF_C3XXX_ETR_BAR;
85 }
86
get_sram_bar_id(struct adf_hw_device_data * self)87 static u32 get_sram_bar_id(struct adf_hw_device_data *self)
88 {
89 return ADF_C3XXX_SRAM_BAR;
90 }
91
get_sku(struct adf_hw_device_data * self)92 static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
93 {
94 int aes = self->get_num_aes(self);
95
96 if (aes == 6)
97 return DEV_SKU_4;
98
99 return DEV_SKU_UNKNOWN;
100 }
101
adf_get_arbiter_mapping(struct adf_accel_dev * accel_dev)102 static const u32 *adf_get_arbiter_mapping(struct adf_accel_dev *accel_dev)
103 {
104 return thrd_to_arb_map;
105 }
106
configure_iov_threads(struct adf_accel_dev * accel_dev,bool enable)107 static void configure_iov_threads(struct adf_accel_dev *accel_dev, bool enable)
108 {
109 adf_gen2_cfg_iov_thds(accel_dev, enable,
110 ADF_C3XXX_AE2FUNC_MAP_GRP_A_NUM_REGS,
111 ADF_C3XXX_AE2FUNC_MAP_GRP_B_NUM_REGS);
112 }
113
adf_init_hw_data_c3xxx(struct adf_hw_device_data * hw_data)114 void adf_init_hw_data_c3xxx(struct adf_hw_device_data *hw_data)
115 {
116 hw_data->dev_class = &c3xxx_class;
117 hw_data->instance_id = c3xxx_class.instances++;
118 hw_data->num_banks = ADF_C3XXX_ETR_MAX_BANKS;
119 hw_data->num_rings_per_bank = ADF_ETR_MAX_RINGS_PER_BANK;
120 hw_data->num_accel = ADF_C3XXX_MAX_ACCELERATORS;
121 hw_data->num_logical_accel = 1;
122 hw_data->num_engines = ADF_C3XXX_MAX_ACCELENGINES;
123 hw_data->tx_rx_gap = ADF_GEN2_RX_RINGS_OFFSET;
124 hw_data->tx_rings_mask = ADF_GEN2_TX_RINGS_MASK;
125 hw_data->ring_to_svc_map = ADF_GEN2_DEFAULT_RING_TO_SRV_MAP;
126 hw_data->alloc_irq = adf_isr_resource_alloc;
127 hw_data->free_irq = adf_isr_resource_free;
128 hw_data->enable_error_correction = adf_gen2_enable_error_correction;
129 hw_data->get_accel_mask = get_accel_mask;
130 hw_data->get_ae_mask = get_ae_mask;
131 hw_data->get_accel_cap = adf_gen2_get_accel_cap;
132 hw_data->get_num_accels = adf_gen2_get_num_accels;
133 hw_data->get_num_aes = adf_gen2_get_num_aes;
134 hw_data->get_sram_bar_id = get_sram_bar_id;
135 hw_data->get_etr_bar_id = get_etr_bar_id;
136 hw_data->get_misc_bar_id = get_misc_bar_id;
137 hw_data->get_admin_info = adf_gen2_get_admin_info;
138 hw_data->get_arb_info = adf_gen2_get_arb_info;
139 hw_data->get_sku = get_sku;
140 hw_data->fw_name = ADF_C3XXX_FW;
141 hw_data->fw_mmp_name = ADF_C3XXX_MMP;
142 hw_data->init_admin_comms = adf_init_admin_comms;
143 hw_data->exit_admin_comms = adf_exit_admin_comms;
144 hw_data->configure_iov_threads = configure_iov_threads;
145 hw_data->send_admin_init = adf_send_admin_init;
146 hw_data->init_arb = adf_init_arb;
147 hw_data->exit_arb = adf_exit_arb;
148 hw_data->get_arb_mapping = adf_get_arbiter_mapping;
149 hw_data->enable_ints = adf_gen2_enable_ints;
150 hw_data->reset_device = adf_reset_flr;
151 hw_data->set_ssm_wdtimer = adf_gen2_set_ssm_wdtimer;
152 hw_data->disable_iov = adf_disable_sriov;
153 hw_data->dev_config = adf_gen2_dev_config;
154 hw_data->measure_clock = measure_clock;
155 hw_data->get_hb_clock = get_ts_clock;
156 hw_data->num_hb_ctrs = ADF_NUM_HB_CNT_PER_AE;
157 hw_data->check_hb_ctrs = adf_heartbeat_check_ctrs;
158
159 adf_gen2_init_pf_pfvf_ops(&hw_data->pfvf_ops);
160 adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
161 adf_gen2_init_dc_ops(&hw_data->dc_ops);
162 }
163
adf_clean_hw_data_c3xxx(struct adf_hw_device_data * hw_data)164 void adf_clean_hw_data_c3xxx(struct adf_hw_device_data *hw_data)
165 {
166 hw_data->dev_class->instances--;
167 }
168