1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __LINUX_GPIO_DRIVER_H
3 #define __LINUX_GPIO_DRIVER_H
4 
5 #include <linux/device.h>
6 #include <linux/irq.h>
7 #include <linux/irqchip/chained_irq.h>
8 #include <linux/irqdomain.h>
9 #include <linux/lockdep.h>
10 #include <linux/pinctrl/pinctrl.h>
11 #include <linux/pinctrl/pinconf-generic.h>
12 #include <linux/property.h>
13 #include <linux/types.h>
14 
15 #include <asm/msi.h>
16 
17 struct gpio_desc;
18 struct of_phandle_args;
19 struct device_node;
20 struct seq_file;
21 struct gpio_device;
22 struct module;
23 enum gpiod_flags;
24 enum gpio_lookup_flags;
25 
26 struct gpio_chip;
27 
28 union gpio_irq_fwspec {
29 	struct irq_fwspec	fwspec;
30 #ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
31 	msi_alloc_info_t	msiinfo;
32 #endif
33 };
34 
35 #define GPIO_LINE_DIRECTION_IN	1
36 #define GPIO_LINE_DIRECTION_OUT	0
37 
38 /**
39  * struct gpio_irq_chip - GPIO interrupt controller
40  */
41 struct gpio_irq_chip {
42 	/**
43 	 * @chip:
44 	 *
45 	 * GPIO IRQ chip implementation, provided by GPIO driver.
46 	 */
47 	struct irq_chip *chip;
48 
49 	/**
50 	 * @domain:
51 	 *
52 	 * Interrupt translation domain; responsible for mapping between GPIO
53 	 * hwirq number and Linux IRQ number.
54 	 */
55 	struct irq_domain *domain;
56 
57 	/**
58 	 * @domain_ops:
59 	 *
60 	 * Table of interrupt domain operations for this IRQ chip.
61 	 */
62 	const struct irq_domain_ops *domain_ops;
63 
64 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
65 	/**
66 	 * @fwnode:
67 	 *
68 	 * Firmware node corresponding to this gpiochip/irqchip, necessary
69 	 * for hierarchical irqdomain support.
70 	 */
71 	struct fwnode_handle *fwnode;
72 
73 	/**
74 	 * @parent_domain:
75 	 *
76 	 * If non-NULL, will be set as the parent of this GPIO interrupt
77 	 * controller's IRQ domain to establish a hierarchical interrupt
78 	 * domain. The presence of this will activate the hierarchical
79 	 * interrupt support.
80 	 */
81 	struct irq_domain *parent_domain;
82 
83 	/**
84 	 * @child_to_parent_hwirq:
85 	 *
86 	 * This callback translates a child hardware IRQ offset to a parent
87 	 * hardware IRQ offset on a hierarchical interrupt chip. The child
88 	 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the
89 	 * ngpio field of struct gpio_chip) and the corresponding parent
90 	 * hardware IRQ and type (such as IRQ_TYPE_*) shall be returned by
91 	 * the driver. The driver can calculate this from an offset or using
92 	 * a lookup table or whatever method is best for this chip. Return
93 	 * 0 on successful translation in the driver.
94 	 *
95 	 * If some ranges of hardware IRQs do not have a corresponding parent
96 	 * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and
97 	 * @need_valid_mask to make these GPIO lines unavailable for
98 	 * translation.
99 	 */
100 	int (*child_to_parent_hwirq)(struct gpio_chip *gc,
101 				     unsigned int child_hwirq,
102 				     unsigned int child_type,
103 				     unsigned int *parent_hwirq,
104 				     unsigned int *parent_type);
105 
106 	/**
107 	 * @populate_parent_alloc_arg :
108 	 *
109 	 * This optional callback allocates and populates the specific struct
110 	 * for the parent's IRQ domain. If this is not specified, then
111 	 * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell
112 	 * variant named &gpiochip_populate_parent_fwspec_fourcell is also
113 	 * available.
114 	 */
115 	int (*populate_parent_alloc_arg)(struct gpio_chip *gc,
116 					 union gpio_irq_fwspec *fwspec,
117 					 unsigned int parent_hwirq,
118 					 unsigned int parent_type);
119 
120 	/**
121 	 * @child_offset_to_irq:
122 	 *
123 	 * This optional callback is used to translate the child's GPIO line
124 	 * offset on the GPIO chip to an IRQ number for the GPIO to_irq()
125 	 * callback. If this is not specified, then a default callback will be
126 	 * provided that returns the line offset.
127 	 */
128 	unsigned int (*child_offset_to_irq)(struct gpio_chip *gc,
129 					    unsigned int pin);
130 
131 	/**
132 	 * @child_irq_domain_ops:
133 	 *
134 	 * The IRQ domain operations that will be used for this GPIO IRQ
135 	 * chip. If no operations are provided, then default callbacks will
136 	 * be populated to setup the IRQ hierarchy. Some drivers need to
137 	 * supply their own translate function.
138 	 */
139 	struct irq_domain_ops child_irq_domain_ops;
140 #endif
141 
142 	/**
143 	 * @handler:
144 	 *
145 	 * The IRQ handler to use (often a predefined IRQ core function) for
146 	 * GPIO IRQs, provided by GPIO driver.
147 	 */
148 	irq_flow_handler_t handler;
149 
150 	/**
151 	 * @default_type:
152 	 *
153 	 * Default IRQ triggering type applied during GPIO driver
154 	 * initialization, provided by GPIO driver.
155 	 */
156 	unsigned int default_type;
157 
158 	/**
159 	 * @lock_key:
160 	 *
161 	 * Per GPIO IRQ chip lockdep class for IRQ lock.
162 	 */
163 	struct lock_class_key *lock_key;
164 
165 	/**
166 	 * @request_key:
167 	 *
168 	 * Per GPIO IRQ chip lockdep class for IRQ request.
169 	 */
170 	struct lock_class_key *request_key;
171 
172 	/**
173 	 * @parent_handler:
174 	 *
175 	 * The interrupt handler for the GPIO chip's parent interrupts, may be
176 	 * NULL if the parent interrupts are nested rather than cascaded.
177 	 */
178 	irq_flow_handler_t parent_handler;
179 
180 	union {
181 		/**
182 		 * @parent_handler_data:
183 		 *
184 		 * If @per_parent_data is false, @parent_handler_data is a
185 		 * single pointer used as the data associated with every
186 		 * parent interrupt.
187 		 */
188 		void *parent_handler_data;
189 
190 		/**
191 		 * @parent_handler_data_array:
192 		 *
193 		 * If @per_parent_data is true, @parent_handler_data_array is
194 		 * an array of @num_parents pointers, and is used to associate
195 		 * different data for each parent. This cannot be NULL if
196 		 * @per_parent_data is true.
197 		 */
198 		void **parent_handler_data_array;
199 	};
200 
201 	/**
202 	 * @num_parents:
203 	 *
204 	 * The number of interrupt parents of a GPIO chip.
205 	 */
206 	unsigned int num_parents;
207 
208 	/**
209 	 * @parents:
210 	 *
211 	 * A list of interrupt parents of a GPIO chip. This is owned by the
212 	 * driver, so the core will only reference this list, not modify it.
213 	 */
214 	unsigned int *parents;
215 
216 	/**
217 	 * @map:
218 	 *
219 	 * A list of interrupt parents for each line of a GPIO chip.
220 	 */
221 	unsigned int *map;
222 
223 	/**
224 	 * @threaded:
225 	 *
226 	 * True if set the interrupt handling uses nested threads.
227 	 */
228 	bool threaded;
229 
230 	/**
231 	 * @per_parent_data:
232 	 *
233 	 * True if parent_handler_data_array describes a @num_parents
234 	 * sized array to be used as parent data.
235 	 */
236 	bool per_parent_data;
237 
238 	/**
239 	 * @initialized:
240 	 *
241 	 * Flag to track GPIO chip irq member's initialization.
242 	 * This flag will make sure GPIO chip irq members are not used
243 	 * before they are initialized.
244 	 */
245 	bool initialized;
246 
247 	/**
248 	 * @init_hw: optional routine to initialize hardware before
249 	 * an IRQ chip will be added. This is quite useful when
250 	 * a particular driver wants to clear IRQ related registers
251 	 * in order to avoid undesired events.
252 	 */
253 	int (*init_hw)(struct gpio_chip *gc);
254 
255 	/**
256 	 * @init_valid_mask: optional routine to initialize @valid_mask, to be
257 	 * used if not all GPIO lines are valid interrupts. Sometimes some
258 	 * lines just cannot fire interrupts, and this routine, when defined,
259 	 * is passed a bitmap in "valid_mask" and it will have ngpios
260 	 * bits from 0..(ngpios-1) set to "1" as in valid. The callback can
261 	 * then directly set some bits to "0" if they cannot be used for
262 	 * interrupts.
263 	 */
264 	void (*init_valid_mask)(struct gpio_chip *gc,
265 				unsigned long *valid_mask,
266 				unsigned int ngpios);
267 
268 	/**
269 	 * @valid_mask:
270 	 *
271 	 * If not %NULL, holds bitmask of GPIOs which are valid to be included
272 	 * in IRQ domain of the chip.
273 	 */
274 	unsigned long *valid_mask;
275 
276 	/**
277 	 * @first:
278 	 *
279 	 * Required for static IRQ allocation. If set, irq_domain_add_simple()
280 	 * will allocate and map all IRQs during initialization.
281 	 */
282 	unsigned int first;
283 
284 	/**
285 	 * @irq_enable:
286 	 *
287 	 * Store old irq_chip irq_enable callback
288 	 */
289 	void		(*irq_enable)(struct irq_data *data);
290 
291 	/**
292 	 * @irq_disable:
293 	 *
294 	 * Store old irq_chip irq_disable callback
295 	 */
296 	void		(*irq_disable)(struct irq_data *data);
297 	/**
298 	 * @irq_unmask:
299 	 *
300 	 * Store old irq_chip irq_unmask callback
301 	 */
302 	void		(*irq_unmask)(struct irq_data *data);
303 
304 	/**
305 	 * @irq_mask:
306 	 *
307 	 * Store old irq_chip irq_mask callback
308 	 */
309 	void		(*irq_mask)(struct irq_data *data);
310 };
311 
312 /**
313  * struct gpio_chip - abstract a GPIO controller
314  * @label: a functional name for the GPIO device, such as a part
315  *	number or the name of the SoC IP-block implementing it.
316  * @gpiodev: the internal state holder, opaque struct
317  * @parent: optional parent device providing the GPIOs
318  * @fwnode: optional fwnode providing this controller's properties
319  * @owner: helps prevent removal of modules exporting active GPIOs
320  * @request: optional hook for chip-specific activation, such as
321  *	enabling module power and clock; may sleep
322  * @free: optional hook for chip-specific deactivation, such as
323  *	disabling module power and clock; may sleep
324  * @get_direction: returns direction for signal "offset", 0=out, 1=in,
325  *	(same as GPIO_LINE_DIRECTION_OUT / GPIO_LINE_DIRECTION_IN),
326  *	or negative error. It is recommended to always implement this
327  *	function, even on input-only or output-only gpio chips.
328  * @direction_input: configures signal "offset" as input, or returns error
329  *	This can be omitted on input-only or output-only gpio chips.
330  * @direction_output: configures signal "offset" as output, or returns error
331  *	This can be omitted on input-only or output-only gpio chips.
332  * @get: returns value for signal "offset", 0=low, 1=high, or negative error
333  * @get_multiple: reads values for multiple signals defined by "mask" and
334  *	stores them in "bits", returns 0 on success or negative error
335  * @set: assigns output value for signal "offset"
336  * @set_multiple: assigns output values for multiple signals defined by "mask"
337  * @set_config: optional hook for all kinds of settings. Uses the same
338  *	packed config format as generic pinconf.
339  * @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
340  *	implementation may not sleep
341  * @dbg_show: optional routine to show contents in debugfs; default code
342  *	will be used when this is omitted, but custom code can show extra
343  *	state (such as pullup/pulldown configuration).
344  * @init_valid_mask: optional routine to initialize @valid_mask, to be used if
345  *	not all GPIOs are valid.
346  * @add_pin_ranges: optional routine to initialize pin ranges, to be used when
347  *	requires special mapping of the pins that provides GPIO functionality.
348  *	It is called after adding GPIO chip and before adding IRQ chip.
349  * @en_hw_timestamp: Dependent on GPIO chip, an optional routine to
350  *	enable hardware timestamp.
351  * @dis_hw_timestamp: Dependent on GPIO chip, an optional routine to
352  *	disable hardware timestamp.
353  * @base: identifies the first GPIO number handled by this chip;
354  *	or, if negative during registration, requests dynamic ID allocation.
355  *	DEPRECATION: providing anything non-negative and nailing the base
356  *	offset of GPIO chips is deprecated. Please pass -1 as base to
357  *	let gpiolib select the chip base in all possible cases. We want to
358  *	get rid of the static GPIO number space in the long run.
359  * @ngpio: the number of GPIOs handled by this controller; the last GPIO
360  *	handled is (base + ngpio - 1).
361  * @offset: when multiple gpio chips belong to the same device this
362  *	can be used as offset within the device so friendly names can
363  *	be properly assigned.
364  * @names: if set, must be an array of strings to use as alternative
365  *      names for the GPIOs in this chip. Any entry in the array
366  *      may be NULL if there is no alias for the GPIO, however the
367  *      array must be @ngpio entries long.  A name can include a single printk
368  *      format specifier for an unsigned int.  It is substituted by the actual
369  *      number of the gpio.
370  * @can_sleep: flag must be set iff get()/set() methods sleep, as they
371  *	must while accessing GPIO expander chips over I2C or SPI. This
372  *	implies that if the chip supports IRQs, these IRQs need to be threaded
373  *	as the chip access may sleep when e.g. reading out the IRQ status
374  *	registers.
375  * @read_reg: reader function for generic GPIO
376  * @write_reg: writer function for generic GPIO
377  * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing
378  *	line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the
379  *	generic GPIO core. It is for internal housekeeping only.
380  * @reg_dat: data (in) register for generic GPIO
381  * @reg_set: output set register (out=high) for generic GPIO
382  * @reg_clr: output clear register (out=low) for generic GPIO
383  * @reg_dir_out: direction out setting register for generic GPIO
384  * @reg_dir_in: direction in setting register for generic GPIO
385  * @bgpio_dir_unreadable: indicates that the direction register(s) cannot
386  *	be read and we need to rely on out internal state tracking.
387  * @bgpio_bits: number of register bits used for a generic GPIO i.e.
388  *	<register width> * 8
389  * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
390  *	shadowed and real data registers writes together.
391  * @bgpio_data:	shadowed data register for generic GPIO to clear/set bits
392  *	safely.
393  * @bgpio_dir: shadowed direction register for generic GPIO to clear/set
394  *	direction safely. A "1" in this word means the line is set as
395  *	output.
396  *
397  * A gpio_chip can help platforms abstract various sources of GPIOs so
398  * they can all be accessed through a common programming interface.
399  * Example sources would be SOC controllers, FPGAs, multifunction
400  * chips, dedicated GPIO expanders, and so on.
401  *
402  * Each chip controls a number of signals, identified in method calls
403  * by "offset" values in the range 0..(@ngpio - 1).  When those signals
404  * are referenced through calls like gpio_get_value(gpio), the offset
405  * is calculated by subtracting @base from the gpio number.
406  */
407 struct gpio_chip {
408 	const char		*label;
409 	struct gpio_device	*gpiodev;
410 	struct device		*parent;
411 	struct fwnode_handle	*fwnode;
412 	struct module		*owner;
413 
414 	int			(*request)(struct gpio_chip *gc,
415 						unsigned int offset);
416 	void			(*free)(struct gpio_chip *gc,
417 						unsigned int offset);
418 	int			(*get_direction)(struct gpio_chip *gc,
419 						unsigned int offset);
420 	int			(*direction_input)(struct gpio_chip *gc,
421 						unsigned int offset);
422 	int			(*direction_output)(struct gpio_chip *gc,
423 						unsigned int offset, int value);
424 	int			(*get)(struct gpio_chip *gc,
425 						unsigned int offset);
426 	int			(*get_multiple)(struct gpio_chip *gc,
427 						unsigned long *mask,
428 						unsigned long *bits);
429 	void			(*set)(struct gpio_chip *gc,
430 						unsigned int offset, int value);
431 	void			(*set_multiple)(struct gpio_chip *gc,
432 						unsigned long *mask,
433 						unsigned long *bits);
434 	int			(*set_config)(struct gpio_chip *gc,
435 					      unsigned int offset,
436 					      unsigned long config);
437 	int			(*to_irq)(struct gpio_chip *gc,
438 						unsigned int offset);
439 
440 	void			(*dbg_show)(struct seq_file *s,
441 						struct gpio_chip *gc);
442 
443 	int			(*init_valid_mask)(struct gpio_chip *gc,
444 						   unsigned long *valid_mask,
445 						   unsigned int ngpios);
446 
447 	int			(*add_pin_ranges)(struct gpio_chip *gc);
448 
449 	int			(*en_hw_timestamp)(struct gpio_chip *gc,
450 						   u32 offset,
451 						   unsigned long flags);
452 	int			(*dis_hw_timestamp)(struct gpio_chip *gc,
453 						    u32 offset,
454 						    unsigned long flags);
455 	int			base;
456 	u16			ngpio;
457 	u16			offset;
458 	const char		*const *names;
459 	bool			can_sleep;
460 
461 #if IS_ENABLED(CONFIG_GPIO_GENERIC)
462 	unsigned long (*read_reg)(void __iomem *reg);
463 	void (*write_reg)(void __iomem *reg, unsigned long data);
464 	bool be_bits;
465 	void __iomem *reg_dat;
466 	void __iomem *reg_set;
467 	void __iomem *reg_clr;
468 	void __iomem *reg_dir_out;
469 	void __iomem *reg_dir_in;
470 	bool bgpio_dir_unreadable;
471 	int bgpio_bits;
472 	raw_spinlock_t bgpio_lock;
473 	unsigned long bgpio_data;
474 	unsigned long bgpio_dir;
475 #endif /* CONFIG_GPIO_GENERIC */
476 
477 #ifdef CONFIG_GPIOLIB_IRQCHIP
478 	/*
479 	 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
480 	 * to handle IRQs for most practical cases.
481 	 */
482 
483 	/**
484 	 * @irq:
485 	 *
486 	 * Integrates interrupt chip functionality with the GPIO chip. Can be
487 	 * used to handle IRQs for most practical cases.
488 	 */
489 	struct gpio_irq_chip irq;
490 #endif /* CONFIG_GPIOLIB_IRQCHIP */
491 
492 	/**
493 	 * @valid_mask:
494 	 *
495 	 * If not %NULL, holds bitmask of GPIOs which are valid to be used
496 	 * from the chip.
497 	 */
498 	unsigned long *valid_mask;
499 
500 #if defined(CONFIG_OF_GPIO)
501 	/*
502 	 * If CONFIG_OF_GPIO is enabled, then all GPIO controllers described in
503 	 * the device tree automatically may have an OF translation
504 	 */
505 
506 	/**
507 	 * @of_node:
508 	 *
509 	 * Pointer to a device tree node representing this GPIO controller.
510 	 */
511 	struct device_node *of_node;
512 
513 	/**
514 	 * @of_gpio_n_cells:
515 	 *
516 	 * Number of cells used to form the GPIO specifier.
517 	 */
518 	unsigned int of_gpio_n_cells;
519 
520 	/**
521 	 * @of_xlate:
522 	 *
523 	 * Callback to translate a device tree GPIO specifier into a chip-
524 	 * relative GPIO number and flags.
525 	 */
526 	int (*of_xlate)(struct gpio_chip *gc,
527 			const struct of_phandle_args *gpiospec, u32 *flags);
528 
529 	/**
530 	 * @of_gpio_ranges_fallback:
531 	 *
532 	 * Optional hook for the case that no gpio-ranges property is defined
533 	 * within the device tree node "np" (usually DT before introduction
534 	 * of gpio-ranges). So this callback is helpful to provide the
535 	 * necessary backward compatibility for the pin ranges.
536 	 */
537 	int (*of_gpio_ranges_fallback)(struct gpio_chip *gc,
538 				       struct device_node *np);
539 
540 #endif /* CONFIG_OF_GPIO */
541 };
542 
543 extern const char *gpiochip_is_requested(struct gpio_chip *gc,
544 			unsigned int offset);
545 
546 /**
547  * for_each_requested_gpio_in_range - iterates over requested GPIOs in a given range
548  * @chip:	the chip to query
549  * @i:		loop variable
550  * @base:	first GPIO in the range
551  * @size:	amount of GPIOs to check starting from @base
552  * @label:	label of current GPIO
553  */
554 #define for_each_requested_gpio_in_range(chip, i, base, size, label)			\
555 	for (i = 0; i < size; i++)							\
556 		if ((label = gpiochip_is_requested(chip, base + i)) == NULL) {} else
557 
558 /* Iterates over all requested GPIO of the given @chip */
559 #define for_each_requested_gpio(chip, i, label)						\
560 	for_each_requested_gpio_in_range(chip, i, 0, chip->ngpio, label)
561 
562 /* add/remove chips */
563 extern int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data,
564 				      struct lock_class_key *lock_key,
565 				      struct lock_class_key *request_key);
566 
567 /**
568  * gpiochip_add_data() - register a gpio_chip
569  * @gc: the chip to register, with gc->base initialized
570  * @data: driver-private data associated with this chip
571  *
572  * Context: potentially before irqs will work
573  *
574  * When gpiochip_add_data() is called very early during boot, so that GPIOs
575  * can be freely used, the gc->parent device must be registered before
576  * the gpio framework's arch_initcall().  Otherwise sysfs initialization
577  * for GPIOs will fail rudely.
578  *
579  * gpiochip_add_data() must only be called after gpiolib initialization,
580  * i.e. after core_initcall().
581  *
582  * If gc->base is negative, this requests dynamic assignment of
583  * a range of valid GPIOs.
584  *
585  * Returns:
586  * A negative errno if the chip can't be registered, such as because the
587  * gc->base is invalid or already associated with a different chip.
588  * Otherwise it returns zero as a success code.
589  */
590 #ifdef CONFIG_LOCKDEP
591 #define gpiochip_add_data(gc, data) ({		\
592 		static struct lock_class_key lock_key;	\
593 		static struct lock_class_key request_key;	  \
594 		gpiochip_add_data_with_key(gc, data, &lock_key, \
595 					   &request_key);	  \
596 	})
597 #define devm_gpiochip_add_data(dev, gc, data) ({ \
598 		static struct lock_class_key lock_key;	\
599 		static struct lock_class_key request_key;	  \
600 		devm_gpiochip_add_data_with_key(dev, gc, data, &lock_key, \
601 					   &request_key);	  \
602 	})
603 #else
604 #define gpiochip_add_data(gc, data) gpiochip_add_data_with_key(gc, data, NULL, NULL)
605 #define devm_gpiochip_add_data(dev, gc, data) \
606 	devm_gpiochip_add_data_with_key(dev, gc, data, NULL, NULL)
607 #endif /* CONFIG_LOCKDEP */
608 
gpiochip_add(struct gpio_chip * gc)609 static inline int gpiochip_add(struct gpio_chip *gc)
610 {
611 	return gpiochip_add_data(gc, NULL);
612 }
613 extern void gpiochip_remove(struct gpio_chip *gc);
614 extern int devm_gpiochip_add_data_with_key(struct device *dev, struct gpio_chip *gc, void *data,
615 					   struct lock_class_key *lock_key,
616 					   struct lock_class_key *request_key);
617 
618 extern struct gpio_chip *gpiochip_find(void *data,
619 			      int (*match)(struct gpio_chip *gc, void *data));
620 
621 bool gpiochip_line_is_irq(struct gpio_chip *gc, unsigned int offset);
622 int gpiochip_reqres_irq(struct gpio_chip *gc, unsigned int offset);
623 void gpiochip_relres_irq(struct gpio_chip *gc, unsigned int offset);
624 void gpiochip_disable_irq(struct gpio_chip *gc, unsigned int offset);
625 void gpiochip_enable_irq(struct gpio_chip *gc, unsigned int offset);
626 
627 /* irq_data versions of the above */
628 int gpiochip_irq_reqres(struct irq_data *data);
629 void gpiochip_irq_relres(struct irq_data *data);
630 
631 /* Paste this in your irq_chip structure  */
632 #define	GPIOCHIP_IRQ_RESOURCE_HELPERS					\
633 		.irq_request_resources  = gpiochip_irq_reqres,		\
634 		.irq_release_resources  = gpiochip_irq_relres
635 
gpio_irq_chip_set_chip(struct gpio_irq_chip * girq,const struct irq_chip * chip)636 static inline void gpio_irq_chip_set_chip(struct gpio_irq_chip *girq,
637 					  const struct irq_chip *chip)
638 {
639 	/* Yes, dropping const is ugly, but it isn't like we have a choice */
640 	girq->chip = (struct irq_chip *)chip;
641 }
642 
643 /* Line status inquiry for drivers */
644 bool gpiochip_line_is_open_drain(struct gpio_chip *gc, unsigned int offset);
645 bool gpiochip_line_is_open_source(struct gpio_chip *gc, unsigned int offset);
646 
647 /* Sleep persistence inquiry for drivers */
648 bool gpiochip_line_is_persistent(struct gpio_chip *gc, unsigned int offset);
649 bool gpiochip_line_is_valid(const struct gpio_chip *gc, unsigned int offset);
650 
651 /* get driver data */
652 void *gpiochip_get_data(struct gpio_chip *gc);
653 
654 struct bgpio_pdata {
655 	const char *label;
656 	int base;
657 	int ngpio;
658 };
659 
660 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
661 
662 int gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc,
663 					    union gpio_irq_fwspec *gfwspec,
664 					    unsigned int parent_hwirq,
665 					    unsigned int parent_type);
666 int gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc,
667 					     union gpio_irq_fwspec *gfwspec,
668 					     unsigned int parent_hwirq,
669 					     unsigned int parent_type);
670 
671 #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */
672 
673 int bgpio_init(struct gpio_chip *gc, struct device *dev,
674 	       unsigned long sz, void __iomem *dat, void __iomem *set,
675 	       void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
676 	       unsigned long flags);
677 
678 #define BGPIOF_BIG_ENDIAN		BIT(0)
679 #define BGPIOF_UNREADABLE_REG_SET	BIT(1) /* reg_set is unreadable */
680 #define BGPIOF_UNREADABLE_REG_DIR	BIT(2) /* reg_dir is unreadable */
681 #define BGPIOF_BIG_ENDIAN_BYTE_ORDER	BIT(3)
682 #define BGPIOF_READ_OUTPUT_REG_SET	BIT(4) /* reg_set stores output value */
683 #define BGPIOF_NO_OUTPUT		BIT(5) /* only input */
684 #define BGPIOF_NO_SET_ON_INPUT		BIT(6)
685 
686 int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
687 		     irq_hw_number_t hwirq);
688 void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq);
689 
690 int gpiochip_irq_domain_activate(struct irq_domain *domain,
691 				 struct irq_data *data, bool reserve);
692 void gpiochip_irq_domain_deactivate(struct irq_domain *domain,
693 				    struct irq_data *data);
694 
695 bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gc,
696 				unsigned int offset);
697 
698 #ifdef CONFIG_GPIOLIB_IRQCHIP
699 int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
700 				struct irq_domain *domain);
701 #else
gpiochip_irqchip_add_domain(struct gpio_chip * gc,struct irq_domain * domain)702 static inline int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
703 					      struct irq_domain *domain)
704 {
705 	WARN_ON(1);
706 	return -EINVAL;
707 }
708 #endif
709 
710 int gpiochip_generic_request(struct gpio_chip *gc, unsigned int offset);
711 void gpiochip_generic_free(struct gpio_chip *gc, unsigned int offset);
712 int gpiochip_generic_config(struct gpio_chip *gc, unsigned int offset,
713 			    unsigned long config);
714 
715 /**
716  * struct gpio_pin_range - pin range controlled by a gpio chip
717  * @node: list for maintaining set of pin ranges, used internally
718  * @pctldev: pinctrl device which handles corresponding pins
719  * @range: actual range of pins controlled by a gpio controller
720  */
721 struct gpio_pin_range {
722 	struct list_head node;
723 	struct pinctrl_dev *pctldev;
724 	struct pinctrl_gpio_range range;
725 };
726 
727 #ifdef CONFIG_PINCTRL
728 
729 int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
730 			   unsigned int gpio_offset, unsigned int pin_offset,
731 			   unsigned int npins);
732 int gpiochip_add_pingroup_range(struct gpio_chip *gc,
733 			struct pinctrl_dev *pctldev,
734 			unsigned int gpio_offset, const char *pin_group);
735 void gpiochip_remove_pin_ranges(struct gpio_chip *gc);
736 
737 #else /* ! CONFIG_PINCTRL */
738 
739 static inline int
gpiochip_add_pin_range(struct gpio_chip * gc,const char * pinctl_name,unsigned int gpio_offset,unsigned int pin_offset,unsigned int npins)740 gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
741 		       unsigned int gpio_offset, unsigned int pin_offset,
742 		       unsigned int npins)
743 {
744 	return 0;
745 }
746 static inline int
gpiochip_add_pingroup_range(struct gpio_chip * gc,struct pinctrl_dev * pctldev,unsigned int gpio_offset,const char * pin_group)747 gpiochip_add_pingroup_range(struct gpio_chip *gc,
748 			struct pinctrl_dev *pctldev,
749 			unsigned int gpio_offset, const char *pin_group)
750 {
751 	return 0;
752 }
753 
754 static inline void
gpiochip_remove_pin_ranges(struct gpio_chip * gc)755 gpiochip_remove_pin_ranges(struct gpio_chip *gc)
756 {
757 }
758 
759 #endif /* CONFIG_PINCTRL */
760 
761 struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *gc,
762 					    unsigned int hwnum,
763 					    const char *label,
764 					    enum gpio_lookup_flags lflags,
765 					    enum gpiod_flags dflags);
766 void gpiochip_free_own_desc(struct gpio_desc *desc);
767 
768 #ifdef CONFIG_GPIOLIB
769 
770 /* lock/unlock as IRQ */
771 int gpiochip_lock_as_irq(struct gpio_chip *gc, unsigned int offset);
772 void gpiochip_unlock_as_irq(struct gpio_chip *gc, unsigned int offset);
773 
774 
775 struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
776 
777 #else /* CONFIG_GPIOLIB */
778 
gpiod_to_chip(const struct gpio_desc * desc)779 static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
780 {
781 	/* GPIO can never have been requested */
782 	WARN_ON(1);
783 	return ERR_PTR(-ENODEV);
784 }
785 
gpiochip_lock_as_irq(struct gpio_chip * gc,unsigned int offset)786 static inline int gpiochip_lock_as_irq(struct gpio_chip *gc,
787 				       unsigned int offset)
788 {
789 	WARN_ON(1);
790 	return -EINVAL;
791 }
792 
gpiochip_unlock_as_irq(struct gpio_chip * gc,unsigned int offset)793 static inline void gpiochip_unlock_as_irq(struct gpio_chip *gc,
794 					  unsigned int offset)
795 {
796 	WARN_ON(1);
797 }
798 #endif /* CONFIG_GPIOLIB */
799 
800 #define for_each_gpiochip_node(dev, child)					\
801 	device_for_each_child_node(dev, child)					\
802 		if (!fwnode_property_present(child, "gpio-controller")) {} else
803 
gpiochip_node_count(struct device * dev)804 static inline unsigned int gpiochip_node_count(struct device *dev)
805 {
806 	struct fwnode_handle *child;
807 	unsigned int count = 0;
808 
809 	for_each_gpiochip_node(dev, child)
810 		count++;
811 
812 	return count;
813 }
814 
gpiochip_node_get_first(struct device * dev)815 static inline struct fwnode_handle *gpiochip_node_get_first(struct device *dev)
816 {
817 	struct fwnode_handle *fwnode;
818 
819 	for_each_gpiochip_node(dev, fwnode)
820 		return fwnode;
821 
822 	return NULL;
823 }
824 
825 #endif /* __LINUX_GPIO_DRIVER_H */
826