1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Admin Function driver
3  *
4  * Copyright (C) 2018 Marvell.
5  *
6  */
7 
8 #ifndef MBOX_H
9 #define MBOX_H
10 
11 #include <linux/etherdevice.h>
12 #include <linux/sizes.h>
13 
14 #include "rvu_struct.h"
15 #include "common.h"
16 
17 #define MBOX_SIZE		SZ_64K
18 
19 /* AF/PF: PF initiated, PF/VF VF initiated */
20 #define MBOX_DOWN_RX_START	0
21 #define MBOX_DOWN_RX_SIZE	(46 * SZ_1K)
22 #define MBOX_DOWN_TX_START	(MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)
23 #define MBOX_DOWN_TX_SIZE	(16 * SZ_1K)
24 /* AF/PF: AF initiated, PF/VF PF initiated */
25 #define MBOX_UP_RX_START	(MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)
26 #define MBOX_UP_RX_SIZE		SZ_1K
27 #define MBOX_UP_TX_START	(MBOX_UP_RX_START + MBOX_UP_RX_SIZE)
28 #define MBOX_UP_TX_SIZE		SZ_1K
29 
30 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE
31 # error "incorrect mailbox area sizes"
32 #endif
33 
34 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
35 
36 #define MBOX_RSP_TIMEOUT	6000 /* Time(ms) to wait for mbox response */
37 
38 #define MBOX_MSG_ALIGN		16  /* Align mbox msg start to 16bytes */
39 
40 /* Mailbox directions */
41 #define MBOX_DIR_AFPF		0  /* AF replies to PF */
42 #define MBOX_DIR_PFAF		1  /* PF sends messages to AF */
43 #define MBOX_DIR_PFVF		2  /* PF replies to VF */
44 #define MBOX_DIR_VFPF		3  /* VF sends messages to PF */
45 #define MBOX_DIR_AFPF_UP	4  /* AF sends messages to PF */
46 #define MBOX_DIR_PFAF_UP	5  /* PF replies to AF */
47 #define MBOX_DIR_PFVF_UP	6  /* PF sends messages to VF */
48 #define MBOX_DIR_VFPF_UP	7  /* VF replies to PF */
49 
50 struct otx2_mbox_dev {
51 	void	    *mbase;   /* This dev's mbox region */
52 	void	    *hwbase;
53 	spinlock_t  mbox_lock;
54 	u16         msg_size; /* Total msg size to be sent */
55 	u16         rsp_size; /* Total rsp size to be sure the reply is ok */
56 	u16         num_msgs; /* No of msgs sent or waiting for response */
57 	u16         msgs_acked; /* No of msgs for which response is received */
58 };
59 
60 struct otx2_mbox {
61 	struct pci_dev *pdev;
62 	void   *hwbase;  /* Mbox region advertised by HW */
63 	void   *reg_base;/* CSR base for this dev */
64 	u64    trigger;  /* Trigger mbox notification */
65 	u16    tr_shift; /* Mbox trigger shift */
66 	u64    rx_start; /* Offset of Rx region in mbox memory */
67 	u64    tx_start; /* Offset of Tx region in mbox memory */
68 	u16    rx_size;  /* Size of Rx region */
69 	u16    tx_size;  /* Size of Tx region */
70 	u16    ndevs;    /* The number of peers */
71 	struct otx2_mbox_dev *dev;
72 };
73 
74 /* Header which precedes all mbox messages */
75 struct mbox_hdr {
76 	u64 msg_size;	/* Total msgs size embedded */
77 	u16  num_msgs;   /* No of msgs embedded */
78 };
79 
80 /* Header which precedes every msg and is also part of it */
81 struct mbox_msghdr {
82 	u16 pcifunc;     /* Who's sending this msg */
83 	u16 id;          /* Mbox message ID */
84 #define OTX2_MBOX_REQ_SIG (0xdead)
85 #define OTX2_MBOX_RSP_SIG (0xbeef)
86 	u16 sig;         /* Signature, for validating corrupted msgs */
87 #define OTX2_MBOX_VERSION (0x000a)
88 	u16 ver;         /* Version of msg's structure for this ID */
89 	u16 next_msgoff; /* Offset of next msg within mailbox region */
90 	int rc;          /* Msg process'ed response code */
91 };
92 
93 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
94 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
95 void otx2_mbox_destroy(struct otx2_mbox *mbox);
96 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase,
97 		   struct pci_dev *pdev, void __force *reg_base,
98 		   int direction, int ndevs);
99 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase,
100 			   struct pci_dev *pdev, void __force *reg_base,
101 			   int direction, int ndevs);
102 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
103 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
104 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid);
105 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
106 					    int size, int size_rsp);
107 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid,
108 				      struct mbox_msghdr *msg);
109 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid);
110 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid,
111 			   u16 pcifunc, u16 id);
112 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid);
113 const char *otx2_mbox_id2name(u16 id);
otx2_mbox_alloc_msg(struct otx2_mbox * mbox,int devid,int size)114 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox,
115 						      int devid, int size)
116 {
117 	return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);
118 }
119 
120 /* Mailbox message types */
121 #define MBOX_MSG_MASK				0xFFFF
122 #define MBOX_MSG_INVALID			0xFFFE
123 #define MBOX_MSG_MAX				0xFFFF
124 
125 #define MBOX_MESSAGES							\
126 /* Generic mbox IDs (range 0x000 - 0x1FF) */				\
127 M(READY,		0x001, ready, msg_req, ready_msg_rsp)		\
128 M(ATTACH_RESOURCES,	0x002, attach_resources, rsrc_attach, msg_rsp)	\
129 M(DETACH_RESOURCES,	0x003, detach_resources, rsrc_detach, msg_rsp)	\
130 M(FREE_RSRC_CNT,	0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp)	\
131 M(MSIX_OFFSET,		0x005, msix_offset, msg_req, msix_offset_rsp)	\
132 M(VF_FLR,		0x006, vf_flr, msg_req, msg_rsp)		\
133 M(PTP_OP,		0x007, ptp_op, ptp_req, ptp_rsp)		\
134 M(GET_HW_CAP,		0x008, get_hw_cap, msg_req, get_hw_cap_rsp)	\
135 M(LMTST_TBL_SETUP,	0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req,    \
136 				msg_rsp)				\
137 M(SET_VF_PERM,		0x00b, set_vf_perm, set_vf_perm, msg_rsp)	\
138 /* CGX mbox IDs (range 0x200 - 0x3FF) */				\
139 M(CGX_START_RXTX,	0x200, cgx_start_rxtx, msg_req, msg_rsp)	\
140 M(CGX_STOP_RXTX,	0x201, cgx_stop_rxtx, msg_req, msg_rsp)		\
141 M(CGX_STATS,		0x202, cgx_stats, msg_req, cgx_stats_rsp)	\
142 M(CGX_MAC_ADDR_SET,	0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get,    \
143 				cgx_mac_addr_set_or_get)		\
144 M(CGX_MAC_ADDR_GET,	0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get,    \
145 				cgx_mac_addr_set_or_get)		\
146 M(CGX_PROMISC_ENABLE,	0x205, cgx_promisc_enable, msg_req, msg_rsp)	\
147 M(CGX_PROMISC_DISABLE,	0x206, cgx_promisc_disable, msg_req, msg_rsp)	\
148 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp)	\
149 M(CGX_STOP_LINKEVENTS,	0x208, cgx_stop_linkevents, msg_req, msg_rsp)	\
150 M(CGX_GET_LINKINFO,	0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \
151 M(CGX_INTLBK_ENABLE,	0x20A, cgx_intlbk_enable, msg_req, msg_rsp)	\
152 M(CGX_INTLBK_DISABLE,	0x20B, cgx_intlbk_disable, msg_req, msg_rsp)	\
153 M(CGX_PTP_RX_ENABLE,	0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp)	\
154 M(CGX_PTP_RX_DISABLE,	0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp)	\
155 M(CGX_CFG_PAUSE_FRM,	0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg,	\
156 			       cgx_pause_frm_cfg)			\
157 M(CGX_FW_DATA_GET,	0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \
158 M(CGX_FEC_SET,		0x210, cgx_set_fec_param, fec_mode, fec_mode) \
159 M(CGX_MAC_ADDR_ADD,	0x211, cgx_mac_addr_add, cgx_mac_addr_add_req,    \
160 				cgx_mac_addr_add_rsp)		\
161 M(CGX_MAC_ADDR_DEL,	0x212, cgx_mac_addr_del, cgx_mac_addr_del_req,    \
162 			       msg_rsp)		\
163 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req,    \
164 				  cgx_max_dmac_entries_get_rsp)		\
165 M(CGX_FEC_STATS,	0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \
166 M(CGX_SET_LINK_MODE,	0x218, cgx_set_link_mode, cgx_set_link_mode_req,\
167 			       cgx_set_link_mode_rsp)	\
168 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \
169 M(CGX_FEATURES_GET,	0x21B, cgx_features_get, msg_req,		\
170 			       cgx_features_info_msg)			\
171 M(RPM_STATS,		0x21C, rpm_stats, msg_req, rpm_stats_rsp)	\
172 M(CGX_MAC_ADDR_RESET,	0x21D, cgx_mac_addr_reset, cgx_mac_addr_reset_req, \
173 							msg_rsp) \
174 M(CGX_MAC_ADDR_UPDATE,	0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \
175 						    cgx_mac_addr_update_rsp) \
176 M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg,  \
177 				 cgx_pfc_rsp)                               \
178 /* NPA mbox IDs (range 0x400 - 0x5FF) */				\
179 M(NPA_LF_ALLOC,		0x400, npa_lf_alloc,				\
180 				npa_lf_alloc_req, npa_lf_alloc_rsp)	\
181 M(NPA_LF_FREE,		0x401, npa_lf_free, msg_req, msg_rsp)		\
182 M(NPA_AQ_ENQ,		0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp)   \
183 M(NPA_HWCTX_DISABLE,	0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\
184 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */				\
185 /* TIM mbox IDs (range 0x800 - 0x9FF) */				\
186 /* CPT mbox IDs (range 0xA00 - 0xBFF) */				\
187 M(CPT_LF_ALLOC,		0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg,	\
188 			       msg_rsp)					\
189 M(CPT_LF_FREE,		0xA01, cpt_lf_free, msg_req, msg_rsp)		\
190 M(CPT_RD_WR_REGISTER,	0xA02, cpt_rd_wr_register,  cpt_rd_wr_reg_msg,	\
191 			       cpt_rd_wr_reg_msg)			\
192 M(CPT_INLINE_IPSEC_CFG,	0xA04, cpt_inline_ipsec_cfg,			\
193 			       cpt_inline_ipsec_cfg_msg, msg_rsp)	\
194 M(CPT_STATS,            0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp)	\
195 M(CPT_RXC_TIME_CFG,     0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req,  \
196 			       msg_rsp)                                 \
197 M(CPT_CTX_CACHE_SYNC,   0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp)    \
198 /* SDP mbox IDs (range 0x1000 - 0x11FF) */				\
199 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \
200 M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \
201 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */				\
202 M(NPC_MCAM_ALLOC_ENTRY,	0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\
203 				npc_mcam_alloc_entry_rsp)		\
204 M(NPC_MCAM_FREE_ENTRY,	0x6001, npc_mcam_free_entry,			\
205 				 npc_mcam_free_entry_req, msg_rsp)	\
206 M(NPC_MCAM_WRITE_ENTRY,	0x6002, npc_mcam_write_entry,			\
207 				 npc_mcam_write_entry_req, msg_rsp)	\
208 M(NPC_MCAM_ENA_ENTRY,   0x6003, npc_mcam_ena_entry,			\
209 				 npc_mcam_ena_dis_entry_req, msg_rsp)	\
210 M(NPC_MCAM_DIS_ENTRY,   0x6004, npc_mcam_dis_entry,			\
211 				 npc_mcam_ena_dis_entry_req, msg_rsp)	\
212 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\
213 				npc_mcam_shift_entry_rsp)		\
214 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter,		\
215 					npc_mcam_alloc_counter_req,	\
216 					npc_mcam_alloc_counter_rsp)	\
217 M(NPC_MCAM_FREE_COUNTER,  0x6007, npc_mcam_free_counter,		\
218 				    npc_mcam_oper_counter_req, msg_rsp)	\
219 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter,		\
220 				   npc_mcam_unmap_counter_req, msg_rsp)	\
221 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter,		\
222 				   npc_mcam_oper_counter_req, msg_rsp)	\
223 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats,		\
224 				   npc_mcam_oper_counter_req,		\
225 				   npc_mcam_oper_counter_rsp)		\
226 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry,      \
227 					  npc_mcam_alloc_and_write_entry_req,  \
228 					  npc_mcam_alloc_and_write_entry_rsp)  \
229 M(NPC_GET_KEX_CFG,	  0x600c, npc_get_kex_cfg,			\
230 				   msg_req, npc_get_kex_cfg_rsp)	\
231 M(NPC_INSTALL_FLOW,	  0x600d, npc_install_flow,			       \
232 				  npc_install_flow_req, npc_install_flow_rsp)  \
233 M(NPC_DELETE_FLOW,	  0x600e, npc_delete_flow,			\
234 				  npc_delete_flow_req, msg_rsp)		\
235 M(NPC_MCAM_READ_ENTRY,	  0x600f, npc_mcam_read_entry,			\
236 				  npc_mcam_read_entry_req,		\
237 				  npc_mcam_read_entry_rsp)		\
238 M(NPC_SET_PKIND,        0x6010,   npc_set_pkind,                        \
239 				  npc_set_pkind, msg_rsp)               \
240 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule,            \
241 				   msg_req, npc_mcam_read_base_rule_rsp)  \
242 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats,                     \
243 				   npc_mcam_get_stats_req,              \
244 				   npc_mcam_get_stats_rsp)              \
245 M(NPC_GET_SECRET_KEY, 0x6013, npc_get_secret_key,                     \
246 				   npc_get_secret_key_req,              \
247 				   npc_get_secret_key_rsp)              \
248 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */				\
249 M(NIX_LF_ALLOC,		0x8000, nix_lf_alloc,				\
250 				 nix_lf_alloc_req, nix_lf_alloc_rsp)	\
251 M(NIX_LF_FREE,		0x8001, nix_lf_free, nix_lf_free_req, msg_rsp)	\
252 M(NIX_AQ_ENQ,		0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp)  \
253 M(NIX_HWCTX_DISABLE,	0x8003, nix_hwctx_disable,			\
254 				 hwctx_disable_req, msg_rsp)		\
255 M(NIX_TXSCH_ALLOC,	0x8004, nix_txsch_alloc,			\
256 				 nix_txsch_alloc_req, nix_txsch_alloc_rsp)   \
257 M(NIX_TXSCH_FREE,	0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \
258 M(NIX_TXSCHQ_CFG,	0x8006, nix_txschq_cfg, nix_txschq_config,	\
259 				nix_txschq_config)			\
260 M(NIX_STATS_RST,	0x8007, nix_stats_rst, msg_req, msg_rsp)	\
261 M(NIX_VTAG_CFG,		0x8008, nix_vtag_cfg, nix_vtag_config,		\
262 				 nix_vtag_config_rsp)			\
263 M(NIX_RSS_FLOWKEY_CFG,  0x8009, nix_rss_flowkey_cfg,			\
264 				 nix_rss_flowkey_cfg,			\
265 				 nix_rss_flowkey_cfg_rsp)		\
266 M(NIX_SET_MAC_ADDR,	0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \
267 M(NIX_SET_RX_MODE,	0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp)	\
268 M(NIX_SET_HW_FRS,	0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp)	\
269 M(NIX_LF_START_RX,	0x800d, nix_lf_start_rx, msg_req, msg_rsp)	\
270 M(NIX_LF_STOP_RX,	0x800e, nix_lf_stop_rx, msg_req, msg_rsp)	\
271 M(NIX_MARK_FORMAT_CFG,	0x800f, nix_mark_format_cfg,			\
272 				 nix_mark_format_cfg,			\
273 				 nix_mark_format_cfg_rsp)		\
274 M(NIX_SET_RX_CFG,	0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp)	\
275 M(NIX_LSO_FORMAT_CFG,	0x8011, nix_lso_format_cfg,			\
276 				 nix_lso_format_cfg,			\
277 				 nix_lso_format_cfg_rsp)		\
278 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp)	\
279 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \
280 M(NIX_BP_ENABLE,	0x8016, nix_bp_enable, nix_bp_cfg_req,	\
281 				nix_bp_cfg_rsp)	\
282 M(NIX_BP_DISABLE,	0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \
283 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \
284 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg,			\
285 				nix_inline_ipsec_cfg, msg_rsp)		\
286 M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg,		\
287 				nix_inline_ipsec_lf_cfg, msg_rsp)	\
288 M(NIX_CN10K_AQ_ENQ,	0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \
289 				nix_cn10k_aq_enq_rsp)			\
290 M(NIX_GET_HW_INFO,	0x801c, nix_get_hw_info, msg_req, nix_hw_info)	\
291 M(NIX_BANDPROF_ALLOC,	0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \
292 				nix_bandprof_alloc_rsp)			    \
293 M(NIX_BANDPROF_FREE,	0x801e, nix_bandprof_free, nix_bandprof_free_req,   \
294 				msg_rsp)				    \
295 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req,		\
296 				nix_bandprof_get_hwinfo_rsp)		    \
297 /* MCS mbox IDs (range 0xA000 - 0xBFFF) */					\
298 M(MCS_ALLOC_RESOURCES,	0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req,	\
299 				mcs_alloc_rsrc_rsp)				\
300 M(MCS_FREE_RESOURCES,	0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \
301 M(MCS_FLOWID_ENTRY_WRITE, 0xa002, mcs_flowid_entry_write, mcs_flowid_entry_write_req,	\
302 				msg_rsp)					\
303 M(MCS_SECY_PLCY_WRITE,	0xa003, mcs_secy_plcy_write, mcs_secy_plcy_write_req,	\
304 				msg_rsp)					\
305 M(MCS_RX_SC_CAM_WRITE,	0xa004, mcs_rx_sc_cam_write, mcs_rx_sc_cam_write_req,	\
306 				msg_rsp)					\
307 M(MCS_SA_PLCY_WRITE,	0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req,	\
308 				msg_rsp)					\
309 M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map,	\
310 				  msg_rsp)					\
311 M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map,	\
312 				  msg_rsp)					\
313 M(MCS_FLOWID_ENA_ENTRY,	0xa008, mcs_flowid_ena_entry, mcs_flowid_ena_dis_entry,	\
314 				msg_rsp)					\
315 M(MCS_PN_TABLE_WRITE,	0xa009, mcs_pn_table_write, mcs_pn_table_write_req,	\
316 				msg_rsp)					\
317 M(MCS_SET_ACTIVE_LMAC,	0xa00a,	mcs_set_active_lmac, mcs_set_active_lmac,	\
318 				msg_rsp)					\
319 M(MCS_GET_HW_INFO,	0xa00b,	mcs_get_hw_info, msg_req, mcs_hw_info)		\
320 M(MCS_GET_FLOWID_STATS, 0xa00c, mcs_get_flowid_stats, mcs_stats_req,		\
321 				mcs_flowid_stats)				\
322 M(MCS_GET_SECY_STATS,	0xa00d, mcs_get_secy_stats, mcs_stats_req,		\
323 				mcs_secy_stats)					\
324 M(MCS_GET_SC_STATS,	0xa00e, mcs_get_sc_stats, mcs_stats_req, mcs_sc_stats)	\
325 M(MCS_GET_SA_STATS,	0xa00f, mcs_get_sa_stats, mcs_stats_req, mcs_sa_stats)	\
326 M(MCS_GET_PORT_STATS,	0xa010, mcs_get_port_stats, mcs_stats_req,		\
327 				mcs_port_stats)					\
328 M(MCS_CLEAR_STATS,	0xa011,	mcs_clear_stats, mcs_clear_stats, msg_rsp)	\
329 M(MCS_INTR_CFG,		0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp)		\
330 M(MCS_SET_LMAC_MODE,	0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp)	\
331 M(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold,	\
332 				msg_rsp)					\
333 M(MCS_ALLOC_CTRL_PKT_RULE, 0xa015, mcs_alloc_ctrl_pkt_rule,			\
334 				   mcs_alloc_ctrl_pkt_rule_req,			\
335 				   mcs_alloc_ctrl_pkt_rule_rsp)			\
336 M(MCS_FREE_CTRL_PKT_RULE, 0xa016, mcs_free_ctrl_pkt_rule,			\
337 				  mcs_free_ctrl_pkt_rule_req, msg_rsp)		\
338 M(MCS_CTRL_PKT_RULE_WRITE, 0xa017, mcs_ctrl_pkt_rule_write,			\
339 				   mcs_ctrl_pkt_rule_write_req, msg_rsp)	\
340 M(MCS_PORT_RESET,	0xa018, mcs_port_reset, mcs_port_reset_req, msg_rsp)	\
341 M(MCS_PORT_CFG_SET,	0xa019, mcs_port_cfg_set, mcs_port_cfg_set_req, msg_rsp)\
342 M(MCS_PORT_CFG_GET,	0xa020, mcs_port_cfg_get, mcs_port_cfg_get_req,		\
343 				mcs_port_cfg_get_rsp)				\
344 M(MCS_CUSTOM_TAG_CFG_GET, 0xa021, mcs_custom_tag_cfg_get,			\
345 				  mcs_custom_tag_cfg_get_req,			\
346 				  mcs_custom_tag_cfg_get_rsp)
347 
348 /* Messages initiated by AF (range 0xC00 - 0xEFF) */
349 #define MBOX_UP_CGX_MESSAGES						\
350 M(CGX_LINK_EVENT,	0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp)
351 
352 #define MBOX_UP_CPT_MESSAGES						\
353 M(CPT_INST_LMTST,	0xD00, cpt_inst_lmtst, cpt_inst_lmtst_req, msg_rsp)
354 
355 #define MBOX_UP_MCS_MESSAGES						\
356 M(MCS_INTR_NOTIFY,	0xE00, mcs_intr_notify, mcs_intr_info, msg_rsp)
357 
358 enum {
359 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,
360 MBOX_MESSAGES
361 MBOX_UP_CGX_MESSAGES
362 MBOX_UP_CPT_MESSAGES
363 MBOX_UP_MCS_MESSAGES
364 #undef M
365 };
366 
367 /* Mailbox message formats */
368 
369 #define RVU_DEFAULT_PF_FUNC     0xFFFF
370 
371 /* Generic request msg used for those mbox messages which
372  * don't send any data in the request.
373  */
374 struct msg_req {
375 	struct mbox_msghdr hdr;
376 };
377 
378 /* Generic response msg used an ack or response for those mbox
379  * messages which don't have a specific rsp msg format.
380  */
381 struct msg_rsp {
382 	struct mbox_msghdr hdr;
383 };
384 
385 /* RVU mailbox error codes
386  * Range 256 - 300.
387  */
388 enum rvu_af_status {
389 	RVU_INVALID_VF_ID           = -256,
390 };
391 
392 struct ready_msg_rsp {
393 	struct mbox_msghdr hdr;
394 	u16    sclk_freq;	/* SCLK frequency (in MHz) */
395 	u16    rclk_freq;	/* RCLK frequency (in MHz) */
396 };
397 
398 /* Structure for requesting resource provisioning.
399  * 'modify' flag to be used when either requesting more
400  * or to detach partial of a certain resource type.
401  * Rest of the fields specify how many of what type to
402  * be attached.
403  * To request LFs from two blocks of same type this mailbox
404  * can be sent twice as below:
405  *      struct rsrc_attach *attach;
406  *       .. Allocate memory for message ..
407  *       attach->cptlfs = 3; <3 LFs from CPT0>
408  *       .. Send message ..
409  *       .. Allocate memory for message ..
410  *       attach->modify = 1;
411  *       attach->cpt_blkaddr = BLKADDR_CPT1;
412  *       attach->cptlfs = 2; <2 LFs from CPT1>
413  *       .. Send message ..
414  */
415 struct rsrc_attach {
416 	struct mbox_msghdr hdr;
417 	u8   modify:1;
418 	u8   npalf:1;
419 	u8   nixlf:1;
420 	u16  sso;
421 	u16  ssow;
422 	u16  timlfs;
423 	u16  cptlfs;
424 	int  cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */
425 };
426 
427 /* Structure for relinquishing resources.
428  * 'partial' flag to be used when relinquishing all resources
429  * but only of a certain type. If not set, all resources of all
430  * types provisioned to the RVU function will be detached.
431  */
432 struct rsrc_detach {
433 	struct mbox_msghdr hdr;
434 	u8 partial:1;
435 	u8 npalf:1;
436 	u8 nixlf:1;
437 	u8 sso:1;
438 	u8 ssow:1;
439 	u8 timlfs:1;
440 	u8 cptlfs:1;
441 };
442 
443 /* Number of resources available to the caller.
444  * In reply to MBOX_MSG_FREE_RSRC_CNT.
445  */
446 struct free_rsrcs_rsp {
447 	struct mbox_msghdr hdr;
448 	u16 schq[NIX_TXSCH_LVL_CNT];
449 	u16  sso;
450 	u16  tim;
451 	u16  ssow;
452 	u16  cpt;
453 	u8   npa;
454 	u8   nix;
455 	u16  schq_nix1[NIX_TXSCH_LVL_CNT];
456 	u8   nix1;
457 	u8   cpt1;
458 	u8   ree0;
459 	u8   ree1;
460 };
461 
462 #define MSIX_VECTOR_INVALID	0xFFFF
463 #define MAX_RVU_BLKLF_CNT	256
464 
465 struct msix_offset_rsp {
466 	struct mbox_msghdr hdr;
467 	u16  npa_msixoff;
468 	u16  nix_msixoff;
469 	u16  sso;
470 	u16  ssow;
471 	u16  timlfs;
472 	u16  cptlfs;
473 	u16  sso_msixoff[MAX_RVU_BLKLF_CNT];
474 	u16  ssow_msixoff[MAX_RVU_BLKLF_CNT];
475 	u16  timlf_msixoff[MAX_RVU_BLKLF_CNT];
476 	u16  cptlf_msixoff[MAX_RVU_BLKLF_CNT];
477 	u16  cpt1_lfs;
478 	u16  ree0_lfs;
479 	u16  ree1_lfs;
480 	u16  cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];
481 	u16  ree0_lf_msixoff[MAX_RVU_BLKLF_CNT];
482 	u16  ree1_lf_msixoff[MAX_RVU_BLKLF_CNT];
483 };
484 
485 struct get_hw_cap_rsp {
486 	struct mbox_msghdr hdr;
487 	u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
488 	u8 nix_shaping;		     /* Is shaping and coloring supported */
489 	u8 npc_hash_extract;	/* Is hash extract supported */
490 };
491 
492 /* CGX mbox message formats */
493 
494 struct cgx_stats_rsp {
495 	struct mbox_msghdr hdr;
496 #define CGX_RX_STATS_COUNT	9
497 #define CGX_TX_STATS_COUNT	18
498 	u64 rx_stats[CGX_RX_STATS_COUNT];
499 	u64 tx_stats[CGX_TX_STATS_COUNT];
500 };
501 
502 struct cgx_fec_stats_rsp {
503 	struct mbox_msghdr hdr;
504 	u64 fec_corr_blks;
505 	u64 fec_uncorr_blks;
506 };
507 /* Structure for requesting the operation for
508  * setting/getting mac address in the CGX interface
509  */
510 struct cgx_mac_addr_set_or_get {
511 	struct mbox_msghdr hdr;
512 	u8 mac_addr[ETH_ALEN];
513 	u32 index;
514 };
515 
516 /* Structure for requesting the operation to
517  * add DMAC filter entry into CGX interface
518  */
519 struct cgx_mac_addr_add_req {
520 	struct mbox_msghdr hdr;
521 	u8 mac_addr[ETH_ALEN];
522 };
523 
524 /* Structure for response against the operation to
525  * add DMAC filter entry into CGX interface
526  */
527 struct cgx_mac_addr_add_rsp {
528 	struct mbox_msghdr hdr;
529 	u32 index;
530 };
531 
532 /* Structure for requesting the operation to
533  * delete DMAC filter entry from CGX interface
534  */
535 struct cgx_mac_addr_del_req {
536 	struct mbox_msghdr hdr;
537 	u32 index;
538 };
539 
540 /* Structure for response against the operation to
541  * get maximum supported DMAC filter entries
542  */
543 struct cgx_max_dmac_entries_get_rsp {
544 	struct mbox_msghdr hdr;
545 	u32 max_dmac_filters;
546 };
547 
548 struct cgx_link_user_info {
549 	uint64_t link_up:1;
550 	uint64_t full_duplex:1;
551 	uint64_t lmac_type_id:4;
552 	uint64_t speed:20; /* speed in Mbps */
553 	uint64_t an:1;		/* AN supported or not */
554 	uint64_t fec:2;	 /* FEC type if enabled else 0 */
555 #define LMACTYPE_STR_LEN 16
556 	char lmac_type[LMACTYPE_STR_LEN];
557 };
558 
559 struct cgx_link_info_msg {
560 	struct mbox_msghdr hdr;
561 	struct cgx_link_user_info link_info;
562 };
563 
564 struct cgx_pause_frm_cfg {
565 	struct mbox_msghdr hdr;
566 	u8 set;
567 	/* set = 1 if the request is to config pause frames */
568 	/* set = 0 if the request is to fetch pause frames config */
569 	u8 rx_pause;
570 	u8 tx_pause;
571 };
572 
573 enum fec_type {
574 	OTX2_FEC_NONE,
575 	OTX2_FEC_BASER,
576 	OTX2_FEC_RS,
577 	OTX2_FEC_STATS_CNT = 2,
578 	OTX2_FEC_OFF,
579 };
580 
581 struct fec_mode {
582 	struct mbox_msghdr hdr;
583 	int fec;
584 };
585 
586 struct sfp_eeprom_s {
587 #define SFP_EEPROM_SIZE 256
588 	u16 sff_id;
589 	u8 buf[SFP_EEPROM_SIZE];
590 	u64 reserved;
591 };
592 
593 struct phy_s {
594 	struct {
595 		u64 can_change_mod_type:1;
596 		u64 mod_type:1;
597 		u64 has_fec_stats:1;
598 	} misc;
599 	struct fec_stats_s {
600 		u32 rsfec_corr_cws;
601 		u32 rsfec_uncorr_cws;
602 		u32 brfec_corr_blks;
603 		u32 brfec_uncorr_blks;
604 	} fec_stats;
605 };
606 
607 struct cgx_lmac_fwdata_s {
608 	u16 rw_valid;
609 	u64 supported_fec;
610 	u64 supported_an;
611 	u64 supported_link_modes;
612 	/* only applicable if AN is supported */
613 	u64 advertised_fec;
614 	u64 advertised_link_modes;
615 	/* Only applicable if SFP/QSFP slot is present */
616 	struct sfp_eeprom_s sfp_eeprom;
617 	struct phy_s phy;
618 #define LMAC_FWDATA_RESERVED_MEM 1021
619 	u64 reserved[LMAC_FWDATA_RESERVED_MEM];
620 };
621 
622 struct cgx_fw_data {
623 	struct mbox_msghdr hdr;
624 	struct cgx_lmac_fwdata_s fwdata;
625 };
626 
627 struct cgx_set_link_mode_args {
628 	u32 speed;
629 	u8 duplex;
630 	u8 an;
631 	u8 ports;
632 	u64 mode;
633 };
634 
635 struct cgx_set_link_mode_req {
636 #define AUTONEG_UNKNOWN		0xff
637 	struct mbox_msghdr hdr;
638 	struct cgx_set_link_mode_args args;
639 };
640 
641 struct cgx_set_link_mode_rsp {
642 	struct mbox_msghdr hdr;
643 	int status;
644 };
645 
646 struct cgx_mac_addr_reset_req {
647 	struct mbox_msghdr hdr;
648 	u32 index;
649 };
650 
651 struct cgx_mac_addr_update_req {
652 	struct mbox_msghdr hdr;
653 	u8 mac_addr[ETH_ALEN];
654 	u32 index;
655 };
656 
657 struct cgx_mac_addr_update_rsp {
658 	struct mbox_msghdr hdr;
659 	u32 index;
660 };
661 
662 #define RVU_LMAC_FEAT_FC		BIT_ULL(0) /* pause frames */
663 #define	RVU_LMAC_FEAT_HIGIG2		BIT_ULL(1)
664 			/* flow control from physical link higig2 messages */
665 #define RVU_LMAC_FEAT_PTP		BIT_ULL(2) /* precison time protocol */
666 #define RVU_LMAC_FEAT_DMACF		BIT_ULL(3) /* DMAC FILTER */
667 #define RVU_MAC_VERSION			BIT_ULL(4)
668 #define RVU_MAC_CGX			BIT_ULL(5)
669 #define RVU_MAC_RPM			BIT_ULL(6)
670 
671 struct cgx_features_info_msg {
672 	struct mbox_msghdr hdr;
673 	u64    lmac_features;
674 };
675 
676 struct rpm_stats_rsp {
677 	struct mbox_msghdr hdr;
678 #define RPM_RX_STATS_COUNT		43
679 #define RPM_TX_STATS_COUNT		34
680 	u64 rx_stats[RPM_RX_STATS_COUNT];
681 	u64 tx_stats[RPM_TX_STATS_COUNT];
682 };
683 
684 struct cgx_pfc_cfg {
685 	struct mbox_msghdr hdr;
686 	u8 rx_pause;
687 	u8 tx_pause;
688 	u16 pfc_en; /*  bitmap indicating pfc enabled traffic classes */
689 };
690 
691 struct cgx_pfc_rsp {
692 	struct mbox_msghdr hdr;
693 	u8 rx_pause;
694 	u8 tx_pause;
695 };
696 
697  /* NPA mbox message formats */
698 
699 struct npc_set_pkind {
700 	struct mbox_msghdr hdr;
701 #define OTX2_PRIV_FLAGS_DEFAULT  BIT_ULL(0)
702 #define OTX2_PRIV_FLAGS_CUSTOM   BIT_ULL(63)
703 	u64 mode;
704 #define PKIND_TX		BIT_ULL(0)
705 #define PKIND_RX		BIT_ULL(1)
706 	u8 dir;
707 	u8 pkind; /* valid only in case custom flag */
708 	u8 var_len_off; /* Offset of custom header length field.
709 			 * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND
710 			 */
711 	u8 var_len_off_mask; /* Mask for length with in offset */
712 	u8 shift_dir; /* shift direction to get length of the header at var_len_off */
713 };
714 
715 /* NPA mbox message formats */
716 
717 /* NPA mailbox error codes
718  * Range 301 - 400.
719  */
720 enum npa_af_status {
721 	NPA_AF_ERR_PARAM            = -301,
722 	NPA_AF_ERR_AQ_FULL          = -302,
723 	NPA_AF_ERR_AQ_ENQUEUE       = -303,
724 	NPA_AF_ERR_AF_LF_INVALID    = -304,
725 	NPA_AF_ERR_AF_LF_ALLOC      = -305,
726 	NPA_AF_ERR_LF_RESET         = -306,
727 };
728 
729 /* For NPA LF context alloc and init */
730 struct npa_lf_alloc_req {
731 	struct mbox_msghdr hdr;
732 	int node;
733 	int aura_sz;  /* No of auras */
734 	u32 nr_pools; /* No of pools */
735 	u64 way_mask;
736 };
737 
738 struct npa_lf_alloc_rsp {
739 	struct mbox_msghdr hdr;
740 	u32 stack_pg_ptrs;  /* No of ptrs per stack page */
741 	u32 stack_pg_bytes; /* Size of stack page */
742 	u16 qints; /* NPA_AF_CONST::QINTS */
743 	u8 cache_lines; /*BATCH ALLOC DMA */
744 };
745 
746 /* NPA AQ enqueue msg */
747 struct npa_aq_enq_req {
748 	struct mbox_msghdr hdr;
749 	u32 aura_id;
750 	u8 ctype;
751 	u8 op;
752 	union {
753 		/* Valid when op == WRITE/INIT and ctype == AURA.
754 		 * LF fills the pool_id in aura.pool_addr. AF will translate
755 		 * the pool_id to pool context pointer.
756 		 */
757 		struct npa_aura_s aura;
758 		/* Valid when op == WRITE/INIT and ctype == POOL */
759 		struct npa_pool_s pool;
760 	};
761 	/* Mask data when op == WRITE (1=write, 0=don't write) */
762 	union {
763 		/* Valid when op == WRITE and ctype == AURA */
764 		struct npa_aura_s aura_mask;
765 		/* Valid when op == WRITE and ctype == POOL */
766 		struct npa_pool_s pool_mask;
767 	};
768 };
769 
770 struct npa_aq_enq_rsp {
771 	struct mbox_msghdr hdr;
772 	union {
773 		/* Valid when op == READ and ctype == AURA */
774 		struct npa_aura_s aura;
775 		/* Valid when op == READ and ctype == POOL */
776 		struct npa_pool_s pool;
777 	};
778 };
779 
780 /* Disable all contexts of type 'ctype' */
781 struct hwctx_disable_req {
782 	struct mbox_msghdr hdr;
783 	u8 ctype;
784 };
785 
786 /* NIX mbox message formats */
787 
788 /* NIX mailbox error codes
789  * Range 401 - 500.
790  */
791 enum nix_af_status {
792 	NIX_AF_ERR_PARAM            = -401,
793 	NIX_AF_ERR_AQ_FULL          = -402,
794 	NIX_AF_ERR_AQ_ENQUEUE       = -403,
795 	NIX_AF_ERR_AF_LF_INVALID    = -404,
796 	NIX_AF_ERR_AF_LF_ALLOC      = -405,
797 	NIX_AF_ERR_TLX_ALLOC_FAIL   = -406,
798 	NIX_AF_ERR_TLX_INVALID      = -407,
799 	NIX_AF_ERR_RSS_SIZE_INVALID = -408,
800 	NIX_AF_ERR_RSS_GRPS_INVALID = -409,
801 	NIX_AF_ERR_FRS_INVALID      = -410,
802 	NIX_AF_ERR_RX_LINK_INVALID  = -411,
803 	NIX_AF_INVAL_TXSCHQ_CFG     = -412,
804 	NIX_AF_SMQ_FLUSH_FAILED     = -413,
805 	NIX_AF_ERR_LF_RESET         = -414,
806 	NIX_AF_ERR_RSS_NOSPC_FIELD  = -415,
807 	NIX_AF_ERR_RSS_NOSPC_ALGO   = -416,
808 	NIX_AF_ERR_MARK_CFG_FAIL    = -417,
809 	NIX_AF_ERR_LSO_CFG_FAIL     = -418,
810 	NIX_AF_INVAL_NPA_PF_FUNC    = -419,
811 	NIX_AF_INVAL_SSO_PF_FUNC    = -420,
812 	NIX_AF_ERR_TX_VTAG_NOSPC    = -421,
813 	NIX_AF_ERR_RX_VTAG_INUSE    = -422,
814 	NIX_AF_ERR_PTP_CONFIG_FAIL  = -423,
815 	NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424,
816 	NIX_AF_ERR_INVALID_NIXBLK   = -425,
817 	NIX_AF_ERR_INVALID_BANDPROF = -426,
818 	NIX_AF_ERR_IPOLICER_NOTSUPP = -427,
819 	NIX_AF_ERR_BANDPROF_INVAL_REQ  = -428,
820 	NIX_AF_ERR_CQ_CTX_WRITE_ERR  = -429,
821 	NIX_AF_ERR_AQ_CTX_RETRY_WRITE  = -430,
822 	NIX_AF_ERR_LINK_CREDITS  = -431,
823 };
824 
825 /* For NIX RX vtag action  */
826 enum nix_rx_vtag0_type {
827 	NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */
828 	NIX_AF_LFX_RX_VTAG_TYPE1,
829 	NIX_AF_LFX_RX_VTAG_TYPE2,
830 	NIX_AF_LFX_RX_VTAG_TYPE3,
831 	NIX_AF_LFX_RX_VTAG_TYPE4,
832 	NIX_AF_LFX_RX_VTAG_TYPE5,
833 	NIX_AF_LFX_RX_VTAG_TYPE6,
834 	NIX_AF_LFX_RX_VTAG_TYPE7,
835 };
836 
837 /* For NIX LF context alloc and init */
838 struct nix_lf_alloc_req {
839 	struct mbox_msghdr hdr;
840 	int node;
841 	u32 rq_cnt;   /* No of receive queues */
842 	u32 sq_cnt;   /* No of send queues */
843 	u32 cq_cnt;   /* No of completion queues */
844 	u8  xqe_sz;
845 	u16 rss_sz;
846 	u8  rss_grps;
847 	u16 npa_func;
848 	u16 sso_func;
849 	u64 rx_cfg;   /* See NIX_AF_LF(0..127)_RX_CFG */
850 	u64 way_mask;
851 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)
852 #define NIX_LF_LBK_BLK_SEL	    BIT_ULL(1)
853 	u64 flags;
854 };
855 
856 struct nix_lf_alloc_rsp {
857 	struct mbox_msghdr hdr;
858 	u16	sqb_size;
859 	u16	rx_chan_base;
860 	u16	tx_chan_base;
861 	u8      rx_chan_cnt; /* total number of RX channels */
862 	u8      tx_chan_cnt; /* total number of TX channels */
863 	u8	lso_tsov4_idx;
864 	u8	lso_tsov6_idx;
865 	u8      mac_addr[ETH_ALEN];
866 	u8	lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
867 	u8	lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
868 	u16	cints; /* NIX_AF_CONST2::CINTS */
869 	u16	qints; /* NIX_AF_CONST2::QINTS */
870 	u8	cgx_links;  /* No. of CGX links present in HW */
871 	u8	lbk_links;  /* No. of LBK links present in HW */
872 	u8	sdp_links;  /* No. of SDP links present in HW */
873 	u8	tx_link;    /* Transmit channel link number */
874 };
875 
876 struct nix_lf_free_req {
877 	struct mbox_msghdr hdr;
878 #define NIX_LF_DISABLE_FLOWS		BIT_ULL(0)
879 #define NIX_LF_DONT_FREE_TX_VTAG	BIT_ULL(1)
880 	u64 flags;
881 };
882 
883 /* CN10K NIX AQ enqueue msg */
884 struct nix_cn10k_aq_enq_req {
885 	struct mbox_msghdr hdr;
886 	u32  qidx;
887 	u8 ctype;
888 	u8 op;
889 	union {
890 		struct nix_cn10k_rq_ctx_s rq;
891 		struct nix_cn10k_sq_ctx_s sq;
892 		struct nix_cq_ctx_s cq;
893 		struct nix_rsse_s   rss;
894 		struct nix_rx_mce_s mce;
895 		struct nix_bandprof_s prof;
896 	};
897 	union {
898 		struct nix_cn10k_rq_ctx_s rq_mask;
899 		struct nix_cn10k_sq_ctx_s sq_mask;
900 		struct nix_cq_ctx_s cq_mask;
901 		struct nix_rsse_s   rss_mask;
902 		struct nix_rx_mce_s mce_mask;
903 		struct nix_bandprof_s prof_mask;
904 	};
905 };
906 
907 struct nix_cn10k_aq_enq_rsp {
908 	struct mbox_msghdr hdr;
909 	union {
910 		struct nix_cn10k_rq_ctx_s rq;
911 		struct nix_cn10k_sq_ctx_s sq;
912 		struct nix_cq_ctx_s cq;
913 		struct nix_rsse_s   rss;
914 		struct nix_rx_mce_s mce;
915 		struct nix_bandprof_s prof;
916 	};
917 };
918 
919 /* NIX AQ enqueue msg */
920 struct nix_aq_enq_req {
921 	struct mbox_msghdr hdr;
922 	u32  qidx;
923 	u8 ctype;
924 	u8 op;
925 	union {
926 		struct nix_rq_ctx_s rq;
927 		struct nix_sq_ctx_s sq;
928 		struct nix_cq_ctx_s cq;
929 		struct nix_rsse_s   rss;
930 		struct nix_rx_mce_s mce;
931 		u64 prof;
932 	};
933 	union {
934 		struct nix_rq_ctx_s rq_mask;
935 		struct nix_sq_ctx_s sq_mask;
936 		struct nix_cq_ctx_s cq_mask;
937 		struct nix_rsse_s   rss_mask;
938 		struct nix_rx_mce_s mce_mask;
939 		u64 prof_mask;
940 	};
941 };
942 
943 struct nix_aq_enq_rsp {
944 	struct mbox_msghdr hdr;
945 	union {
946 		struct nix_rq_ctx_s rq;
947 		struct nix_sq_ctx_s sq;
948 		struct nix_cq_ctx_s cq;
949 		struct nix_rsse_s   rss;
950 		struct nix_rx_mce_s mce;
951 		struct nix_bandprof_s prof;
952 	};
953 };
954 
955 /* Tx scheduler/shaper mailbox messages */
956 
957 #define MAX_TXSCHQ_PER_FUNC		128
958 
959 struct nix_txsch_alloc_req {
960 	struct mbox_msghdr hdr;
961 	/* Scheduler queue count request at each level */
962 	u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */
963 	u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */
964 };
965 
966 struct nix_txsch_alloc_rsp {
967 	struct mbox_msghdr hdr;
968 	/* Scheduler queue count allocated at each level */
969 	u16 schq_contig[NIX_TXSCH_LVL_CNT];
970 	u16 schq[NIX_TXSCH_LVL_CNT];
971 	/* Scheduler queue list allocated at each level */
972 	u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
973 	u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
974 	u8  aggr_level; /* Traffic aggregation scheduler level */
975 	u8  aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */
976 	u8  link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
977 };
978 
979 struct nix_txsch_free_req {
980 	struct mbox_msghdr hdr;
981 #define TXSCHQ_FREE_ALL BIT_ULL(0)
982 	u16 flags;
983 	/* Scheduler queue level to be freed */
984 	u16 schq_lvl;
985 	/* List of scheduler queues to be freed */
986 	u16 schq;
987 };
988 
989 struct nix_txschq_config {
990 	struct mbox_msghdr hdr;
991 	u8 lvl;	/* SMQ/MDQ/TL4/TL3/TL2/TL1 */
992 	u8 read;
993 #define TXSCHQ_IDX_SHIFT	16
994 #define TXSCHQ_IDX_MASK		(BIT_ULL(10) - 1)
995 #define TXSCHQ_IDX(reg, shift)	(((reg) >> (shift)) & TXSCHQ_IDX_MASK)
996 	u8 num_regs;
997 #define MAX_REGS_PER_MBOX_MSG	20
998 	u64 reg[MAX_REGS_PER_MBOX_MSG];
999 	u64 regval[MAX_REGS_PER_MBOX_MSG];
1000 	/* All 0's => overwrite with new value */
1001 	u64 regval_mask[MAX_REGS_PER_MBOX_MSG];
1002 };
1003 
1004 struct nix_vtag_config {
1005 	struct mbox_msghdr hdr;
1006 	/* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
1007 	u8 vtag_size;
1008 	/* cfg_type is '0' for tx vlan cfg
1009 	 * cfg_type is '1' for rx vlan cfg
1010 	 */
1011 	u8 cfg_type;
1012 	union {
1013 		/* valid when cfg_type is '0' */
1014 		struct {
1015 			u64 vtag0;
1016 			u64 vtag1;
1017 
1018 			/* cfg_vtag0 & cfg_vtag1 fields are valid
1019 			 * when free_vtag0 & free_vtag1 are '0's.
1020 			 */
1021 			/* cfg_vtag0 = 1 to configure vtag0 */
1022 			u8 cfg_vtag0 :1;
1023 			/* cfg_vtag1 = 1 to configure vtag1 */
1024 			u8 cfg_vtag1 :1;
1025 
1026 			/* vtag0_idx & vtag1_idx are only valid when
1027 			 * both cfg_vtag0 & cfg_vtag1 are '0's,
1028 			 * these fields are used along with free_vtag0
1029 			 * & free_vtag1 to free the nix lf's tx_vlan
1030 			 * configuration.
1031 			 *
1032 			 * Denotes the indices of tx_vtag def registers
1033 			 * that needs to be cleared and freed.
1034 			 */
1035 			int vtag0_idx;
1036 			int vtag1_idx;
1037 
1038 			/* free_vtag0 & free_vtag1 fields are valid
1039 			 * when cfg_vtag0 & cfg_vtag1 are '0's.
1040 			 */
1041 			/* free_vtag0 = 1 clears vtag0 configuration
1042 			 * vtag0_idx denotes the index to be cleared.
1043 			 */
1044 			u8 free_vtag0 :1;
1045 			/* free_vtag1 = 1 clears vtag1 configuration
1046 			 * vtag1_idx denotes the index to be cleared.
1047 			 */
1048 			u8 free_vtag1 :1;
1049 		} tx;
1050 
1051 		/* valid when cfg_type is '1' */
1052 		struct {
1053 			/* rx vtag type index, valid values are in 0..7 range */
1054 			u8 vtag_type;
1055 			/* rx vtag strip */
1056 			u8 strip_vtag :1;
1057 			/* rx vtag capture */
1058 			u8 capture_vtag :1;
1059 		} rx;
1060 	};
1061 };
1062 
1063 struct nix_vtag_config_rsp {
1064 	struct mbox_msghdr hdr;
1065 	int vtag0_idx;
1066 	int vtag1_idx;
1067 	/* Indices of tx_vtag def registers used to configure
1068 	 * tx vtag0 & vtag1 headers, these indices are valid
1069 	 * when nix_vtag_config mbox requested for vtag0 and/
1070 	 * or vtag1 configuration.
1071 	 */
1072 };
1073 
1074 struct nix_rss_flowkey_cfg {
1075 	struct mbox_msghdr hdr;
1076 	int	mcam_index;  /* MCAM entry index to modify */
1077 #define NIX_FLOW_KEY_TYPE_PORT	BIT(0)
1078 #define NIX_FLOW_KEY_TYPE_IPV4	BIT(1)
1079 #define NIX_FLOW_KEY_TYPE_IPV6	BIT(2)
1080 #define NIX_FLOW_KEY_TYPE_TCP	BIT(3)
1081 #define NIX_FLOW_KEY_TYPE_UDP	BIT(4)
1082 #define NIX_FLOW_KEY_TYPE_SCTP	BIT(5)
1083 #define NIX_FLOW_KEY_TYPE_NVGRE    BIT(6)
1084 #define NIX_FLOW_KEY_TYPE_VXLAN    BIT(7)
1085 #define NIX_FLOW_KEY_TYPE_GENEVE   BIT(8)
1086 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9)
1087 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10)
1088 #define NIX_FLOW_KEY_TYPE_GTPU       BIT(11)
1089 #define NIX_FLOW_KEY_TYPE_INNR_IPV4     BIT(12)
1090 #define NIX_FLOW_KEY_TYPE_INNR_IPV6     BIT(13)
1091 #define NIX_FLOW_KEY_TYPE_INNR_TCP      BIT(14)
1092 #define NIX_FLOW_KEY_TYPE_INNR_UDP      BIT(15)
1093 #define NIX_FLOW_KEY_TYPE_INNR_SCTP     BIT(16)
1094 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
1095 #define NIX_FLOW_KEY_TYPE_VLAN		BIT(20)
1096 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO	BIT(21)
1097 #define NIX_FLOW_KEY_TYPE_AH		BIT(22)
1098 #define NIX_FLOW_KEY_TYPE_ESP		BIT(23)
1099 	u32	flowkey_cfg; /* Flowkey types selected */
1100 	u8	group;       /* RSS context or group */
1101 };
1102 
1103 struct nix_rss_flowkey_cfg_rsp {
1104 	struct mbox_msghdr hdr;
1105 	u8	alg_idx; /* Selected algo index */
1106 };
1107 
1108 struct nix_set_mac_addr {
1109 	struct mbox_msghdr hdr;
1110 	u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */
1111 };
1112 
1113 struct nix_get_mac_addr_rsp {
1114 	struct mbox_msghdr hdr;
1115 	u8 mac_addr[ETH_ALEN];
1116 };
1117 
1118 struct nix_mark_format_cfg {
1119 	struct mbox_msghdr hdr;
1120 	u8 offset;
1121 	u8 y_mask;
1122 	u8 y_val;
1123 	u8 r_mask;
1124 	u8 r_val;
1125 };
1126 
1127 struct nix_mark_format_cfg_rsp {
1128 	struct mbox_msghdr hdr;
1129 	u8 mark_format_idx;
1130 };
1131 
1132 struct nix_rx_mode {
1133 	struct mbox_msghdr hdr;
1134 #define NIX_RX_MODE_UCAST	BIT(0)
1135 #define NIX_RX_MODE_PROMISC	BIT(1)
1136 #define NIX_RX_MODE_ALLMULTI	BIT(2)
1137 #define NIX_RX_MODE_USE_MCE	BIT(3)
1138 	u16	mode;
1139 };
1140 
1141 struct nix_rx_cfg {
1142 	struct mbox_msghdr hdr;
1143 #define NIX_RX_OL3_VERIFY   BIT(0)
1144 #define NIX_RX_OL4_VERIFY   BIT(1)
1145 	u8 len_verify; /* Outer L3/L4 len check */
1146 #define NIX_RX_CSUM_OL4_VERIFY  BIT(0)
1147 	u8 csum_verify; /* Outer L4 checksum verification */
1148 };
1149 
1150 struct nix_frs_cfg {
1151 	struct mbox_msghdr hdr;
1152 	u8	update_smq;    /* Update SMQ's min/max lens */
1153 	u8	update_minlen; /* Set minlen also */
1154 	u8	sdp_link;      /* Set SDP RX link */
1155 	u16	maxlen;
1156 	u16	minlen;
1157 };
1158 
1159 struct nix_lso_format_cfg {
1160 	struct mbox_msghdr hdr;
1161 	u64 field_mask;
1162 #define NIX_LSO_FIELD_MAX	8
1163 	u64 fields[NIX_LSO_FIELD_MAX];
1164 };
1165 
1166 struct nix_lso_format_cfg_rsp {
1167 	struct mbox_msghdr hdr;
1168 	u8 lso_format_idx;
1169 };
1170 
1171 struct nix_bp_cfg_req {
1172 	struct mbox_msghdr hdr;
1173 	u16	chan_base; /* Starting channel number */
1174 	u8	chan_cnt; /* Number of channels */
1175 	u8	bpid_per_chan;
1176 	/* bpid_per_chan = 0 assigns single bp id for range of channels */
1177 	/* bpid_per_chan = 1 assigns separate bp id for each channel */
1178 };
1179 
1180 /* PF can be mapped to either CGX or LBK interface,
1181  * so maximum 64 channels are possible.
1182  */
1183 #define NIX_MAX_BPID_CHAN	64
1184 struct nix_bp_cfg_rsp {
1185 	struct mbox_msghdr hdr;
1186 	u16	chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */
1187 	u8	chan_cnt; /* Number of channel for which bpids are assigned */
1188 };
1189 
1190 /* Global NIX inline IPSec configuration */
1191 struct nix_inline_ipsec_cfg {
1192 	struct mbox_msghdr hdr;
1193 	u32 cpt_credit;
1194 	struct {
1195 		u8 egrp;
1196 		u8 opcode;
1197 		u16 param1;
1198 		u16 param2;
1199 	} gen_cfg;
1200 	struct {
1201 		u16 cpt_pf_func;
1202 		u8 cpt_slot;
1203 	} inst_qsel;
1204 	u8 enable;
1205 };
1206 
1207 /* Per NIX LF inline IPSec configuration */
1208 struct nix_inline_ipsec_lf_cfg {
1209 	struct mbox_msghdr hdr;
1210 	u64 sa_base_addr;
1211 	struct {
1212 		u32 tag_const;
1213 		u16 lenm1_max;
1214 		u8 sa_pow2_size;
1215 		u8 tt;
1216 	} ipsec_cfg0;
1217 	struct {
1218 		u32 sa_idx_max;
1219 		u8 sa_idx_w;
1220 	} ipsec_cfg1;
1221 	u8 enable;
1222 };
1223 
1224 struct nix_hw_info {
1225 	struct mbox_msghdr hdr;
1226 	u16 rsvs16;
1227 	u16 max_mtu;
1228 	u16 min_mtu;
1229 	u32 rpm_dwrr_mtu;
1230 	u32 sdp_dwrr_mtu;
1231 	u64 rsvd[16]; /* Add reserved fields for future expansion */
1232 };
1233 
1234 struct nix_bandprof_alloc_req {
1235 	struct mbox_msghdr hdr;
1236 	/* Count of profiles needed per layer */
1237 	u16 prof_count[BAND_PROF_NUM_LAYERS];
1238 };
1239 
1240 struct nix_bandprof_alloc_rsp {
1241 	struct mbox_msghdr hdr;
1242 	u16 prof_count[BAND_PROF_NUM_LAYERS];
1243 
1244 	/* There is no need to allocate morethan 1 bandwidth profile
1245 	 * per RQ of a PF_FUNC's NIXLF. So limit the maximum
1246 	 * profiles to 64 per PF_FUNC.
1247 	 */
1248 #define MAX_BANDPROF_PER_PFFUNC	64
1249 	u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];
1250 };
1251 
1252 struct nix_bandprof_free_req {
1253 	struct mbox_msghdr hdr;
1254 	u8 free_all;
1255 	u16 prof_count[BAND_PROF_NUM_LAYERS];
1256 	u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];
1257 };
1258 
1259 struct nix_bandprof_get_hwinfo_rsp {
1260 	struct mbox_msghdr hdr;
1261 	u16 prof_count[BAND_PROF_NUM_LAYERS];
1262 	u32 policer_timeunit;
1263 };
1264 
1265 /* NPC mbox message structs */
1266 
1267 #define NPC_MCAM_ENTRY_INVALID	0xFFFF
1268 #define NPC_MCAM_INVALID_MAP	0xFFFF
1269 
1270 /* NPC mailbox error codes
1271  * Range 701 - 800.
1272  */
1273 enum npc_af_status {
1274 	NPC_MCAM_INVALID_REQ	= -701,
1275 	NPC_MCAM_ALLOC_DENIED	= -702,
1276 	NPC_MCAM_ALLOC_FAILED	= -703,
1277 	NPC_MCAM_PERM_DENIED	= -704,
1278 	NPC_FLOW_INTF_INVALID	= -707,
1279 	NPC_FLOW_CHAN_INVALID	= -708,
1280 	NPC_FLOW_NO_NIXLF	= -709,
1281 	NPC_FLOW_NOT_SUPPORTED	= -710,
1282 	NPC_FLOW_VF_PERM_DENIED	= -711,
1283 	NPC_FLOW_VF_NOT_INIT	= -712,
1284 	NPC_FLOW_VF_OVERLAP	= -713,
1285 };
1286 
1287 struct npc_mcam_alloc_entry_req {
1288 	struct mbox_msghdr hdr;
1289 #define NPC_MAX_NONCONTIG_ENTRIES	256
1290 	u8  contig;   /* Contiguous entries ? */
1291 #define NPC_MCAM_ANY_PRIO		0
1292 #define NPC_MCAM_LOWER_PRIO		1
1293 #define NPC_MCAM_HIGHER_PRIO		2
1294 	u8  priority; /* Lower or higher w.r.t ref_entry */
1295 	u16 ref_entry;
1296 	u16 count;    /* Number of entries requested */
1297 };
1298 
1299 struct npc_mcam_alloc_entry_rsp {
1300 	struct mbox_msghdr hdr;
1301 	u16 entry; /* Entry allocated or start index if contiguous.
1302 		    * Invalid incase of non-contiguous.
1303 		    */
1304 	u16 count; /* Number of entries allocated */
1305 	u16 free_count; /* Number of entries available */
1306 	u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1307 };
1308 
1309 struct npc_mcam_free_entry_req {
1310 	struct mbox_msghdr hdr;
1311 	u16 entry; /* Entry index to be freed */
1312 	u8  all;   /* If all entries allocated to this PFVF to be freed */
1313 };
1314 
1315 struct mcam_entry {
1316 #define NPC_MAX_KWS_IN_KEY	7 /* Number of keywords in max keywidth */
1317 	u64	kw[NPC_MAX_KWS_IN_KEY];
1318 	u64	kw_mask[NPC_MAX_KWS_IN_KEY];
1319 	u64	action;
1320 	u64	vtag_action;
1321 };
1322 
1323 struct npc_mcam_write_entry_req {
1324 	struct mbox_msghdr hdr;
1325 	struct mcam_entry entry_data;
1326 	u16 entry;	 /* MCAM entry to write this match key */
1327 	u16 cntr;	 /* Counter for this MCAM entry */
1328 	u8  intf;	 /* Rx or Tx interface */
1329 	u8  enable_entry;/* Enable this MCAM entry ? */
1330 	u8  set_cntr;    /* Set counter for this entry ? */
1331 };
1332 
1333 /* Enable/Disable a given entry */
1334 struct npc_mcam_ena_dis_entry_req {
1335 	struct mbox_msghdr hdr;
1336 	u16 entry;
1337 };
1338 
1339 struct npc_mcam_shift_entry_req {
1340 	struct mbox_msghdr hdr;
1341 #define NPC_MCAM_MAX_SHIFTS	64
1342 	u16 curr_entry[NPC_MCAM_MAX_SHIFTS];
1343 	u16 new_entry[NPC_MCAM_MAX_SHIFTS];
1344 	u16 shift_count; /* Number of entries to shift */
1345 };
1346 
1347 struct npc_mcam_shift_entry_rsp {
1348 	struct mbox_msghdr hdr;
1349 	u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */
1350 };
1351 
1352 struct npc_mcam_alloc_counter_req {
1353 	struct mbox_msghdr hdr;
1354 	u8  contig;	/* Contiguous counters ? */
1355 #define NPC_MAX_NONCONTIG_COUNTERS       64
1356 	u16 count;	/* Number of counters requested */
1357 };
1358 
1359 struct npc_mcam_alloc_counter_rsp {
1360 	struct mbox_msghdr hdr;
1361 	u16 cntr;   /* Counter allocated or start index if contiguous.
1362 		     * Invalid incase of non-contiguous.
1363 		     */
1364 	u16 count;  /* Number of counters allocated */
1365 	u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
1366 };
1367 
1368 struct npc_mcam_oper_counter_req {
1369 	struct mbox_msghdr hdr;
1370 	u16 cntr;   /* Free a counter or clear/fetch it's stats */
1371 };
1372 
1373 struct npc_mcam_oper_counter_rsp {
1374 	struct mbox_msghdr hdr;
1375 	u64 stat;  /* valid only while fetching counter's stats */
1376 };
1377 
1378 struct npc_mcam_unmap_counter_req {
1379 	struct mbox_msghdr hdr;
1380 	u16 cntr;
1381 	u16 entry; /* Entry and counter to be unmapped */
1382 	u8  all;   /* Unmap all entries using this counter ? */
1383 };
1384 
1385 struct npc_mcam_alloc_and_write_entry_req {
1386 	struct mbox_msghdr hdr;
1387 	struct mcam_entry entry_data;
1388 	u16 ref_entry;
1389 	u8  priority;    /* Lower or higher w.r.t ref_entry */
1390 	u8  intf;	 /* Rx or Tx interface */
1391 	u8  enable_entry;/* Enable this MCAM entry ? */
1392 	u8  alloc_cntr;  /* Allocate counter and map ? */
1393 };
1394 
1395 struct npc_mcam_alloc_and_write_entry_rsp {
1396 	struct mbox_msghdr hdr;
1397 	u16 entry;
1398 	u16 cntr;
1399 };
1400 
1401 struct npc_get_kex_cfg_rsp {
1402 	struct mbox_msghdr hdr;
1403 	u64 rx_keyx_cfg;   /* NPC_AF_INTF(0)_KEX_CFG */
1404 	u64 tx_keyx_cfg;   /* NPC_AF_INTF(1)_KEX_CFG */
1405 #define NPC_MAX_INTF	2
1406 #define NPC_MAX_LID	8
1407 #define NPC_MAX_LT	16
1408 #define NPC_MAX_LD	2
1409 #define NPC_MAX_LFL	16
1410 	/* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
1411 	u64 kex_ld_flags[NPC_MAX_LD];
1412 	/* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
1413 	u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
1414 	/* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
1415 	u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
1416 #define MKEX_NAME_LEN 128
1417 	u8 mkex_pfl_name[MKEX_NAME_LEN];
1418 };
1419 
1420 struct flow_msg {
1421 	unsigned char dmac[6];
1422 	unsigned char smac[6];
1423 	__be16 etype;
1424 	__be16 vlan_etype;
1425 	__be16 vlan_tci;
1426 	union {
1427 		__be32 ip4src;
1428 		__be32 ip6src[4];
1429 	};
1430 	union {
1431 		__be32 ip4dst;
1432 		__be32 ip6dst[4];
1433 	};
1434 	u8 tos;
1435 	u8 ip_ver;
1436 	u8 ip_proto;
1437 	u8 tc;
1438 	__be16 sport;
1439 	__be16 dport;
1440 };
1441 
1442 struct npc_install_flow_req {
1443 	struct mbox_msghdr hdr;
1444 	struct flow_msg packet;
1445 	struct flow_msg mask;
1446 	u64 features;
1447 	u16 entry;
1448 	u16 channel;
1449 	u16 chan_mask;
1450 	u8 intf;
1451 	u8 set_cntr; /* If counter is available set counter for this entry ? */
1452 	u8 default_rule;
1453 	u8 append; /* overwrite(0) or append(1) flow to default rule? */
1454 	u16 vf;
1455 	/* action */
1456 	u32 index;
1457 	u16 match_id;
1458 	u8 flow_key_alg;
1459 	u8 op;
1460 	/* vtag rx action */
1461 	u8 vtag0_type;
1462 	u8 vtag0_valid;
1463 	u8 vtag1_type;
1464 	u8 vtag1_valid;
1465 	/* vtag tx action */
1466 	u16 vtag0_def;
1467 	u8  vtag0_op;
1468 	u16 vtag1_def;
1469 	u8  vtag1_op;
1470 };
1471 
1472 struct npc_install_flow_rsp {
1473 	struct mbox_msghdr hdr;
1474 	int counter; /* negative if no counter else counter number */
1475 };
1476 
1477 struct npc_delete_flow_req {
1478 	struct mbox_msghdr hdr;
1479 	u16 entry;
1480 	u16 start;/*Disable range of entries */
1481 	u16 end;
1482 	u8 all; /* PF + VFs */
1483 };
1484 
1485 struct npc_mcam_read_entry_req {
1486 	struct mbox_msghdr hdr;
1487 	u16 entry;	 /* MCAM entry to read */
1488 };
1489 
1490 struct npc_mcam_read_entry_rsp {
1491 	struct mbox_msghdr hdr;
1492 	struct mcam_entry entry_data;
1493 	u8 intf;
1494 	u8 enable;
1495 };
1496 
1497 struct npc_mcam_read_base_rule_rsp {
1498 	struct mbox_msghdr hdr;
1499 	struct mcam_entry entry;
1500 };
1501 
1502 struct npc_mcam_get_stats_req {
1503 	struct mbox_msghdr hdr;
1504 	u16 entry; /* mcam entry */
1505 };
1506 
1507 struct npc_mcam_get_stats_rsp {
1508 	struct mbox_msghdr hdr;
1509 	u64 stat;  /* counter stats */
1510 	u8 stat_ena; /* enabled */
1511 };
1512 
1513 struct npc_get_secret_key_req {
1514 	struct mbox_msghdr hdr;
1515 	u8 intf;
1516 };
1517 
1518 struct npc_get_secret_key_rsp {
1519 	struct mbox_msghdr hdr;
1520 	u64 secret_key[3];
1521 };
1522 
1523 enum ptp_op {
1524 	PTP_OP_ADJFINE = 0,
1525 	PTP_OP_GET_CLOCK = 1,
1526 	PTP_OP_GET_TSTMP = 2,
1527 	PTP_OP_SET_THRESH = 3,
1528 	PTP_OP_EXTTS_ON = 4,
1529 };
1530 
1531 struct ptp_req {
1532 	struct mbox_msghdr hdr;
1533 	u8 op;
1534 	s64 scaled_ppm;
1535 	u64 thresh;
1536 	int extts_on;
1537 };
1538 
1539 struct ptp_rsp {
1540 	struct mbox_msghdr hdr;
1541 	u64 clk;
1542 };
1543 
1544 struct set_vf_perm  {
1545 	struct  mbox_msghdr hdr;
1546 	u16	vf;
1547 #define RESET_VF_PERM		BIT_ULL(0)
1548 #define	VF_TRUSTED		BIT_ULL(1)
1549 	u64	flags;
1550 };
1551 
1552 struct lmtst_tbl_setup_req {
1553 	struct mbox_msghdr hdr;
1554 	u64 dis_sched_early_comp :1;
1555 	u64 sch_ena		 :1;
1556 	u64 dis_line_pref	 :1;
1557 	u64 ssow_pf_func	 :13;
1558 	u16 base_pcifunc;
1559 	u8  use_local_lmt_region;
1560 	u64 lmt_iova;
1561 	u64 rsvd[4];
1562 };
1563 
1564 /* CPT mailbox error codes
1565  * Range 901 - 1000.
1566  */
1567 enum cpt_af_status {
1568 	CPT_AF_ERR_PARAM		= -901,
1569 	CPT_AF_ERR_GRP_INVALID		= -902,
1570 	CPT_AF_ERR_LF_INVALID		= -903,
1571 	CPT_AF_ERR_ACCESS_DENIED	= -904,
1572 	CPT_AF_ERR_SSO_PF_FUNC_INVALID	= -905,
1573 	CPT_AF_ERR_NIX_PF_FUNC_INVALID	= -906,
1574 	CPT_AF_ERR_INLINE_IPSEC_INB_ENA	= -907,
1575 	CPT_AF_ERR_INLINE_IPSEC_OUT_ENA	= -908
1576 };
1577 
1578 /* CPT mbox message formats */
1579 struct cpt_rd_wr_reg_msg {
1580 	struct mbox_msghdr hdr;
1581 	u64 reg_offset;
1582 	u64 *ret_val;
1583 	u64 val;
1584 	u8 is_write;
1585 	int blkaddr;
1586 };
1587 
1588 struct cpt_lf_alloc_req_msg {
1589 	struct mbox_msghdr hdr;
1590 	u16 nix_pf_func;
1591 	u16 sso_pf_func;
1592 	u16 eng_grpmsk;
1593 	int blkaddr;
1594 };
1595 
1596 #define CPT_INLINE_INBOUND      0
1597 #define CPT_INLINE_OUTBOUND     1
1598 
1599 /* Mailbox message request format for CPT IPsec
1600  * inline inbound and outbound configuration.
1601  */
1602 struct cpt_inline_ipsec_cfg_msg {
1603 	struct mbox_msghdr hdr;
1604 	u8 enable;
1605 	u8 slot;
1606 	u8 dir;
1607 	u8 sso_pf_func_ovrd;
1608 	u16 sso_pf_func; /* inbound path SSO_PF_FUNC */
1609 	u16 nix_pf_func; /* outbound path NIX_PF_FUNC */
1610 };
1611 
1612 /* Mailbox message request and response format for CPT stats. */
1613 struct cpt_sts_req {
1614 	struct mbox_msghdr hdr;
1615 	u8 blkaddr;
1616 };
1617 
1618 struct cpt_sts_rsp {
1619 	struct mbox_msghdr hdr;
1620 	u64 inst_req_pc;
1621 	u64 inst_lat_pc;
1622 	u64 rd_req_pc;
1623 	u64 rd_lat_pc;
1624 	u64 rd_uc_pc;
1625 	u64 active_cycles_pc;
1626 	u64 ctx_mis_pc;
1627 	u64 ctx_hit_pc;
1628 	u64 ctx_aop_pc;
1629 	u64 ctx_aop_lat_pc;
1630 	u64 ctx_ifetch_pc;
1631 	u64 ctx_ifetch_lat_pc;
1632 	u64 ctx_ffetch_pc;
1633 	u64 ctx_ffetch_lat_pc;
1634 	u64 ctx_wback_pc;
1635 	u64 ctx_wback_lat_pc;
1636 	u64 ctx_psh_pc;
1637 	u64 ctx_psh_lat_pc;
1638 	u64 ctx_err;
1639 	u64 ctx_enc_id;
1640 	u64 ctx_flush_timer;
1641 	u64 rxc_time;
1642 	u64 rxc_time_cfg;
1643 	u64 rxc_active_sts;
1644 	u64 rxc_zombie_sts;
1645 	u64 busy_sts_ae;
1646 	u64 free_sts_ae;
1647 	u64 busy_sts_se;
1648 	u64 free_sts_se;
1649 	u64 busy_sts_ie;
1650 	u64 free_sts_ie;
1651 	u64 exe_err_info;
1652 	u64 cptclk_cnt;
1653 	u64 diag;
1654 	u64 rxc_dfrg;
1655 	u64 x2p_link_cfg0;
1656 	u64 x2p_link_cfg1;
1657 };
1658 
1659 /* Mailbox message request format to configure reassembly timeout. */
1660 struct cpt_rxc_time_cfg_req {
1661 	struct mbox_msghdr hdr;
1662 	int blkaddr;
1663 	u32 step;
1664 	u16 zombie_thres;
1665 	u16 zombie_limit;
1666 	u16 active_thres;
1667 	u16 active_limit;
1668 };
1669 
1670 /* Mailbox message request format to request for CPT_INST_S lmtst. */
1671 struct cpt_inst_lmtst_req {
1672 	struct mbox_msghdr hdr;
1673 	u64 inst[8];
1674 	u64 rsvd;
1675 };
1676 
1677 struct sdp_node_info {
1678 	/* Node to which this PF belons to */
1679 	u8 node_id;
1680 	u8 max_vfs;
1681 	u8 num_pf_rings;
1682 	u8 pf_srn;
1683 #define SDP_MAX_VFS	128
1684 	u8 vf_rings[SDP_MAX_VFS];
1685 };
1686 
1687 struct sdp_chan_info_msg {
1688 	struct mbox_msghdr hdr;
1689 	struct sdp_node_info info;
1690 };
1691 
1692 struct sdp_get_chan_info_msg {
1693 	struct mbox_msghdr hdr;
1694 	u16 chan_base;
1695 	u16 num_chan;
1696 };
1697 
1698 /* CGX mailbox error codes
1699  * Range 1101 - 1200.
1700  */
1701 enum cgx_af_status {
1702 	LMAC_AF_ERR_INVALID_PARAM	= -1101,
1703 	LMAC_AF_ERR_PF_NOT_MAPPED	= -1102,
1704 	LMAC_AF_ERR_PERM_DENIED		= -1103,
1705 	LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED       = -1104,
1706 	LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED = -1105,
1707 	LMAC_AF_ERR_CMD_TIMEOUT = -1106,
1708 	LMAC_AF_ERR_FIRMWARE_DATA_NOT_MAPPED = -1107,
1709 	LMAC_AF_ERR_EXACT_MATCH_TBL_ADD_FAILED = -1108,
1710 	LMAC_AF_ERR_EXACT_MATCH_TBL_DEL_FAILED = -1109,
1711 	LMAC_AF_ERR_EXACT_MATCH_TBL_LOOK_UP_FAILED = -1110,
1712 };
1713 
1714 enum mcs_direction {
1715 	MCS_RX,
1716 	MCS_TX,
1717 };
1718 
1719 enum mcs_rsrc_type {
1720 	MCS_RSRC_TYPE_FLOWID,
1721 	MCS_RSRC_TYPE_SECY,
1722 	MCS_RSRC_TYPE_SC,
1723 	MCS_RSRC_TYPE_SA,
1724 };
1725 
1726 struct mcs_alloc_rsrc_req {
1727 	struct mbox_msghdr hdr;
1728 	u8 rsrc_type;
1729 	u8 rsrc_cnt;	/* Resources count */
1730 	u8 mcs_id;	/* MCS block ID	*/
1731 	u8 dir;		/* Macsec ingress or egress side */
1732 	u8 all;		/* Allocate all resource type one each */
1733 	u64 rsvd;
1734 };
1735 
1736 struct mcs_alloc_rsrc_rsp {
1737 	struct mbox_msghdr hdr;
1738 	u8 flow_ids[128];	/* Index of reserved entries */
1739 	u8 secy_ids[128];
1740 	u8 sc_ids[128];
1741 	u8 sa_ids[256];
1742 	u8 rsrc_type;
1743 	u8 rsrc_cnt;		/* No of entries reserved */
1744 	u8 mcs_id;
1745 	u8 dir;
1746 	u8 all;
1747 	u8 rsvd[256];		/* reserved fields for future expansion */
1748 };
1749 
1750 struct mcs_free_rsrc_req {
1751 	struct mbox_msghdr hdr;
1752 	u8 rsrc_id;		/* Index of the entry to be freed */
1753 	u8 rsrc_type;
1754 	u8 mcs_id;
1755 	u8 dir;
1756 	u8 all;			/* Free all the cam resources */
1757 	u64 rsvd;
1758 };
1759 
1760 struct mcs_flowid_entry_write_req {
1761 	struct mbox_msghdr hdr;
1762 	u64 data[4];
1763 	u64 mask[4];
1764 	u64 sci;	/* CNF10K-B for tx_secy_mem_map */
1765 	u8 flow_id;
1766 	u8 secy_id;	/* secyid for which flowid is mapped */
1767 	u8 sc_id;	/* Valid if dir = MCS_TX, SC_CAM id mapped to flowid */
1768 	u8 ena;		/* Enable tcam entry */
1769 	u8 ctrl_pkt;
1770 	u8 mcs_id;
1771 	u8 dir;
1772 	u64 rsvd;
1773 };
1774 
1775 struct mcs_secy_plcy_write_req {
1776 	struct mbox_msghdr hdr;
1777 	u64 plcy;
1778 	u8 secy_id;
1779 	u8 mcs_id;
1780 	u8 dir;
1781 	u64 rsvd;
1782 };
1783 
1784 /* RX SC_CAM mapping */
1785 struct mcs_rx_sc_cam_write_req {
1786 	struct mbox_msghdr hdr;
1787 	u64 sci;	/* SCI */
1788 	u64 secy_id;	/* secy index mapped to SC */
1789 	u8 sc_id;	/* SC CAM entry index */
1790 	u8 mcs_id;
1791 	u64 rsvd;
1792 };
1793 
1794 struct mcs_sa_plcy_write_req {
1795 	struct mbox_msghdr hdr;
1796 	u64 plcy[2][9];		/* Support 2 SA policy */
1797 	u8 sa_index[2];
1798 	u8 sa_cnt;
1799 	u8 mcs_id;
1800 	u8 dir;
1801 	u64 rsvd;
1802 };
1803 
1804 struct mcs_tx_sc_sa_map {
1805 	struct mbox_msghdr hdr;
1806 	u8 sa_index0;
1807 	u8 sa_index1;
1808 	u8 rekey_ena;
1809 	u8 sa_index0_vld;
1810 	u8 sa_index1_vld;
1811 	u8 tx_sa_active;
1812 	u64 sectag_sci;
1813 	u8 sc_id;	/* used as index for SA_MEM_MAP */
1814 	u8 mcs_id;
1815 	u64 rsvd;
1816 };
1817 
1818 struct mcs_rx_sc_sa_map {
1819 	struct mbox_msghdr hdr;
1820 	u8 sa_index;
1821 	u8 sa_in_use;
1822 	u8 sc_id;
1823 	u8 an;		/* value range 0-3, sc_id + an used as index SA_MEM_MAP */
1824 	u8 mcs_id;
1825 	u64 rsvd;
1826 };
1827 
1828 struct mcs_flowid_ena_dis_entry {
1829 	struct mbox_msghdr hdr;
1830 	u8 flow_id;
1831 	u8 ena;
1832 	u8 mcs_id;
1833 	u8 dir;
1834 	u64 rsvd;
1835 };
1836 
1837 struct mcs_pn_table_write_req {
1838 	struct mbox_msghdr hdr;
1839 	u64 next_pn;
1840 	u8 pn_id;
1841 	u8 mcs_id;
1842 	u8 dir;
1843 	u64 rsvd;
1844 };
1845 
1846 struct mcs_hw_info {
1847 	struct mbox_msghdr hdr;
1848 	u8 num_mcs_blks;	/* Number of MCS blocks */
1849 	u8 tcam_entries;	/* RX/TX Tcam entries per mcs block */
1850 	u8 secy_entries;	/* RX/TX SECY entries per mcs block */
1851 	u8 sc_entries;		/* RX/TX SC CAM entries per mcs block */
1852 	u8 sa_entries;		/* PN table entries = SA entries */
1853 	u64 rsvd[16];
1854 };
1855 
1856 struct mcs_set_active_lmac {
1857 	struct mbox_msghdr hdr;
1858 	u32 lmac_bmap;	/* bitmap of active lmac per mcs block */
1859 	u8 mcs_id;
1860 	u16 chan_base; /* MCS channel base */
1861 	u64 rsvd;
1862 };
1863 
1864 struct mcs_set_lmac_mode {
1865 	struct mbox_msghdr hdr;
1866 	u8 mode;	/* 1:Bypass 0:Operational */
1867 	u8 lmac_id;
1868 	u8 mcs_id;
1869 	u64 rsvd;
1870 };
1871 
1872 struct mcs_port_reset_req {
1873 	struct mbox_msghdr hdr;
1874 	u8 reset;
1875 	u8 mcs_id;
1876 	u8 port_id;
1877 	u64 rsvd;
1878 };
1879 
1880 struct mcs_port_cfg_set_req {
1881 	struct mbox_msghdr hdr;
1882 	u8 cstm_tag_rel_mode_sel;
1883 	u8 custom_hdr_enb;
1884 	u8 fifo_skid;
1885 	u8 port_mode;
1886 	u8 port_id;
1887 	u8 mcs_id;
1888 	u64 rsvd;
1889 };
1890 
1891 struct mcs_port_cfg_get_req {
1892 	struct mbox_msghdr hdr;
1893 	u8 port_id;
1894 	u8 mcs_id;
1895 	u64 rsvd;
1896 };
1897 
1898 struct mcs_port_cfg_get_rsp {
1899 	struct mbox_msghdr hdr;
1900 	u8 cstm_tag_rel_mode_sel;
1901 	u8 custom_hdr_enb;
1902 	u8 fifo_skid;
1903 	u8 port_mode;
1904 	u8 port_id;
1905 	u8 mcs_id;
1906 	u64 rsvd;
1907 };
1908 
1909 struct mcs_custom_tag_cfg_get_req {
1910 	struct mbox_msghdr hdr;
1911 	u8 mcs_id;
1912 	u8 dir;
1913 	u64 rsvd;
1914 };
1915 
1916 struct mcs_custom_tag_cfg_get_rsp {
1917 	struct mbox_msghdr hdr;
1918 	u16 cstm_etype[8];
1919 	u8 cstm_indx[8];
1920 	u8 cstm_etype_en;
1921 	u8 mcs_id;
1922 	u8 dir;
1923 	u64 rsvd;
1924 };
1925 
1926 /* MCS mailbox error codes
1927  * Range 1201 - 1300.
1928  */
1929 enum mcs_af_status {
1930 	MCS_AF_ERR_INVALID_MCSID        = -1201,
1931 	MCS_AF_ERR_NOT_MAPPED           = -1202,
1932 };
1933 
1934 struct mcs_set_pn_threshold {
1935 	struct mbox_msghdr hdr;
1936 	u64 threshold;
1937 	u8 xpn; /* '1' for setting xpn threshold */
1938 	u8 mcs_id;
1939 	u8 dir;
1940 	u64 rsvd;
1941 };
1942 
1943 enum mcs_ctrl_pkt_rulew_type {
1944 	MCS_CTRL_PKT_RULE_TYPE_ETH,
1945 	MCS_CTRL_PKT_RULE_TYPE_DA,
1946 	MCS_CTRL_PKT_RULE_TYPE_RANGE,
1947 	MCS_CTRL_PKT_RULE_TYPE_COMBO,
1948 	MCS_CTRL_PKT_RULE_TYPE_MAC,
1949 };
1950 
1951 struct mcs_alloc_ctrl_pkt_rule_req {
1952 	struct mbox_msghdr hdr;
1953 	u8 rule_type;
1954 	u8 mcs_id;	/* MCS block ID	*/
1955 	u8 dir;		/* Macsec ingress or egress side */
1956 	u64 rsvd;
1957 };
1958 
1959 struct mcs_alloc_ctrl_pkt_rule_rsp {
1960 	struct mbox_msghdr hdr;
1961 	u8 rule_idx;
1962 	u8 rule_type;
1963 	u8 mcs_id;
1964 	u8 dir;
1965 	u64 rsvd;
1966 };
1967 
1968 struct mcs_free_ctrl_pkt_rule_req {
1969 	struct mbox_msghdr hdr;
1970 	u8 rule_idx;
1971 	u8 rule_type;
1972 	u8 mcs_id;
1973 	u8 dir;
1974 	u8 all;
1975 	u64 rsvd;
1976 };
1977 
1978 struct mcs_ctrl_pkt_rule_write_req {
1979 	struct mbox_msghdr hdr;
1980 	u64 data0;
1981 	u64 data1;
1982 	u64 data2;
1983 	u8 rule_idx;
1984 	u8 rule_type;
1985 	u8 mcs_id;
1986 	u8 dir;
1987 	u64 rsvd;
1988 };
1989 
1990 struct mcs_stats_req {
1991 	struct mbox_msghdr hdr;
1992 	u8 id;
1993 	u8 mcs_id;
1994 	u8 dir;
1995 	u64 rsvd;
1996 };
1997 
1998 struct mcs_flowid_stats {
1999 	struct mbox_msghdr hdr;
2000 	u64 tcam_hit_cnt;
2001 	u64 rsvd;
2002 };
2003 
2004 struct mcs_secy_stats {
2005 	struct mbox_msghdr hdr;
2006 	u64 ctl_pkt_bcast_cnt;
2007 	u64 ctl_pkt_mcast_cnt;
2008 	u64 ctl_pkt_ucast_cnt;
2009 	u64 ctl_octet_cnt;
2010 	u64 unctl_pkt_bcast_cnt;
2011 	u64 unctl_pkt_mcast_cnt;
2012 	u64 unctl_pkt_ucast_cnt;
2013 	u64 unctl_octet_cnt;
2014 	/* Valid only for RX */
2015 	u64 octet_decrypted_cnt;
2016 	u64 octet_validated_cnt;
2017 	u64 pkt_port_disabled_cnt;
2018 	u64 pkt_badtag_cnt;
2019 	u64 pkt_nosa_cnt;
2020 	u64 pkt_nosaerror_cnt;
2021 	u64 pkt_tagged_ctl_cnt;
2022 	u64 pkt_untaged_cnt;
2023 	u64 pkt_ctl_cnt;	/* CN10K-B */
2024 	u64 pkt_notag_cnt;	/* CNF10K-B */
2025 	/* Valid only for TX */
2026 	u64 octet_encrypted_cnt;
2027 	u64 octet_protected_cnt;
2028 	u64 pkt_noactivesa_cnt;
2029 	u64 pkt_toolong_cnt;
2030 	u64 pkt_untagged_cnt;
2031 	u64 rsvd[4];
2032 };
2033 
2034 struct mcs_port_stats {
2035 	struct mbox_msghdr hdr;
2036 	u64 tcam_miss_cnt;
2037 	u64 parser_err_cnt;
2038 	u64 preempt_err_cnt;  /* CNF10K-B */
2039 	u64 sectag_insert_err_cnt;
2040 	u64 rsvd[4];
2041 };
2042 
2043 /* Only for CN10K-B */
2044 struct mcs_sa_stats {
2045 	struct mbox_msghdr hdr;
2046 	/* RX */
2047 	u64 pkt_invalid_cnt;
2048 	u64 pkt_nosaerror_cnt;
2049 	u64 pkt_notvalid_cnt;
2050 	u64 pkt_ok_cnt;
2051 	u64 pkt_nosa_cnt;
2052 	/* TX */
2053 	u64 pkt_encrypt_cnt;
2054 	u64 pkt_protected_cnt;
2055 	u64 rsvd[4];
2056 };
2057 
2058 struct mcs_sc_stats {
2059 	struct mbox_msghdr hdr;
2060 	/* RX */
2061 	u64 hit_cnt;
2062 	u64 pkt_invalid_cnt;
2063 	u64 pkt_late_cnt;
2064 	u64 pkt_notvalid_cnt;
2065 	u64 pkt_unchecked_cnt;
2066 	u64 pkt_delay_cnt;	/* CNF10K-B */
2067 	u64 pkt_ok_cnt;		/* CNF10K-B */
2068 	u64 octet_decrypt_cnt;	/* CN10K-B */
2069 	u64 octet_validate_cnt;	/* CN10K-B */
2070 	/* TX */
2071 	u64 pkt_encrypt_cnt;
2072 	u64 pkt_protected_cnt;
2073 	u64 octet_encrypt_cnt;		/* CN10K-B */
2074 	u64 octet_protected_cnt;	/* CN10K-B */
2075 	u64 rsvd[4];
2076 };
2077 
2078 struct mcs_clear_stats {
2079 	struct mbox_msghdr hdr;
2080 #define MCS_FLOWID_STATS	0
2081 #define MCS_SECY_STATS		1
2082 #define MCS_SC_STATS		2
2083 #define MCS_SA_STATS		3
2084 #define MCS_PORT_STATS		4
2085 	u8 type;	/* FLOWID, SECY, SC, SA, PORT */
2086 	u8 id;		/* type = PORT, If id = FF(invalid) port no is derived from pcifunc */
2087 	u8 mcs_id;
2088 	u8 dir;
2089 	u8 all;		/* All resources stats mapped to PF are cleared */
2090 };
2091 
2092 struct mcs_intr_cfg {
2093 	struct mbox_msghdr hdr;
2094 #define MCS_CPM_RX_SECTAG_V_EQ1_INT		BIT_ULL(0)
2095 #define MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT	BIT_ULL(1)
2096 #define MCS_CPM_RX_SECTAG_SL_GTE48_INT		BIT_ULL(2)
2097 #define MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT	BIT_ULL(3)
2098 #define MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT	BIT_ULL(4)
2099 #define MCS_CPM_RX_PACKET_XPN_EQ0_INT		BIT_ULL(5)
2100 #define MCS_CPM_RX_PN_THRESH_REACHED_INT	BIT_ULL(6)
2101 #define MCS_CPM_TX_PACKET_XPN_EQ0_INT		BIT_ULL(7)
2102 #define MCS_CPM_TX_PN_THRESH_REACHED_INT	BIT_ULL(8)
2103 #define MCS_CPM_TX_SA_NOT_VALID_INT		BIT_ULL(9)
2104 #define MCS_BBE_RX_DFIFO_OVERFLOW_INT		BIT_ULL(10)
2105 #define MCS_BBE_RX_PLFIFO_OVERFLOW_INT		BIT_ULL(11)
2106 #define MCS_BBE_TX_DFIFO_OVERFLOW_INT		BIT_ULL(12)
2107 #define MCS_BBE_TX_PLFIFO_OVERFLOW_INT		BIT_ULL(13)
2108 #define MCS_PAB_RX_CHAN_OVERFLOW_INT		BIT_ULL(14)
2109 #define MCS_PAB_TX_CHAN_OVERFLOW_INT		BIT_ULL(15)
2110 	u64 intr_mask;		/* Interrupt enable mask */
2111 	u8 mcs_id;
2112 	u8 lmac_id;
2113 	u64 rsvd;
2114 };
2115 
2116 struct mcs_intr_info {
2117 	struct mbox_msghdr hdr;
2118 	u64 intr_mask;
2119 	int sa_id;
2120 	u8 mcs_id;
2121 	u8 lmac_id;
2122 	u64 rsvd;
2123 };
2124 
2125 #endif /* MBOX_H */
2126