1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * pci_root.c - ACPI PCI Root Bridge Driver ($Revision: 40 $)
4 *
5 * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
6 * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
7 */
8
9 #define pr_fmt(fmt) "ACPI: " fmt
10
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/types.h>
15 #include <linux/mutex.h>
16 #include <linux/pm.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/pci.h>
19 #include <linux/pci-acpi.h>
20 #include <linux/dmar.h>
21 #include <linux/acpi.h>
22 #include <linux/slab.h>
23 #include <linux/dmi.h>
24 #include <linux/platform_data/x86/apple.h>
25 #include "internal.h"
26
27 #define ACPI_PCI_ROOT_CLASS "pci_bridge"
28 #define ACPI_PCI_ROOT_DEVICE_NAME "PCI Root Bridge"
29 static int acpi_pci_root_add(struct acpi_device *device,
30 const struct acpi_device_id *not_used);
31 static void acpi_pci_root_remove(struct acpi_device *device);
32
acpi_pci_root_scan_dependent(struct acpi_device * adev)33 static int acpi_pci_root_scan_dependent(struct acpi_device *adev)
34 {
35 acpiphp_check_host_bridge(adev);
36 return 0;
37 }
38
39 #define ACPI_PCIE_REQ_SUPPORT (OSC_PCI_EXT_CONFIG_SUPPORT \
40 | OSC_PCI_ASPM_SUPPORT \
41 | OSC_PCI_CLOCK_PM_SUPPORT \
42 | OSC_PCI_MSI_SUPPORT)
43
44 static const struct acpi_device_id root_device_ids[] = {
45 {"PNP0A03", 0},
46 {"", 0},
47 };
48
49 static struct acpi_scan_handler pci_root_handler = {
50 .ids = root_device_ids,
51 .attach = acpi_pci_root_add,
52 .detach = acpi_pci_root_remove,
53 .hotplug = {
54 .enabled = true,
55 .scan_dependent = acpi_pci_root_scan_dependent,
56 },
57 };
58
59 /**
60 * acpi_is_root_bridge - determine whether an ACPI CA node is a PCI root bridge
61 * @handle: the ACPI CA node in question.
62 *
63 * Note: we could make this API take a struct acpi_device * instead, but
64 * for now, it's more convenient to operate on an acpi_handle.
65 */
acpi_is_root_bridge(acpi_handle handle)66 int acpi_is_root_bridge(acpi_handle handle)
67 {
68 struct acpi_device *device = acpi_fetch_acpi_dev(handle);
69 int ret;
70
71 if (!device)
72 return 0;
73
74 ret = acpi_match_device_ids(device, root_device_ids);
75 if (ret)
76 return 0;
77 else
78 return 1;
79 }
80 EXPORT_SYMBOL_GPL(acpi_is_root_bridge);
81
82 static acpi_status
get_root_bridge_busnr_callback(struct acpi_resource * resource,void * data)83 get_root_bridge_busnr_callback(struct acpi_resource *resource, void *data)
84 {
85 struct resource *res = data;
86 struct acpi_resource_address64 address;
87 acpi_status status;
88
89 status = acpi_resource_to_address64(resource, &address);
90 if (ACPI_FAILURE(status))
91 return AE_OK;
92
93 if ((address.address.address_length > 0) &&
94 (address.resource_type == ACPI_BUS_NUMBER_RANGE)) {
95 res->start = address.address.minimum;
96 res->end = address.address.minimum + address.address.address_length - 1;
97 }
98
99 return AE_OK;
100 }
101
try_get_root_bridge_busnr(acpi_handle handle,struct resource * res)102 static acpi_status try_get_root_bridge_busnr(acpi_handle handle,
103 struct resource *res)
104 {
105 acpi_status status;
106
107 res->start = -1;
108 status =
109 acpi_walk_resources(handle, METHOD_NAME__CRS,
110 get_root_bridge_busnr_callback, res);
111 if (ACPI_FAILURE(status))
112 return status;
113 if (res->start == -1)
114 return AE_ERROR;
115 return AE_OK;
116 }
117
118 struct pci_osc_bit_struct {
119 u32 bit;
120 char *desc;
121 };
122
123 static struct pci_osc_bit_struct pci_osc_support_bit[] = {
124 { OSC_PCI_EXT_CONFIG_SUPPORT, "ExtendedConfig" },
125 { OSC_PCI_ASPM_SUPPORT, "ASPM" },
126 { OSC_PCI_CLOCK_PM_SUPPORT, "ClockPM" },
127 { OSC_PCI_SEGMENT_GROUPS_SUPPORT, "Segments" },
128 { OSC_PCI_MSI_SUPPORT, "MSI" },
129 { OSC_PCI_EDR_SUPPORT, "EDR" },
130 { OSC_PCI_HPX_TYPE_3_SUPPORT, "HPX-Type3" },
131 };
132
133 static struct pci_osc_bit_struct pci_osc_control_bit[] = {
134 { OSC_PCI_EXPRESS_NATIVE_HP_CONTROL, "PCIeHotplug" },
135 { OSC_PCI_SHPC_NATIVE_HP_CONTROL, "SHPCHotplug" },
136 { OSC_PCI_EXPRESS_PME_CONTROL, "PME" },
137 { OSC_PCI_EXPRESS_AER_CONTROL, "AER" },
138 { OSC_PCI_EXPRESS_CAPABILITY_CONTROL, "PCIeCapability" },
139 { OSC_PCI_EXPRESS_LTR_CONTROL, "LTR" },
140 { OSC_PCI_EXPRESS_DPC_CONTROL, "DPC" },
141 };
142
143 static struct pci_osc_bit_struct cxl_osc_support_bit[] = {
144 { OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT, "CXL11PortRegAccess" },
145 { OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT, "CXL20PortDevRegAccess" },
146 { OSC_CXL_PROTOCOL_ERR_REPORTING_SUPPORT, "CXLProtocolErrorReporting" },
147 { OSC_CXL_NATIVE_HP_SUPPORT, "CXLNativeHotPlug" },
148 };
149
150 static struct pci_osc_bit_struct cxl_osc_control_bit[] = {
151 { OSC_CXL_ERROR_REPORTING_CONTROL, "CXLMemErrorReporting" },
152 };
153
decode_osc_bits(struct acpi_pci_root * root,char * msg,u32 word,struct pci_osc_bit_struct * table,int size)154 static void decode_osc_bits(struct acpi_pci_root *root, char *msg, u32 word,
155 struct pci_osc_bit_struct *table, int size)
156 {
157 char buf[80];
158 int i, len = 0;
159 struct pci_osc_bit_struct *entry;
160
161 buf[0] = '\0';
162 for (i = 0, entry = table; i < size; i++, entry++)
163 if (word & entry->bit)
164 len += scnprintf(buf + len, sizeof(buf) - len, "%s%s",
165 len ? " " : "", entry->desc);
166
167 dev_info(&root->device->dev, "_OSC: %s [%s]\n", msg, buf);
168 }
169
decode_osc_support(struct acpi_pci_root * root,char * msg,u32 word)170 static void decode_osc_support(struct acpi_pci_root *root, char *msg, u32 word)
171 {
172 decode_osc_bits(root, msg, word, pci_osc_support_bit,
173 ARRAY_SIZE(pci_osc_support_bit));
174 }
175
decode_osc_control(struct acpi_pci_root * root,char * msg,u32 word)176 static void decode_osc_control(struct acpi_pci_root *root, char *msg, u32 word)
177 {
178 decode_osc_bits(root, msg, word, pci_osc_control_bit,
179 ARRAY_SIZE(pci_osc_control_bit));
180 }
181
decode_cxl_osc_support(struct acpi_pci_root * root,char * msg,u32 word)182 static void decode_cxl_osc_support(struct acpi_pci_root *root, char *msg, u32 word)
183 {
184 decode_osc_bits(root, msg, word, cxl_osc_support_bit,
185 ARRAY_SIZE(cxl_osc_support_bit));
186 }
187
decode_cxl_osc_control(struct acpi_pci_root * root,char * msg,u32 word)188 static void decode_cxl_osc_control(struct acpi_pci_root *root, char *msg, u32 word)
189 {
190 decode_osc_bits(root, msg, word, cxl_osc_control_bit,
191 ARRAY_SIZE(cxl_osc_control_bit));
192 }
193
is_pcie(struct acpi_pci_root * root)194 static inline bool is_pcie(struct acpi_pci_root *root)
195 {
196 return root->bridge_type == ACPI_BRIDGE_TYPE_PCIE;
197 }
198
is_cxl(struct acpi_pci_root * root)199 static inline bool is_cxl(struct acpi_pci_root *root)
200 {
201 return root->bridge_type == ACPI_BRIDGE_TYPE_CXL;
202 }
203
204 static u8 pci_osc_uuid_str[] = "33DB4D5B-1FF7-401C-9657-7441C03DD766";
205 static u8 cxl_osc_uuid_str[] = "68F2D50B-C469-4d8A-BD3D-941A103FD3FC";
206
to_uuid(struct acpi_pci_root * root)207 static char *to_uuid(struct acpi_pci_root *root)
208 {
209 if (is_cxl(root))
210 return cxl_osc_uuid_str;
211 return pci_osc_uuid_str;
212 }
213
cap_length(struct acpi_pci_root * root)214 static int cap_length(struct acpi_pci_root *root)
215 {
216 if (is_cxl(root))
217 return sizeof(u32) * OSC_CXL_CAPABILITY_DWORDS;
218 return sizeof(u32) * OSC_PCI_CAPABILITY_DWORDS;
219 }
220
acpi_pci_run_osc(struct acpi_pci_root * root,const u32 * capbuf,u32 * pci_control,u32 * cxl_control)221 static acpi_status acpi_pci_run_osc(struct acpi_pci_root *root,
222 const u32 *capbuf, u32 *pci_control,
223 u32 *cxl_control)
224 {
225 struct acpi_osc_context context = {
226 .uuid_str = to_uuid(root),
227 .rev = 1,
228 .cap.length = cap_length(root),
229 .cap.pointer = (void *)capbuf,
230 };
231 acpi_status status;
232
233 status = acpi_run_osc(root->device->handle, &context);
234 if (ACPI_SUCCESS(status)) {
235 *pci_control = acpi_osc_ctx_get_pci_control(&context);
236 if (is_cxl(root))
237 *cxl_control = acpi_osc_ctx_get_cxl_control(&context);
238 kfree(context.ret.pointer);
239 }
240 return status;
241 }
242
acpi_pci_query_osc(struct acpi_pci_root * root,u32 support,u32 * control,u32 cxl_support,u32 * cxl_control)243 static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root, u32 support,
244 u32 *control, u32 cxl_support,
245 u32 *cxl_control)
246 {
247 acpi_status status;
248 u32 pci_result, cxl_result, capbuf[OSC_CXL_CAPABILITY_DWORDS];
249
250 support |= root->osc_support_set;
251
252 capbuf[OSC_QUERY_DWORD] = OSC_QUERY_ENABLE;
253 capbuf[OSC_SUPPORT_DWORD] = support;
254 capbuf[OSC_CONTROL_DWORD] = *control | root->osc_control_set;
255
256 if (is_cxl(root)) {
257 cxl_support |= root->osc_ext_support_set;
258 capbuf[OSC_EXT_SUPPORT_DWORD] = cxl_support;
259 capbuf[OSC_EXT_CONTROL_DWORD] = *cxl_control | root->osc_ext_control_set;
260 }
261
262 retry:
263 status = acpi_pci_run_osc(root, capbuf, &pci_result, &cxl_result);
264 if (ACPI_SUCCESS(status)) {
265 root->osc_support_set = support;
266 *control = pci_result;
267 if (is_cxl(root)) {
268 root->osc_ext_support_set = cxl_support;
269 *cxl_control = cxl_result;
270 }
271 } else if (is_cxl(root)) {
272 /*
273 * CXL _OSC is optional on CXL 1.1 hosts. Fall back to PCIe _OSC
274 * upon any failure using CXL _OSC.
275 */
276 root->bridge_type = ACPI_BRIDGE_TYPE_PCIE;
277 goto retry;
278 }
279 return status;
280 }
281
acpi_pci_find_root(acpi_handle handle)282 struct acpi_pci_root *acpi_pci_find_root(acpi_handle handle)
283 {
284 struct acpi_device *device = acpi_fetch_acpi_dev(handle);
285 struct acpi_pci_root *root;
286
287 if (!device || acpi_match_device_ids(device, root_device_ids))
288 return NULL;
289
290 root = acpi_driver_data(device);
291
292 return root;
293 }
294 EXPORT_SYMBOL_GPL(acpi_pci_find_root);
295
296 struct acpi_handle_node {
297 struct list_head node;
298 acpi_handle handle;
299 };
300
301 /**
302 * acpi_get_pci_dev - convert ACPI CA handle to struct pci_dev
303 * @handle: the handle in question
304 *
305 * Given an ACPI CA handle, the desired PCI device is located in the
306 * list of PCI devices.
307 *
308 * If the device is found, its reference count is increased and this
309 * function returns a pointer to its data structure. The caller must
310 * decrement the reference count by calling pci_dev_put().
311 * If no device is found, %NULL is returned.
312 */
acpi_get_pci_dev(acpi_handle handle)313 struct pci_dev *acpi_get_pci_dev(acpi_handle handle)
314 {
315 int dev, fn;
316 unsigned long long adr;
317 acpi_status status;
318 acpi_handle phandle;
319 struct pci_bus *pbus;
320 struct pci_dev *pdev = NULL;
321 struct acpi_handle_node *node, *tmp;
322 struct acpi_pci_root *root;
323 LIST_HEAD(device_list);
324
325 /*
326 * Walk up the ACPI CA namespace until we reach a PCI root bridge.
327 */
328 phandle = handle;
329 while (!acpi_is_root_bridge(phandle)) {
330 node = kzalloc(sizeof(struct acpi_handle_node), GFP_KERNEL);
331 if (!node)
332 goto out;
333
334 INIT_LIST_HEAD(&node->node);
335 node->handle = phandle;
336 list_add(&node->node, &device_list);
337
338 status = acpi_get_parent(phandle, &phandle);
339 if (ACPI_FAILURE(status))
340 goto out;
341 }
342
343 root = acpi_pci_find_root(phandle);
344 if (!root)
345 goto out;
346
347 pbus = root->bus;
348
349 /*
350 * Now, walk back down the PCI device tree until we return to our
351 * original handle. Assumes that everything between the PCI root
352 * bridge and the device we're looking for must be a P2P bridge.
353 */
354 list_for_each_entry(node, &device_list, node) {
355 acpi_handle hnd = node->handle;
356 status = acpi_evaluate_integer(hnd, "_ADR", NULL, &adr);
357 if (ACPI_FAILURE(status))
358 goto out;
359 dev = (adr >> 16) & 0xffff;
360 fn = adr & 0xffff;
361
362 pdev = pci_get_slot(pbus, PCI_DEVFN(dev, fn));
363 if (!pdev || hnd == handle)
364 break;
365
366 pbus = pdev->subordinate;
367 pci_dev_put(pdev);
368
369 /*
370 * This function may be called for a non-PCI device that has a
371 * PCI parent (eg. a disk under a PCI SATA controller). In that
372 * case pdev->subordinate will be NULL for the parent.
373 */
374 if (!pbus) {
375 dev_dbg(&pdev->dev, "Not a PCI-to-PCI bridge\n");
376 pdev = NULL;
377 break;
378 }
379 }
380 out:
381 list_for_each_entry_safe(node, tmp, &device_list, node)
382 kfree(node);
383
384 return pdev;
385 }
386 EXPORT_SYMBOL_GPL(acpi_get_pci_dev);
387
388 /**
389 * acpi_pci_osc_control_set - Request control of PCI root _OSC features.
390 * @handle: ACPI handle of a PCI root bridge (or PCIe Root Complex).
391 * @mask: Mask of _OSC bits to request control of, place to store control mask.
392 * @support: _OSC supported capability.
393 * @cxl_mask: Mask of CXL _OSC control bits, place to store control mask.
394 * @cxl_support: CXL _OSC supported capability.
395 *
396 * Run _OSC query for @mask and if that is successful, compare the returned
397 * mask of control bits with @req. If all of the @req bits are set in the
398 * returned mask, run _OSC request for it.
399 *
400 * The variable at the @mask address may be modified regardless of whether or
401 * not the function returns success. On success it will contain the mask of
402 * _OSC bits the BIOS has granted control of, but its contents are meaningless
403 * on failure.
404 **/
acpi_pci_osc_control_set(acpi_handle handle,u32 * mask,u32 support,u32 * cxl_mask,u32 cxl_support)405 static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask,
406 u32 support, u32 *cxl_mask,
407 u32 cxl_support)
408 {
409 u32 req = OSC_PCI_EXPRESS_CAPABILITY_CONTROL;
410 struct acpi_pci_root *root;
411 acpi_status status;
412 u32 ctrl, cxl_ctrl = 0, capbuf[OSC_CXL_CAPABILITY_DWORDS];
413
414 if (!mask)
415 return AE_BAD_PARAMETER;
416
417 root = acpi_pci_find_root(handle);
418 if (!root)
419 return AE_NOT_EXIST;
420
421 ctrl = *mask;
422 *mask |= root->osc_control_set;
423
424 if (is_cxl(root)) {
425 cxl_ctrl = *cxl_mask;
426 *cxl_mask |= root->osc_ext_control_set;
427 }
428
429 /* Need to check the available controls bits before requesting them. */
430 do {
431 u32 pci_missing = 0, cxl_missing = 0;
432
433 status = acpi_pci_query_osc(root, support, mask, cxl_support,
434 cxl_mask);
435 if (ACPI_FAILURE(status))
436 return status;
437 if (is_cxl(root)) {
438 if (ctrl == *mask && cxl_ctrl == *cxl_mask)
439 break;
440 pci_missing = ctrl & ~(*mask);
441 cxl_missing = cxl_ctrl & ~(*cxl_mask);
442 } else {
443 if (ctrl == *mask)
444 break;
445 pci_missing = ctrl & ~(*mask);
446 }
447 if (pci_missing)
448 decode_osc_control(root, "platform does not support",
449 pci_missing);
450 if (cxl_missing)
451 decode_cxl_osc_control(root, "CXL platform does not support",
452 cxl_missing);
453 ctrl = *mask;
454 cxl_ctrl = *cxl_mask;
455 } while (*mask || *cxl_mask);
456
457 /* No need to request _OSC if the control was already granted. */
458 if ((root->osc_control_set & ctrl) == ctrl &&
459 (root->osc_ext_control_set & cxl_ctrl) == cxl_ctrl)
460 return AE_OK;
461
462 if ((ctrl & req) != req) {
463 decode_osc_control(root, "not requesting control; platform does not support",
464 req & ~(ctrl));
465 return AE_SUPPORT;
466 }
467
468 capbuf[OSC_QUERY_DWORD] = 0;
469 capbuf[OSC_SUPPORT_DWORD] = root->osc_support_set;
470 capbuf[OSC_CONTROL_DWORD] = ctrl;
471 if (is_cxl(root)) {
472 capbuf[OSC_EXT_SUPPORT_DWORD] = root->osc_ext_support_set;
473 capbuf[OSC_EXT_CONTROL_DWORD] = cxl_ctrl;
474 }
475
476 status = acpi_pci_run_osc(root, capbuf, mask, cxl_mask);
477 if (ACPI_FAILURE(status))
478 return status;
479
480 root->osc_control_set = *mask;
481 root->osc_ext_control_set = *cxl_mask;
482 return AE_OK;
483 }
484
calculate_support(void)485 static u32 calculate_support(void)
486 {
487 u32 support;
488
489 /*
490 * All supported architectures that use ACPI have support for
491 * PCI domains, so we indicate this in _OSC support capabilities.
492 */
493 support = OSC_PCI_SEGMENT_GROUPS_SUPPORT;
494 support |= OSC_PCI_HPX_TYPE_3_SUPPORT;
495 if (pci_ext_cfg_avail())
496 support |= OSC_PCI_EXT_CONFIG_SUPPORT;
497 if (pcie_aspm_support_enabled())
498 support |= OSC_PCI_ASPM_SUPPORT | OSC_PCI_CLOCK_PM_SUPPORT;
499 if (pci_msi_enabled())
500 support |= OSC_PCI_MSI_SUPPORT;
501 if (IS_ENABLED(CONFIG_PCIE_EDR))
502 support |= OSC_PCI_EDR_SUPPORT;
503
504 return support;
505 }
506
507 /*
508 * Background on hotplug support, and making it depend on only
509 * CONFIG_HOTPLUG_PCI_PCIE vs. also considering CONFIG_MEMORY_HOTPLUG:
510 *
511 * CONFIG_ACPI_HOTPLUG_MEMORY does depend on CONFIG_MEMORY_HOTPLUG, but
512 * there is no existing _OSC for memory hotplug support. The reason is that
513 * ACPI memory hotplug requires the OS to acknowledge / coordinate with
514 * memory plug events via a scan handler. On the CXL side the equivalent
515 * would be if Linux supported the Mechanical Retention Lock [1], or
516 * otherwise had some coordination for the driver of a PCI device
517 * undergoing hotplug to be consulted on whether the hotplug should
518 * proceed or not.
519 *
520 * The concern is that if Linux says no to supporting CXL hotplug then
521 * the BIOS may say no to giving the OS hotplug control of any other PCIe
522 * device. So the question here is not whether hotplug is enabled, it's
523 * whether it is handled natively by the at all OS, and if
524 * CONFIG_HOTPLUG_PCI_PCIE is enabled then the answer is "yes".
525 *
526 * Otherwise, the plan for CXL coordinated remove, since the kernel does
527 * not support blocking hotplug, is to require the memory device to be
528 * disabled before hotplug is attempted. When CONFIG_MEMORY_HOTPLUG is
529 * disabled that step will fail and the remove attempt cancelled by the
530 * user. If that is not honored and the card is removed anyway then it
531 * does not matter if CONFIG_MEMORY_HOTPLUG is enabled or not, it will
532 * cause a crash and other badness.
533 *
534 * Therefore, just say yes to CXL hotplug and require removal to
535 * be coordinated by userspace unless and until the kernel grows better
536 * mechanisms for doing "managed" removal of devices in consultation with
537 * the driver.
538 *
539 * [1]: https://lore.kernel.org/all/20201122014203.4706-1-ashok.raj@intel.com/
540 */
calculate_cxl_support(void)541 static u32 calculate_cxl_support(void)
542 {
543 u32 support;
544
545 support = OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT;
546 if (pci_aer_available())
547 support |= OSC_CXL_PROTOCOL_ERR_REPORTING_SUPPORT;
548 if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))
549 support |= OSC_CXL_NATIVE_HP_SUPPORT;
550
551 return support;
552 }
553
calculate_control(void)554 static u32 calculate_control(void)
555 {
556 u32 control;
557
558 control = OSC_PCI_EXPRESS_CAPABILITY_CONTROL
559 | OSC_PCI_EXPRESS_PME_CONTROL;
560
561 if (IS_ENABLED(CONFIG_PCIEASPM))
562 control |= OSC_PCI_EXPRESS_LTR_CONTROL;
563
564 if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))
565 control |= OSC_PCI_EXPRESS_NATIVE_HP_CONTROL;
566
567 if (IS_ENABLED(CONFIG_HOTPLUG_PCI_SHPC))
568 control |= OSC_PCI_SHPC_NATIVE_HP_CONTROL;
569
570 if (pci_aer_available())
571 control |= OSC_PCI_EXPRESS_AER_CONTROL;
572
573 /*
574 * Per the Downstream Port Containment Related Enhancements ECN to
575 * the PCI Firmware Spec, r3.2, sec 4.5.1, table 4-5,
576 * OSC_PCI_EXPRESS_DPC_CONTROL indicates the OS supports both DPC
577 * and EDR.
578 */
579 if (IS_ENABLED(CONFIG_PCIE_DPC) && IS_ENABLED(CONFIG_PCIE_EDR))
580 control |= OSC_PCI_EXPRESS_DPC_CONTROL;
581
582 return control;
583 }
584
calculate_cxl_control(void)585 static u32 calculate_cxl_control(void)
586 {
587 u32 control = 0;
588
589 if (IS_ENABLED(CONFIG_MEMORY_FAILURE))
590 control |= OSC_CXL_ERROR_REPORTING_CONTROL;
591
592 return control;
593 }
594
os_control_query_checks(struct acpi_pci_root * root,u32 support)595 static bool os_control_query_checks(struct acpi_pci_root *root, u32 support)
596 {
597 struct acpi_device *device = root->device;
598
599 if (pcie_ports_disabled) {
600 dev_info(&device->dev, "PCIe port services disabled; not requesting _OSC control\n");
601 return false;
602 }
603
604 if ((support & ACPI_PCIE_REQ_SUPPORT) != ACPI_PCIE_REQ_SUPPORT) {
605 decode_osc_support(root, "not requesting OS control; OS requires",
606 ACPI_PCIE_REQ_SUPPORT);
607 return false;
608 }
609
610 return true;
611 }
612
negotiate_os_control(struct acpi_pci_root * root,int * no_aspm)613 static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm)
614 {
615 u32 support, control = 0, requested = 0;
616 u32 cxl_support = 0, cxl_control = 0, cxl_requested = 0;
617 acpi_status status;
618 struct acpi_device *device = root->device;
619 acpi_handle handle = device->handle;
620
621 /*
622 * Apple always return failure on _OSC calls when _OSI("Darwin") has
623 * been called successfully. We know the feature set supported by the
624 * platform, so avoid calling _OSC at all
625 */
626 if (x86_apple_machine) {
627 root->osc_control_set = ~OSC_PCI_EXPRESS_PME_CONTROL;
628 decode_osc_control(root, "OS assumes control of",
629 root->osc_control_set);
630 return;
631 }
632
633 support = calculate_support();
634
635 decode_osc_support(root, "OS supports", support);
636
637 if (os_control_query_checks(root, support))
638 requested = control = calculate_control();
639
640 if (is_cxl(root)) {
641 cxl_support = calculate_cxl_support();
642 decode_cxl_osc_support(root, "OS supports", cxl_support);
643 cxl_requested = cxl_control = calculate_cxl_control();
644 }
645
646 status = acpi_pci_osc_control_set(handle, &control, support,
647 &cxl_control, cxl_support);
648 if (ACPI_SUCCESS(status)) {
649 if (control)
650 decode_osc_control(root, "OS now controls", control);
651 if (cxl_control)
652 decode_cxl_osc_control(root, "OS now controls",
653 cxl_control);
654
655 if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) {
656 /*
657 * We have ASPM control, but the FADT indicates that
658 * it's unsupported. Leave existing configuration
659 * intact and prevent the OS from touching it.
660 */
661 dev_info(&device->dev, "FADT indicates ASPM is unsupported, using BIOS configuration\n");
662 *no_aspm = 1;
663 }
664 } else {
665 /*
666 * We want to disable ASPM here, but aspm_disabled
667 * needs to remain in its state from boot so that we
668 * properly handle PCIe 1.1 devices. So we set this
669 * flag here, to defer the action until after the ACPI
670 * root scan.
671 */
672 *no_aspm = 1;
673
674 /* _OSC is optional for PCI host bridges */
675 if (status == AE_NOT_FOUND && !is_pcie(root))
676 return;
677
678 if (control) {
679 decode_osc_control(root, "OS requested", requested);
680 decode_osc_control(root, "platform willing to grant", control);
681 }
682 if (cxl_control) {
683 decode_cxl_osc_control(root, "OS requested", cxl_requested);
684 decode_cxl_osc_control(root, "platform willing to grant",
685 cxl_control);
686 }
687
688 dev_info(&device->dev, "_OSC: platform retains control of PCIe features (%s)\n",
689 acpi_format_exception(status));
690 }
691 }
692
acpi_pci_root_add(struct acpi_device * device,const struct acpi_device_id * not_used)693 static int acpi_pci_root_add(struct acpi_device *device,
694 const struct acpi_device_id *not_used)
695 {
696 unsigned long long segment, bus;
697 acpi_status status;
698 int result;
699 struct acpi_pci_root *root;
700 acpi_handle handle = device->handle;
701 int no_aspm = 0;
702 bool hotadd = system_state == SYSTEM_RUNNING;
703 const char *acpi_hid;
704
705 root = kzalloc(sizeof(struct acpi_pci_root), GFP_KERNEL);
706 if (!root)
707 return -ENOMEM;
708
709 segment = 0;
710 status = acpi_evaluate_integer(handle, METHOD_NAME__SEG, NULL,
711 &segment);
712 if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) {
713 dev_err(&device->dev, "can't evaluate _SEG\n");
714 result = -ENODEV;
715 goto end;
716 }
717
718 /* Check _CRS first, then _BBN. If no _BBN, default to zero. */
719 root->secondary.flags = IORESOURCE_BUS;
720 status = try_get_root_bridge_busnr(handle, &root->secondary);
721 if (ACPI_FAILURE(status)) {
722 /*
723 * We need both the start and end of the downstream bus range
724 * to interpret _CBA (MMCONFIG base address), so it really is
725 * supposed to be in _CRS. If we don't find it there, all we
726 * can do is assume [_BBN-0xFF] or [0-0xFF].
727 */
728 root->secondary.end = 0xFF;
729 dev_warn(&device->dev,
730 FW_BUG "no secondary bus range in _CRS\n");
731 status = acpi_evaluate_integer(handle, METHOD_NAME__BBN,
732 NULL, &bus);
733 if (ACPI_SUCCESS(status))
734 root->secondary.start = bus;
735 else if (status == AE_NOT_FOUND)
736 root->secondary.start = 0;
737 else {
738 dev_err(&device->dev, "can't evaluate _BBN\n");
739 result = -ENODEV;
740 goto end;
741 }
742 }
743
744 root->device = device;
745 root->segment = segment & 0xFFFF;
746 strcpy(acpi_device_name(device), ACPI_PCI_ROOT_DEVICE_NAME);
747 strcpy(acpi_device_class(device), ACPI_PCI_ROOT_CLASS);
748 device->driver_data = root;
749
750 if (hotadd && dmar_device_add(handle)) {
751 result = -ENXIO;
752 goto end;
753 }
754
755 pr_info("%s [%s] (domain %04x %pR)\n",
756 acpi_device_name(device), acpi_device_bid(device),
757 root->segment, &root->secondary);
758
759 root->mcfg_addr = acpi_pci_root_get_mcfg_addr(handle);
760
761 acpi_hid = acpi_device_hid(root->device);
762 if (strcmp(acpi_hid, "PNP0A08") == 0)
763 root->bridge_type = ACPI_BRIDGE_TYPE_PCIE;
764 else if (strcmp(acpi_hid, "ACPI0016") == 0)
765 root->bridge_type = ACPI_BRIDGE_TYPE_CXL;
766 else
767 dev_dbg(&device->dev, "Assuming non-PCIe host bridge\n");
768
769 negotiate_os_control(root, &no_aspm);
770
771 /*
772 * TBD: Need PCI interface for enumeration/configuration of roots.
773 */
774
775 /*
776 * Scan the Root Bridge
777 * --------------------
778 * Must do this prior to any attempt to bind the root device, as the
779 * PCI namespace does not get created until this call is made (and
780 * thus the root bridge's pci_dev does not exist).
781 */
782 root->bus = pci_acpi_scan_root(root);
783 if (!root->bus) {
784 dev_err(&device->dev,
785 "Bus %04x:%02x not present in PCI namespace\n",
786 root->segment, (unsigned int)root->secondary.start);
787 device->driver_data = NULL;
788 result = -ENODEV;
789 goto remove_dmar;
790 }
791
792 if (no_aspm)
793 pcie_no_aspm();
794
795 pci_acpi_add_bus_pm_notifier(device);
796 device_set_wakeup_capable(root->bus->bridge, device->wakeup.flags.valid);
797
798 if (hotadd) {
799 pcibios_resource_survey_bus(root->bus);
800 pci_assign_unassigned_root_bus_resources(root->bus);
801 /*
802 * This is only called for the hotadd case. For the boot-time
803 * case, we need to wait until after PCI initialization in
804 * order to deal with IOAPICs mapped in on a PCI BAR.
805 *
806 * This is currently x86-specific, because acpi_ioapic_add()
807 * is an empty function without CONFIG_ACPI_HOTPLUG_IOAPIC.
808 * And CONFIG_ACPI_HOTPLUG_IOAPIC depends on CONFIG_X86_IO_APIC
809 * (see drivers/acpi/Kconfig).
810 */
811 acpi_ioapic_add(root->device->handle);
812 }
813
814 pci_lock_rescan_remove();
815 pci_bus_add_devices(root->bus);
816 pci_unlock_rescan_remove();
817 return 1;
818
819 remove_dmar:
820 if (hotadd)
821 dmar_device_remove(handle);
822 end:
823 kfree(root);
824 return result;
825 }
826
acpi_pci_root_remove(struct acpi_device * device)827 static void acpi_pci_root_remove(struct acpi_device *device)
828 {
829 struct acpi_pci_root *root = acpi_driver_data(device);
830
831 pci_lock_rescan_remove();
832
833 pci_stop_root_bus(root->bus);
834
835 pci_ioapic_remove(root);
836 device_set_wakeup_capable(root->bus->bridge, false);
837 pci_acpi_remove_bus_pm_notifier(device);
838
839 pci_remove_root_bus(root->bus);
840 WARN_ON(acpi_ioapic_remove(root));
841
842 dmar_device_remove(device->handle);
843
844 pci_unlock_rescan_remove();
845
846 kfree(root);
847 }
848
849 /*
850 * Following code to support acpi_pci_root_create() is copied from
851 * arch/x86/pci/acpi.c and modified so it could be reused by x86, IA64
852 * and ARM64.
853 */
acpi_pci_root_validate_resources(struct device * dev,struct list_head * resources,unsigned long type)854 static void acpi_pci_root_validate_resources(struct device *dev,
855 struct list_head *resources,
856 unsigned long type)
857 {
858 LIST_HEAD(list);
859 struct resource *res1, *res2, *root = NULL;
860 struct resource_entry *tmp, *entry, *entry2;
861
862 BUG_ON((type & (IORESOURCE_MEM | IORESOURCE_IO)) == 0);
863 root = (type & IORESOURCE_MEM) ? &iomem_resource : &ioport_resource;
864
865 list_splice_init(resources, &list);
866 resource_list_for_each_entry_safe(entry, tmp, &list) {
867 bool free = false;
868 resource_size_t end;
869
870 res1 = entry->res;
871 if (!(res1->flags & type))
872 goto next;
873
874 /* Exclude non-addressable range or non-addressable portion */
875 end = min(res1->end, root->end);
876 if (end <= res1->start) {
877 dev_info(dev, "host bridge window %pR (ignored, not CPU addressable)\n",
878 res1);
879 free = true;
880 goto next;
881 } else if (res1->end != end) {
882 dev_info(dev, "host bridge window %pR ([%#llx-%#llx] ignored, not CPU addressable)\n",
883 res1, (unsigned long long)end + 1,
884 (unsigned long long)res1->end);
885 res1->end = end;
886 }
887
888 resource_list_for_each_entry(entry2, resources) {
889 res2 = entry2->res;
890 if (!(res2->flags & type))
891 continue;
892
893 /*
894 * I don't like throwing away windows because then
895 * our resources no longer match the ACPI _CRS, but
896 * the kernel resource tree doesn't allow overlaps.
897 */
898 if (resource_union(res1, res2, res2)) {
899 dev_info(dev, "host bridge window expanded to %pR; %pR ignored\n",
900 res2, res1);
901 free = true;
902 goto next;
903 }
904 }
905
906 next:
907 resource_list_del(entry);
908 if (free)
909 resource_list_free_entry(entry);
910 else
911 resource_list_add_tail(entry, resources);
912 }
913 }
914
acpi_pci_root_remap_iospace(struct fwnode_handle * fwnode,struct resource_entry * entry)915 static void acpi_pci_root_remap_iospace(struct fwnode_handle *fwnode,
916 struct resource_entry *entry)
917 {
918 #ifdef PCI_IOBASE
919 struct resource *res = entry->res;
920 resource_size_t cpu_addr = res->start;
921 resource_size_t pci_addr = cpu_addr - entry->offset;
922 resource_size_t length = resource_size(res);
923 unsigned long port;
924
925 if (pci_register_io_range(fwnode, cpu_addr, length))
926 goto err;
927
928 port = pci_address_to_pio(cpu_addr);
929 if (port == (unsigned long)-1)
930 goto err;
931
932 res->start = port;
933 res->end = port + length - 1;
934 entry->offset = port - pci_addr;
935
936 if (pci_remap_iospace(res, cpu_addr) < 0)
937 goto err;
938
939 pr_info("Remapped I/O %pa to %pR\n", &cpu_addr, res);
940 return;
941 err:
942 res->flags |= IORESOURCE_DISABLED;
943 #endif
944 }
945
acpi_pci_probe_root_resources(struct acpi_pci_root_info * info)946 int acpi_pci_probe_root_resources(struct acpi_pci_root_info *info)
947 {
948 int ret;
949 struct list_head *list = &info->resources;
950 struct acpi_device *device = info->bridge;
951 struct resource_entry *entry, *tmp;
952 unsigned long flags;
953
954 flags = IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT;
955 ret = acpi_dev_get_resources(device, list,
956 acpi_dev_filter_resource_type_cb,
957 (void *)flags);
958 if (ret < 0)
959 dev_warn(&device->dev,
960 "failed to parse _CRS method, error code %d\n", ret);
961 else if (ret == 0)
962 dev_dbg(&device->dev,
963 "no IO and memory resources present in _CRS\n");
964 else {
965 resource_list_for_each_entry_safe(entry, tmp, list) {
966 if (entry->res->flags & IORESOURCE_IO)
967 acpi_pci_root_remap_iospace(&device->fwnode,
968 entry);
969
970 if (entry->res->flags & IORESOURCE_DISABLED)
971 resource_list_destroy_entry(entry);
972 else
973 entry->res->name = info->name;
974 }
975 acpi_pci_root_validate_resources(&device->dev, list,
976 IORESOURCE_MEM);
977 acpi_pci_root_validate_resources(&device->dev, list,
978 IORESOURCE_IO);
979 }
980
981 return ret;
982 }
983
pci_acpi_root_add_resources(struct acpi_pci_root_info * info)984 static void pci_acpi_root_add_resources(struct acpi_pci_root_info *info)
985 {
986 struct resource_entry *entry, *tmp;
987 struct resource *res, *conflict, *root = NULL;
988
989 resource_list_for_each_entry_safe(entry, tmp, &info->resources) {
990 res = entry->res;
991 if (res->flags & IORESOURCE_MEM)
992 root = &iomem_resource;
993 else if (res->flags & IORESOURCE_IO)
994 root = &ioport_resource;
995 else
996 continue;
997
998 /*
999 * Some legacy x86 host bridge drivers use iomem_resource and
1000 * ioport_resource as default resource pool, skip it.
1001 */
1002 if (res == root)
1003 continue;
1004
1005 conflict = insert_resource_conflict(root, res);
1006 if (conflict) {
1007 dev_info(&info->bridge->dev,
1008 "ignoring host bridge window %pR (conflicts with %s %pR)\n",
1009 res, conflict->name, conflict);
1010 resource_list_destroy_entry(entry);
1011 }
1012 }
1013 }
1014
__acpi_pci_root_release_info(struct acpi_pci_root_info * info)1015 static void __acpi_pci_root_release_info(struct acpi_pci_root_info *info)
1016 {
1017 struct resource *res;
1018 struct resource_entry *entry, *tmp;
1019
1020 if (!info)
1021 return;
1022
1023 resource_list_for_each_entry_safe(entry, tmp, &info->resources) {
1024 res = entry->res;
1025 if (res->parent &&
1026 (res->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
1027 release_resource(res);
1028 resource_list_destroy_entry(entry);
1029 }
1030
1031 info->ops->release_info(info);
1032 }
1033
acpi_pci_root_release_info(struct pci_host_bridge * bridge)1034 static void acpi_pci_root_release_info(struct pci_host_bridge *bridge)
1035 {
1036 struct resource *res;
1037 struct resource_entry *entry;
1038
1039 resource_list_for_each_entry(entry, &bridge->windows) {
1040 res = entry->res;
1041 if (res->flags & IORESOURCE_IO)
1042 pci_unmap_iospace(res);
1043 if (res->parent &&
1044 (res->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
1045 release_resource(res);
1046 }
1047 __acpi_pci_root_release_info(bridge->release_data);
1048 }
1049
acpi_pci_root_create(struct acpi_pci_root * root,struct acpi_pci_root_ops * ops,struct acpi_pci_root_info * info,void * sysdata)1050 struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root,
1051 struct acpi_pci_root_ops *ops,
1052 struct acpi_pci_root_info *info,
1053 void *sysdata)
1054 {
1055 int ret, busnum = root->secondary.start;
1056 struct acpi_device *device = root->device;
1057 int node = acpi_get_node(device->handle);
1058 struct pci_bus *bus;
1059 struct pci_host_bridge *host_bridge;
1060 union acpi_object *obj;
1061
1062 info->root = root;
1063 info->bridge = device;
1064 info->ops = ops;
1065 INIT_LIST_HEAD(&info->resources);
1066 snprintf(info->name, sizeof(info->name), "PCI Bus %04x:%02x",
1067 root->segment, busnum);
1068
1069 if (ops->init_info && ops->init_info(info))
1070 goto out_release_info;
1071 if (ops->prepare_resources)
1072 ret = ops->prepare_resources(info);
1073 else
1074 ret = acpi_pci_probe_root_resources(info);
1075 if (ret < 0)
1076 goto out_release_info;
1077
1078 pci_acpi_root_add_resources(info);
1079 pci_add_resource(&info->resources, &root->secondary);
1080 bus = pci_create_root_bus(NULL, busnum, ops->pci_ops,
1081 sysdata, &info->resources);
1082 if (!bus)
1083 goto out_release_info;
1084
1085 host_bridge = to_pci_host_bridge(bus->bridge);
1086 if (!(root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL))
1087 host_bridge->native_pcie_hotplug = 0;
1088 if (!(root->osc_control_set & OSC_PCI_SHPC_NATIVE_HP_CONTROL))
1089 host_bridge->native_shpc_hotplug = 0;
1090 if (!(root->osc_control_set & OSC_PCI_EXPRESS_AER_CONTROL))
1091 host_bridge->native_aer = 0;
1092 if (!(root->osc_control_set & OSC_PCI_EXPRESS_PME_CONTROL))
1093 host_bridge->native_pme = 0;
1094 if (!(root->osc_control_set & OSC_PCI_EXPRESS_LTR_CONTROL))
1095 host_bridge->native_ltr = 0;
1096 if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL))
1097 host_bridge->native_dpc = 0;
1098
1099 /*
1100 * Evaluate the "PCI Boot Configuration" _DSM Function. If it
1101 * exists and returns 0, we must preserve any PCI resource
1102 * assignments made by firmware for this host bridge.
1103 */
1104 obj = acpi_evaluate_dsm(ACPI_HANDLE(bus->bridge), &pci_acpi_dsm_guid, 1,
1105 DSM_PCI_PRESERVE_BOOT_CONFIG, NULL);
1106 if (obj && obj->type == ACPI_TYPE_INTEGER && obj->integer.value == 0)
1107 host_bridge->preserve_config = 1;
1108 ACPI_FREE(obj);
1109
1110 acpi_dev_power_up_children_with_adr(device);
1111
1112 pci_scan_child_bus(bus);
1113 pci_set_host_bridge_release(host_bridge, acpi_pci_root_release_info,
1114 info);
1115 if (node != NUMA_NO_NODE)
1116 dev_printk(KERN_DEBUG, &bus->dev, "on NUMA node %d\n", node);
1117 return bus;
1118
1119 out_release_info:
1120 __acpi_pci_root_release_info(info);
1121 return NULL;
1122 }
1123
acpi_pci_root_init(void)1124 void __init acpi_pci_root_init(void)
1125 {
1126 if (acpi_pci_disabled)
1127 return;
1128
1129 pci_acpi_crs_quirks();
1130 acpi_scan_add_handler_with_hotplug(&pci_root_handler, "pci_root");
1131 }
1132