1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef DEBUG_H
18 #define DEBUG_H
19
20 #include "hw.h"
21 #include "rc.h"
22 #include "dfs_debug.h"
23
24 struct ath_txq;
25 struct ath_buf;
26
27 #ifdef CONFIG_ATH9K_DEBUGFS
28 #define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
29 #define RESET_STAT_INC(sc, type) sc->debug.stats.reset[type]++
30 #else
31 #define TX_STAT_INC(q, c) do { } while (0)
32 #define RESET_STAT_INC(sc, type) do { } while (0)
33 #endif
34
35 #ifdef CONFIG_ATH9K_DEBUGFS
36
37 /**
38 * struct ath_interrupt_stats - Contains statistics about interrupts
39 * @total: Total no. of interrupts generated so far
40 * @rxok: RX with no errors
41 * @rxlp: RX with low priority RX
42 * @rxhp: RX with high priority, uapsd only
43 * @rxeol: RX with no more RXDESC available
44 * @rxorn: RX FIFO overrun
45 * @txok: TX completed at the requested rate
46 * @txurn: TX FIFO underrun
47 * @mib: MIB regs reaching its threshold
48 * @rxphyerr: RX with phy errors
49 * @rx_keycache_miss: RX with key cache misses
50 * @swba: Software Beacon Alert
51 * @bmiss: Beacon Miss
52 * @bnr: Beacon Not Ready
53 * @cst: Carrier Sense TImeout
54 * @gtt: Global TX Timeout
55 * @tim: RX beacon TIM occurrence
56 * @cabend: RX End of CAB traffic
57 * @dtimsync: DTIM sync lossage
58 * @dtim: RX Beacon with DTIM
59 * @bb_watchdog: Baseband watchdog
60 * @tsfoor: TSF out of range, indicates that the corrected TSF received
61 * from a beacon differs from the PCU's internal TSF by more than a
62 * (programmable) threshold
63 */
64 struct ath_interrupt_stats {
65 u32 total;
66 u32 rxok;
67 u32 rxlp;
68 u32 rxhp;
69 u32 rxeol;
70 u32 rxorn;
71 u32 txok;
72 u32 txeol;
73 u32 txurn;
74 u32 mib;
75 u32 rxphyerr;
76 u32 rx_keycache_miss;
77 u32 swba;
78 u32 bmiss;
79 u32 bnr;
80 u32 cst;
81 u32 gtt;
82 u32 tim;
83 u32 cabend;
84 u32 dtimsync;
85 u32 dtim;
86 u32 bb_watchdog;
87 u32 tsfoor;
88 };
89
90 /**
91 * struct ath_tx_stats - Statistics about TX
92 * @tx_pkts_all: No. of total frames transmitted, including ones that
93 may have had errors.
94 * @tx_bytes_all: No. of total bytes transmitted, including ones that
95 may have had errors.
96 * @queued: Total MPDUs (non-aggr) queued
97 * @completed: Total MPDUs (non-aggr) completed
98 * @a_aggr: Total no. of aggregates queued
99 * @a_queued_hw: Total AMPDUs queued to hardware
100 * @a_queued_sw: Total AMPDUs queued to software queues
101 * @a_completed: Total AMPDUs completed
102 * @a_retries: No. of AMPDUs retried (SW)
103 * @a_xretries: No. of AMPDUs dropped due to xretries
104 * @fifo_underrun: FIFO underrun occurrences
105 Valid only for:
106 - non-aggregate condition.
107 - first packet of aggregate.
108 * @xtxop: No. of frames filtered because of TXOP limit
109 * @timer_exp: Transmit timer expiry
110 * @desc_cfg_err: Descriptor configuration errors
111 * @data_urn: TX data underrun errors
112 * @delim_urn: TX delimiter underrun errors
113 * @puttxbuf: Number of times hardware was given txbuf to write.
114 * @txstart: Number of times hardware was told to start tx.
115 * @txprocdesc: Number of times tx descriptor was processed
116 */
117 struct ath_tx_stats {
118 u32 tx_pkts_all;
119 u32 tx_bytes_all;
120 u32 queued;
121 u32 completed;
122 u32 xretries;
123 u32 a_aggr;
124 u32 a_queued_hw;
125 u32 a_queued_sw;
126 u32 a_completed;
127 u32 a_retries;
128 u32 a_xretries;
129 u32 fifo_underrun;
130 u32 xtxop;
131 u32 timer_exp;
132 u32 desc_cfg_err;
133 u32 data_underrun;
134 u32 delim_underrun;
135 u32 puttxbuf;
136 u32 txstart;
137 u32 txprocdesc;
138 };
139
140 /**
141 * struct ath_rx_stats - RX Statistics
142 * @rx_pkts_all: No. of total frames received, including ones that
143 may have had errors.
144 * @rx_bytes_all: No. of total bytes received, including ones that
145 may have had errors.
146 * @crc_err: No. of frames with incorrect CRC value
147 * @decrypt_crc_err: No. of frames whose CRC check failed after
148 decryption process completed
149 * @phy_err: No. of frames whose reception failed because the PHY
150 encountered an error
151 * @mic_err: No. of frames with incorrect TKIP MIC verification failure
152 * @pre_delim_crc_err: Pre-Frame delimiter CRC error detections
153 * @post_delim_crc_err: Post-Frame delimiter CRC error detections
154 * @decrypt_busy_err: Decryption interruptions counter
155 * @phy_err_stats: Individual PHY error statistics
156 */
157 struct ath_rx_stats {
158 u32 rx_pkts_all;
159 u32 rx_bytes_all;
160 u32 crc_err;
161 u32 decrypt_crc_err;
162 u32 phy_err;
163 u32 mic_err;
164 u32 pre_delim_crc_err;
165 u32 post_delim_crc_err;
166 u32 decrypt_busy_err;
167 u32 phy_err_stats[ATH9K_PHYERR_MAX];
168 };
169
170 enum ath_reset_type {
171 RESET_TYPE_BB_HANG,
172 RESET_TYPE_BB_WATCHDOG,
173 RESET_TYPE_FATAL_INT,
174 RESET_TYPE_TX_ERROR,
175 RESET_TYPE_TX_HANG,
176 RESET_TYPE_PLL_HANG,
177 __RESET_TYPE_MAX
178 };
179
180 struct ath_stats {
181 struct ath_interrupt_stats istats;
182 struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
183 struct ath_rx_stats rxstats;
184 struct ath_dfs_stats dfs_stats;
185 u32 reset[__RESET_TYPE_MAX];
186 };
187
188 #define ATH_DBG_MAX_SAMPLES 10
189 struct ath_dbg_bb_mac_samp {
190 u32 dma_dbg_reg_vals[ATH9K_NUM_DMA_DEBUG_REGS];
191 u32 pcu_obs, pcu_cr, noise;
192 struct {
193 u64 jiffies;
194 int8_t rssi_ctl0;
195 int8_t rssi_ctl1;
196 int8_t rssi_ctl2;
197 int8_t rssi_ext0;
198 int8_t rssi_ext1;
199 int8_t rssi_ext2;
200 int8_t rssi;
201 bool isok;
202 u8 rts_fail_cnt;
203 u8 data_fail_cnt;
204 u8 rateindex;
205 u8 qid;
206 u8 tid;
207 u32 ba_low;
208 u32 ba_high;
209 } ts[ATH_DBG_MAX_SAMPLES];
210 struct {
211 u64 jiffies;
212 int8_t rssi_ctl0;
213 int8_t rssi_ctl1;
214 int8_t rssi_ctl2;
215 int8_t rssi_ext0;
216 int8_t rssi_ext1;
217 int8_t rssi_ext2;
218 int8_t rssi;
219 bool is_mybeacon;
220 u8 antenna;
221 u8 rate;
222 } rs[ATH_DBG_MAX_SAMPLES];
223 struct ath_cycle_counters cc;
224 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
225 };
226
227 struct ath9k_debug {
228 struct dentry *debugfs_phy;
229 u32 regidx;
230 struct ath_stats stats;
231 #ifdef CONFIG_ATH9K_MAC_DEBUG
232 spinlock_t samp_lock;
233 struct ath_dbg_bb_mac_samp bb_mac_samp[ATH_DBG_MAX_SAMPLES];
234 u8 sampidx;
235 u8 tsidx;
236 u8 rsidx;
237 #endif
238 };
239
240 int ath9k_init_debug(struct ath_hw *ah);
241
242 void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
243 void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
244 struct ath_tx_status *ts, struct ath_txq *txq,
245 unsigned int flags);
246 void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);
247
248 #else
249
ath9k_init_debug(struct ath_hw * ah)250 static inline int ath9k_init_debug(struct ath_hw *ah)
251 {
252 return 0;
253 }
254
ath_debug_stat_interrupt(struct ath_softc * sc,enum ath9k_int status)255 static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
256 enum ath9k_int status)
257 {
258 }
259
ath_debug_stat_tx(struct ath_softc * sc,struct ath_buf * bf,struct ath_tx_status * ts,struct ath_txq * txq,unsigned int flags)260 static inline void ath_debug_stat_tx(struct ath_softc *sc,
261 struct ath_buf *bf,
262 struct ath_tx_status *ts,
263 struct ath_txq *txq,
264 unsigned int flags)
265 {
266 }
267
ath_debug_stat_rx(struct ath_softc * sc,struct ath_rx_status * rs)268 static inline void ath_debug_stat_rx(struct ath_softc *sc,
269 struct ath_rx_status *rs)
270 {
271 }
272
273 #endif /* CONFIG_ATH9K_DEBUGFS */
274
275 #ifdef CONFIG_ATH9K_MAC_DEBUG
276
277 void ath9k_debug_samp_bb_mac(struct ath_softc *sc);
278
279 #else
280
ath9k_debug_samp_bb_mac(struct ath_softc * sc)281 static inline void ath9k_debug_samp_bb_mac(struct ath_softc *sc)
282 {
283 }
284
285 #endif
286
287
288 #endif /* DEBUG_H */
289