1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012  Realtek Corporation.*/
3 
4 #include "../wifi.h"
5 #include "../rtl8192ce/reg.h"
6 #include "../rtl8192ce/def.h"
7 #include "dm_common.h"
8 #include "fw_common.h"
9 #include "phy_common.h"
10 #include <linux/export.h>
11 
rtl92c_phy_query_bb_reg(struct ieee80211_hw * hw,u32 regaddr,u32 bitmask)12 u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
13 {
14 	struct rtl_priv *rtlpriv = rtl_priv(hw);
15 	u32 returnvalue, originalvalue, bitshift;
16 
17 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
18 		regaddr, bitmask);
19 	originalvalue = rtl_read_dword(rtlpriv, regaddr);
20 	bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
21 	returnvalue = (originalvalue & bitmask) >> bitshift;
22 
23 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
24 		"BBR MASK=0x%x Addr[0x%x]=0x%x\n",
25 		bitmask, regaddr, originalvalue);
26 
27 	return returnvalue;
28 }
29 EXPORT_SYMBOL(rtl92c_phy_query_bb_reg);
30 
rtl92c_phy_set_bb_reg(struct ieee80211_hw * hw,u32 regaddr,u32 bitmask,u32 data)31 void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw,
32 			   u32 regaddr, u32 bitmask, u32 data)
33 {
34 	struct rtl_priv *rtlpriv = rtl_priv(hw);
35 	u32 originalvalue, bitshift;
36 
37 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
38 		"regaddr(%#x), bitmask(%#x), data(%#x)\n",
39 		regaddr, bitmask, data);
40 
41 	if (bitmask != MASKDWORD) {
42 		originalvalue = rtl_read_dword(rtlpriv, regaddr);
43 		bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
44 		data = ((originalvalue & (~bitmask)) | (data << bitshift));
45 	}
46 
47 	rtl_write_dword(rtlpriv, regaddr, data);
48 
49 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
50 		"regaddr(%#x), bitmask(%#x), data(%#x)\n",
51 		regaddr, bitmask, data);
52 }
53 EXPORT_SYMBOL(rtl92c_phy_set_bb_reg);
54 
_rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw * hw,enum radio_path rfpath,u32 offset)55 u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw,
56 				  enum radio_path rfpath, u32 offset)
57 {
58 	WARN_ONCE(true, "rtl8192c-common: _rtl92c_phy_fw_rf_serial_read deprecated!\n");
59 	return 0;
60 }
61 EXPORT_SYMBOL(_rtl92c_phy_fw_rf_serial_read);
62 
_rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw * hw,enum radio_path rfpath,u32 offset,u32 data)63 void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
64 				    enum radio_path rfpath, u32 offset,
65 				    u32 data)
66 {
67 	WARN_ONCE(true, "rtl8192c-common: _rtl92c_phy_fw_rf_serial_write deprecated!\n");
68 }
69 EXPORT_SYMBOL(_rtl92c_phy_fw_rf_serial_write);
70 
_rtl92c_phy_rf_serial_read(struct ieee80211_hw * hw,enum radio_path rfpath,u32 offset)71 u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
72 			       enum radio_path rfpath, u32 offset)
73 {
74 	struct rtl_priv *rtlpriv = rtl_priv(hw);
75 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
76 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
77 	u32 newoffset;
78 	u32 tmplong, tmplong2;
79 	u8 rfpi_enable = 0;
80 	u32 retvalue;
81 
82 	offset &= 0x3f;
83 	newoffset = offset;
84 	if (RT_CANNOT_IO(hw)) {
85 		pr_err("return all one\n");
86 		return 0xFFFFFFFF;
87 	}
88 	tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
89 	if (rfpath == RF90_PATH_A)
90 		tmplong2 = tmplong;
91 	else
92 		tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
93 	tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
94 	    (newoffset << 23) | BLSSIREADEDGE;
95 	rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
96 		      tmplong & (~BLSSIREADEDGE));
97 	mdelay(1);
98 	rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
99 	mdelay(1);
100 	rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
101 		      tmplong | BLSSIREADEDGE);
102 	mdelay(1);
103 	if (rfpath == RF90_PATH_A)
104 		rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
105 						 BIT(8));
106 	else if (rfpath == RF90_PATH_B)
107 		rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
108 						 BIT(8));
109 	if (rfpi_enable)
110 		retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
111 					 BLSSIREADBACKDATA);
112 	else
113 		retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
114 					 BLSSIREADBACKDATA);
115 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n",
116 		rfpath, pphyreg->rf_rb,
117 		retvalue);
118 	return retvalue;
119 }
120 EXPORT_SYMBOL(_rtl92c_phy_rf_serial_read);
121 
_rtl92c_phy_rf_serial_write(struct ieee80211_hw * hw,enum radio_path rfpath,u32 offset,u32 data)122 void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
123 				 enum radio_path rfpath, u32 offset,
124 				 u32 data)
125 {
126 	u32 data_and_addr;
127 	u32 newoffset;
128 	struct rtl_priv *rtlpriv = rtl_priv(hw);
129 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
130 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
131 
132 	if (RT_CANNOT_IO(hw)) {
133 		pr_err("stop\n");
134 		return;
135 	}
136 	offset &= 0x3f;
137 	newoffset = offset;
138 	data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
139 	rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
140 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
141 		rfpath, pphyreg->rf3wire_offset,
142 		data_and_addr);
143 }
144 EXPORT_SYMBOL(_rtl92c_phy_rf_serial_write);
145 
_rtl92c_phy_calculate_bit_shift(u32 bitmask)146 u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask)
147 {
148 	u32 i = ffs(bitmask);
149 
150 	return i ? i - 1 : 32;
151 }
152 EXPORT_SYMBOL(_rtl92c_phy_calculate_bit_shift);
153 
_rtl92c_phy_bb_config_1t(struct ieee80211_hw * hw)154 static void _rtl92c_phy_bb_config_1t(struct ieee80211_hw *hw)
155 {
156 	rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2);
157 	rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022);
158 	rtl_set_bbreg(hw, RCCK0_AFESETTING, MASKBYTE3, 0x45);
159 	rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23);
160 	rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, 0x30, 0x1);
161 	rtl_set_bbreg(hw, 0xe74, 0x0c000000, 0x2);
162 	rtl_set_bbreg(hw, 0xe78, 0x0c000000, 0x2);
163 	rtl_set_bbreg(hw, 0xe7c, 0x0c000000, 0x2);
164 	rtl_set_bbreg(hw, 0xe80, 0x0c000000, 0x2);
165 	rtl_set_bbreg(hw, 0xe88, 0x0c000000, 0x2);
166 }
167 
rtl92c_phy_rf_config(struct ieee80211_hw * hw)168 bool rtl92c_phy_rf_config(struct ieee80211_hw *hw)
169 {
170 	struct rtl_priv *rtlpriv = rtl_priv(hw);
171 
172 	return rtlpriv->cfg->ops->phy_rf6052_config(hw);
173 }
174 EXPORT_SYMBOL(rtl92c_phy_rf_config);
175 
_rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw * hw)176 bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw)
177 {
178 	struct rtl_priv *rtlpriv = rtl_priv(hw);
179 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
180 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
181 	bool rtstatus;
182 
183 	rtstatus = rtlpriv->cfg->ops->config_bb_with_headerfile(hw,
184 						 BASEBAND_CONFIG_PHY_REG);
185 	if (!rtstatus) {
186 		pr_err("Write BB Reg Fail!!\n");
187 		return false;
188 	}
189 	if (rtlphy->rf_type == RF_1T2R) {
190 		_rtl92c_phy_bb_config_1t(hw);
191 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n");
192 	}
193 	if (rtlefuse->autoload_failflag == false) {
194 		rtlphy->pwrgroup_cnt = 0;
195 		rtstatus = rtlpriv->cfg->ops->config_bb_with_pgheaderfile(hw,
196 						   BASEBAND_CONFIG_PHY_REG);
197 	}
198 	if (!rtstatus) {
199 		pr_err("BB_PG Reg Fail!!\n");
200 		return false;
201 	}
202 	rtstatus = rtlpriv->cfg->ops->config_bb_with_headerfile(hw,
203 						 BASEBAND_CONFIG_AGC_TAB);
204 	if (!rtstatus) {
205 		pr_err("AGC Table Fail\n");
206 		return false;
207 	}
208 	rtlphy->cck_high_power =
209 		(bool)(rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, 0x200));
210 
211 	return true;
212 }
213 
214 EXPORT_SYMBOL(_rtl92c_phy_bb8192c_config_parafile);
215 
_rtl92c_store_pwrindex_diffrate_offset(struct ieee80211_hw * hw,u32 regaddr,u32 bitmask,u32 data)216 void _rtl92c_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
217 					    u32 regaddr, u32 bitmask,
218 					    u32 data)
219 {
220 	struct rtl_priv *rtlpriv = rtl_priv(hw);
221 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
222 
223 	if (regaddr == RTXAGC_A_RATE18_06) {
224 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][0] =
225 		    data;
226 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
227 			"MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n",
228 			rtlphy->pwrgroup_cnt,
229 			rtlphy->mcs_txpwrlevel_origoffset
230 			[rtlphy->pwrgroup_cnt][0]);
231 	}
232 	if (regaddr == RTXAGC_A_RATE54_24) {
233 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][1] =
234 		    data;
235 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
236 			"MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n",
237 			rtlphy->pwrgroup_cnt,
238 			rtlphy->mcs_txpwrlevel_origoffset
239 			[rtlphy->pwrgroup_cnt][1]);
240 	}
241 	if (regaddr == RTXAGC_A_CCK1_MCS32) {
242 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][6] =
243 		    data;
244 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
245 			"MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n",
246 			rtlphy->pwrgroup_cnt,
247 			rtlphy->mcs_txpwrlevel_origoffset
248 			[rtlphy->pwrgroup_cnt][6]);
249 	}
250 	if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) {
251 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][7] =
252 		    data;
253 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
254 			"MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n",
255 			rtlphy->pwrgroup_cnt,
256 			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
257 							    pwrgroup_cnt][7]);
258 	}
259 	if (regaddr == RTXAGC_A_MCS03_MCS00) {
260 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][2] =
261 		    data;
262 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
263 			"MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n",
264 			rtlphy->pwrgroup_cnt,
265 			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
266 							    pwrgroup_cnt][2]);
267 	}
268 	if (regaddr == RTXAGC_A_MCS07_MCS04) {
269 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][3] =
270 		    data;
271 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
272 			"MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n",
273 			rtlphy->pwrgroup_cnt,
274 			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
275 							    pwrgroup_cnt][3]);
276 	}
277 	if (regaddr == RTXAGC_A_MCS11_MCS08) {
278 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][4] =
279 		    data;
280 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
281 			"MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n",
282 			rtlphy->pwrgroup_cnt,
283 			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
284 							    pwrgroup_cnt][4]);
285 	}
286 	if (regaddr == RTXAGC_A_MCS15_MCS12) {
287 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][5] =
288 		    data;
289 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
290 			"MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n",
291 			rtlphy->pwrgroup_cnt,
292 			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
293 							    pwrgroup_cnt][5]);
294 	}
295 	if (regaddr == RTXAGC_B_RATE18_06) {
296 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][8] =
297 		    data;
298 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
299 			"MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n",
300 			rtlphy->pwrgroup_cnt,
301 			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
302 							    pwrgroup_cnt][8]);
303 	}
304 	if (regaddr == RTXAGC_B_RATE54_24) {
305 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][9] =
306 		    data;
307 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
308 			"MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n",
309 			rtlphy->pwrgroup_cnt,
310 			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
311 							    pwrgroup_cnt][9]);
312 	}
313 	if (regaddr == RTXAGC_B_CCK1_55_MCS32) {
314 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][14] =
315 		    data;
316 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
317 			"MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n",
318 			rtlphy->pwrgroup_cnt,
319 			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
320 							    pwrgroup_cnt][14]);
321 	}
322 	if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) {
323 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][15] =
324 		    data;
325 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
326 			"MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n",
327 			rtlphy->pwrgroup_cnt,
328 			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
329 							    pwrgroup_cnt][15]);
330 	}
331 	if (regaddr == RTXAGC_B_MCS03_MCS00) {
332 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][10] =
333 		    data;
334 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
335 			"MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n",
336 			rtlphy->pwrgroup_cnt,
337 			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
338 							    pwrgroup_cnt][10]);
339 	}
340 	if (regaddr == RTXAGC_B_MCS07_MCS04) {
341 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][11] =
342 		    data;
343 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
344 			"MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n",
345 			rtlphy->pwrgroup_cnt,
346 			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
347 							    pwrgroup_cnt][11]);
348 	}
349 	if (regaddr == RTXAGC_B_MCS11_MCS08) {
350 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][12] =
351 		    data;
352 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
353 			"MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n",
354 			rtlphy->pwrgroup_cnt,
355 			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
356 							    pwrgroup_cnt][12]);
357 	}
358 	if (regaddr == RTXAGC_B_MCS15_MCS12) {
359 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][13] =
360 		    data;
361 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
362 			"MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n",
363 			rtlphy->pwrgroup_cnt,
364 			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
365 							    pwrgroup_cnt][13]);
366 
367 		rtlphy->pwrgroup_cnt++;
368 	}
369 }
370 EXPORT_SYMBOL(_rtl92c_store_pwrindex_diffrate_offset);
371 
rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw * hw)372 void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
373 {
374 	struct rtl_priv *rtlpriv = rtl_priv(hw);
375 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
376 
377 	rtlphy->default_initialgain[0] =
378 	    (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
379 	rtlphy->default_initialgain[1] =
380 	    (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
381 	rtlphy->default_initialgain[2] =
382 	    (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
383 	rtlphy->default_initialgain[3] =
384 	    (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
385 
386 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
387 		"Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
388 		rtlphy->default_initialgain[0],
389 		rtlphy->default_initialgain[1],
390 		rtlphy->default_initialgain[2],
391 		rtlphy->default_initialgain[3]);
392 
393 	rtlphy->framesync = (u8)rtl_get_bbreg(hw,
394 					       ROFDM0_RXDETECTOR3, MASKBYTE0);
395 	rtlphy->framesync_c34 = rtl_get_bbreg(hw,
396 					      ROFDM0_RXDETECTOR2, MASKDWORD);
397 
398 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
399 		"Default framesync (0x%x) = 0x%x\n",
400 		ROFDM0_RXDETECTOR3, rtlphy->framesync);
401 }
402 
_rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw * hw)403 void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
404 {
405 	struct rtl_priv *rtlpriv = rtl_priv(hw);
406 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
407 
408 	rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
409 	rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
410 	rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
411 	rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
412 
413 	rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
414 	rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
415 	rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
416 	rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
417 
418 	rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
419 	rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
420 
421 	rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
422 	rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
423 
424 	rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
425 	    RFPGA0_XA_LSSIPARAMETER;
426 	rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
427 	    RFPGA0_XB_LSSIPARAMETER;
428 
429 	rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
430 	rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
431 	rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
432 	rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
433 
434 	rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
435 	rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
436 	rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
437 	rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
438 
439 	rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
440 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
441 
442 	rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
443 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
444 
445 	rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
446 	rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
447 	rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
448 	rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
449 
450 	rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
451 	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
452 	rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
453 	rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
454 
455 	rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
456 	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
457 	rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
458 	rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
459 
460 	rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
461 	rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
462 	rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBANLANCE;
463 	rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
464 
465 	rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
466 	rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
467 	rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
468 	rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
469 
470 	rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
471 	rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
472 	rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
473 	rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
474 
475 	rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
476 	rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
477 	rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
478 	rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
479 
480 	rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
481 	rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
482 	rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
483 	rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
484 
485 	rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;
486 	rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;
487 
488 }
489 EXPORT_SYMBOL(_rtl92c_phy_init_bb_rf_register_definition);
490 
rtl92c_phy_get_txpower_level(struct ieee80211_hw * hw,long * powerlevel)491 void rtl92c_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
492 {
493 	struct rtl_priv *rtlpriv = rtl_priv(hw);
494 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
495 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
496 	u8 txpwr_level;
497 	long txpwr_dbm;
498 
499 	txpwr_level = rtlphy->cur_cck_txpwridx;
500 	txpwr_dbm = _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_B,
501 						 txpwr_level);
502 	txpwr_level = rtlphy->cur_ofdm24g_txpwridx +
503 	    rtlefuse->legacy_ht_txpowerdiff;
504 	if (_rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
505 					 txpwr_level) > txpwr_dbm)
506 		txpwr_dbm =
507 		    _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
508 						 txpwr_level);
509 	txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
510 	if (_rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
511 					 txpwr_level) > txpwr_dbm)
512 		txpwr_dbm =
513 		    _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
514 						 txpwr_level);
515 	*powerlevel = txpwr_dbm;
516 }
517 
_rtl92c_get_txpower_index(struct ieee80211_hw * hw,u8 channel,u8 * cckpowerlevel,u8 * ofdmpowerlevel)518 static void _rtl92c_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
519 				      u8 *cckpowerlevel, u8 *ofdmpowerlevel)
520 {
521 	struct rtl_priv *rtlpriv = rtl_priv(hw);
522 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
523 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
524 	u8 index = (channel - 1);
525 
526 	cckpowerlevel[RF90_PATH_A] =
527 	    rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
528 	cckpowerlevel[RF90_PATH_B] =
529 	    rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
530 	if (get_rf_type(rtlphy) == RF_1T2R || get_rf_type(rtlphy) == RF_1T1R) {
531 		ofdmpowerlevel[RF90_PATH_A] =
532 		    rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
533 		ofdmpowerlevel[RF90_PATH_B] =
534 		    rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
535 	} else if (get_rf_type(rtlphy) == RF_2T2R) {
536 		ofdmpowerlevel[RF90_PATH_A] =
537 		    rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
538 		ofdmpowerlevel[RF90_PATH_B] =
539 		    rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
540 	}
541 }
542 
_rtl92c_ccxpower_index_check(struct ieee80211_hw * hw,u8 channel,u8 * cckpowerlevel,u8 * ofdmpowerlevel)543 static void _rtl92c_ccxpower_index_check(struct ieee80211_hw *hw,
544 					 u8 channel, u8 *cckpowerlevel,
545 					 u8 *ofdmpowerlevel)
546 {
547 	struct rtl_priv *rtlpriv = rtl_priv(hw);
548 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
549 
550 	rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
551 	rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
552 }
553 
rtl92c_phy_set_txpower_level(struct ieee80211_hw * hw,u8 channel)554 void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
555 {
556 	struct rtl_priv *rtlpriv = rtl_priv(hw);
557 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
558 	u8 cckpowerlevel[2], ofdmpowerlevel[2];
559 
560 	if (!rtlefuse->txpwr_fromeprom)
561 		return;
562 	_rtl92c_get_txpower_index(hw, channel,
563 				  &cckpowerlevel[0], &ofdmpowerlevel[0]);
564 	_rtl92c_ccxpower_index_check(hw, channel, &cckpowerlevel[0],
565 				     &ofdmpowerlevel[0]);
566 	rtlpriv->cfg->ops->phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
567 	rtlpriv->cfg->ops->phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0],
568 						       channel);
569 }
570 EXPORT_SYMBOL(rtl92c_phy_set_txpower_level);
571 
rtl92c_phy_update_txpower_dbm(struct ieee80211_hw * hw,long power_indbm)572 bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw, long power_indbm)
573 {
574 	struct rtl_priv *rtlpriv = rtl_priv(hw);
575 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
576 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
577 	u8 idx;
578 	u8 rf_path;
579 	u8 ccktxpwridx = _rtl92c_phy_dbm_to_txpwr_idx(hw, WIRELESS_MODE_B,
580 						      power_indbm);
581 	u8 ofdmtxpwridx = _rtl92c_phy_dbm_to_txpwr_idx(hw, WIRELESS_MODE_N_24G,
582 						       power_indbm);
583 	if (ofdmtxpwridx - rtlefuse->legacy_ht_txpowerdiff > 0)
584 		ofdmtxpwridx -= rtlefuse->legacy_ht_txpowerdiff;
585 	else
586 		ofdmtxpwridx = 0;
587 	rtl_dbg(rtlpriv, COMP_TXAGC, DBG_TRACE,
588 		"%lx dBm, ccktxpwridx = %d, ofdmtxpwridx = %d\n",
589 		power_indbm, ccktxpwridx, ofdmtxpwridx);
590 	for (idx = 0; idx < 14; idx++) {
591 		for (rf_path = 0; rf_path < 2; rf_path++) {
592 			rtlefuse->txpwrlevel_cck[rf_path][idx] = ccktxpwridx;
593 			rtlefuse->txpwrlevel_ht40_1s[rf_path][idx] =
594 			    ofdmtxpwridx;
595 			rtlefuse->txpwrlevel_ht40_2s[rf_path][idx] =
596 			    ofdmtxpwridx;
597 		}
598 	}
599 	rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
600 	return true;
601 }
602 EXPORT_SYMBOL(rtl92c_phy_update_txpower_dbm);
603 
_rtl92c_phy_dbm_to_txpwr_idx(struct ieee80211_hw * hw,enum wireless_mode wirelessmode,long power_indbm)604 u8 _rtl92c_phy_dbm_to_txpwr_idx(struct ieee80211_hw *hw,
605 				enum wireless_mode wirelessmode,
606 				long power_indbm)
607 {
608 	u8 txpwridx;
609 	long offset;
610 
611 	switch (wirelessmode) {
612 	case WIRELESS_MODE_B:
613 		offset = -7;
614 		break;
615 	case WIRELESS_MODE_G:
616 	case WIRELESS_MODE_N_24G:
617 		offset = -8;
618 		break;
619 	default:
620 		offset = -8;
621 		break;
622 	}
623 
624 	if ((power_indbm - offset) > 0)
625 		txpwridx = (u8)((power_indbm - offset) * 2);
626 	else
627 		txpwridx = 0;
628 
629 	if (txpwridx > MAX_TXPWR_IDX_NMODE_92S)
630 		txpwridx = MAX_TXPWR_IDX_NMODE_92S;
631 
632 	return txpwridx;
633 }
634 EXPORT_SYMBOL(_rtl92c_phy_dbm_to_txpwr_idx);
635 
_rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw * hw,enum wireless_mode wirelessmode,u8 txpwridx)636 long _rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
637 				  enum wireless_mode wirelessmode,
638 				  u8 txpwridx)
639 {
640 	long offset;
641 	long pwrout_dbm;
642 
643 	switch (wirelessmode) {
644 	case WIRELESS_MODE_B:
645 		offset = -7;
646 		break;
647 	case WIRELESS_MODE_G:
648 	case WIRELESS_MODE_N_24G:
649 		offset = -8;
650 		break;
651 	default:
652 		offset = -8;
653 		break;
654 	}
655 	pwrout_dbm = txpwridx / 2 + offset;
656 	return pwrout_dbm;
657 }
658 EXPORT_SYMBOL(_rtl92c_phy_txpwr_idx_to_dbm);
659 
rtl92c_phy_set_bw_mode(struct ieee80211_hw * hw,enum nl80211_channel_type ch_type)660 void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw,
661 			    enum nl80211_channel_type ch_type)
662 {
663 	struct rtl_priv *rtlpriv = rtl_priv(hw);
664 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
665 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
666 	u8 tmp_bw = rtlphy->current_chan_bw;
667 
668 	if (rtlphy->set_bwmode_inprogress)
669 		return;
670 	rtlphy->set_bwmode_inprogress = true;
671 	if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
672 		rtlpriv->cfg->ops->phy_set_bw_mode_callback(hw);
673 	} else {
674 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
675 			"false driver sleep or unload\n");
676 		rtlphy->set_bwmode_inprogress = false;
677 		rtlphy->current_chan_bw = tmp_bw;
678 	}
679 }
680 EXPORT_SYMBOL(rtl92c_phy_set_bw_mode);
681 
rtl92c_phy_sw_chnl_callback(struct ieee80211_hw * hw)682 void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw)
683 {
684 	struct rtl_priv *rtlpriv = rtl_priv(hw);
685 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
686 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
687 	u32 delay;
688 
689 	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE,
690 		"switch to channel%d\n", rtlphy->current_channel);
691 	if (is_hal_stop(rtlhal))
692 		return;
693 	do {
694 		if (!rtlphy->sw_chnl_inprogress)
695 			break;
696 		if (!_rtl92c_phy_sw_chnl_step_by_step
697 		    (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
698 		     &rtlphy->sw_chnl_step, &delay)) {
699 			if (delay > 0)
700 				mdelay(delay);
701 			else
702 				continue;
703 		} else {
704 			rtlphy->sw_chnl_inprogress = false;
705 		}
706 		break;
707 	} while (true);
708 	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
709 }
710 EXPORT_SYMBOL(rtl92c_phy_sw_chnl_callback);
711 
rtl92c_phy_sw_chnl(struct ieee80211_hw * hw)712 u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw)
713 {
714 	struct rtl_priv *rtlpriv = rtl_priv(hw);
715 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
716 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
717 
718 	if (rtlphy->sw_chnl_inprogress)
719 		return 0;
720 	if (rtlphy->set_bwmode_inprogress)
721 		return 0;
722 	WARN_ONCE((rtlphy->current_channel > 14),
723 		  "rtl8192c-common: WIRELESS_MODE_G but channel>14");
724 	rtlphy->sw_chnl_inprogress = true;
725 	rtlphy->sw_chnl_stage = 0;
726 	rtlphy->sw_chnl_step = 0;
727 	if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
728 		rtl92c_phy_sw_chnl_callback(hw);
729 		rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD,
730 			"sw_chnl_inprogress false schedule workitem\n");
731 		rtlphy->sw_chnl_inprogress = false;
732 	} else {
733 		rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD,
734 			"sw_chnl_inprogress false driver sleep or unload\n");
735 		rtlphy->sw_chnl_inprogress = false;
736 	}
737 	return 1;
738 }
739 EXPORT_SYMBOL(rtl92c_phy_sw_chnl);
740 
_rtl92c_phy_sw_rf_seting(struct ieee80211_hw * hw,u8 channel)741 static void _rtl92c_phy_sw_rf_seting(struct ieee80211_hw *hw, u8 channel)
742 {
743 	struct rtl_priv *rtlpriv = rtl_priv(hw);
744 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
745 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
746 
747 	if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version)) {
748 		if (channel == 6 &&
749 		    rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
750 			rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1,
751 				      MASKDWORD, 0x00255);
752 		} else {
753 			u32 backuprf0x1A =
754 			  (u32)rtl_get_rfreg(hw, RF90_PATH_A, RF_RX_G1,
755 					     RFREG_OFFSET_MASK);
756 			rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD,
757 				      backuprf0x1A);
758 		}
759 	}
760 }
761 
_rtl92c_phy_set_sw_chnl_cmdarray(struct swchnlcmd * cmdtable,u32 cmdtableidx,u32 cmdtablesz,enum swchnlcmd_id cmdid,u32 para1,u32 para2,u32 msdelay)762 static bool _rtl92c_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
763 					     u32 cmdtableidx, u32 cmdtablesz,
764 					     enum swchnlcmd_id cmdid,
765 					     u32 para1, u32 para2, u32 msdelay)
766 {
767 	struct swchnlcmd *pcmd;
768 
769 	if (cmdtable == NULL) {
770 		WARN_ONCE(true, "rtl8192c-common: cmdtable cannot be NULL.\n");
771 		return false;
772 	}
773 
774 	if (cmdtableidx >= cmdtablesz)
775 		return false;
776 
777 	pcmd = cmdtable + cmdtableidx;
778 	pcmd->cmdid = cmdid;
779 	pcmd->para1 = para1;
780 	pcmd->para2 = para2;
781 	pcmd->msdelay = msdelay;
782 	return true;
783 }
784 
_rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw * hw,u8 channel,u8 * stage,u8 * step,u32 * delay)785 bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
786 				      u8 channel, u8 *stage, u8 *step,
787 				      u32 *delay)
788 {
789 	struct rtl_priv *rtlpriv = rtl_priv(hw);
790 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
791 	struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
792 	u32 precommoncmdcnt;
793 	struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
794 	u32 postcommoncmdcnt;
795 	struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
796 	u32 rfdependcmdcnt;
797 	struct swchnlcmd *currentcmd = NULL;
798 	u8 rfpath;
799 	u8 num_total_rfpath = rtlphy->num_total_rfpath;
800 
801 	precommoncmdcnt = 0;
802 	_rtl92c_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
803 					 MAX_PRECMD_CNT,
804 					 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
805 	_rtl92c_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
806 					 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
807 
808 	postcommoncmdcnt = 0;
809 
810 	_rtl92c_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
811 					 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
812 
813 	rfdependcmdcnt = 0;
814 
815 	WARN_ONCE((channel < 1 || channel > 14),
816 		  "rtl8192c-common: illegal channel for Zebra: %d\n", channel);
817 
818 	_rtl92c_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
819 					 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
820 					 RF_CHNLBW, channel, 10);
821 
822 	_rtl92c_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
823 					 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0,
824 					 0);
825 
826 	do {
827 		switch (*stage) {
828 		case 0:
829 			currentcmd = &precommoncmd[*step];
830 			break;
831 		case 1:
832 			currentcmd = &rfdependcmd[*step];
833 			break;
834 		case 2:
835 			currentcmd = &postcommoncmd[*step];
836 			break;
837 		default:
838 			pr_err("Invalid 'stage' = %d, Check it!\n",
839 			       *stage);
840 			return true;
841 		}
842 
843 		if (currentcmd->cmdid == CMDID_END) {
844 			if ((*stage) == 2) {
845 				return true;
846 			} else {
847 				(*stage)++;
848 				(*step) = 0;
849 				continue;
850 			}
851 		}
852 
853 		switch (currentcmd->cmdid) {
854 		case CMDID_SET_TXPOWEROWER_LEVEL:
855 			rtl92c_phy_set_txpower_level(hw, channel);
856 			break;
857 		case CMDID_WRITEPORT_ULONG:
858 			rtl_write_dword(rtlpriv, currentcmd->para1,
859 					currentcmd->para2);
860 			break;
861 		case CMDID_WRITEPORT_USHORT:
862 			rtl_write_word(rtlpriv, currentcmd->para1,
863 				       (u16) currentcmd->para2);
864 			break;
865 		case CMDID_WRITEPORT_UCHAR:
866 			rtl_write_byte(rtlpriv, currentcmd->para1,
867 				       (u8)currentcmd->para2);
868 			break;
869 		case CMDID_RF_WRITEREG:
870 			for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
871 				rtlphy->rfreg_chnlval[rfpath] =
872 				    ((rtlphy->rfreg_chnlval[rfpath] &
873 				      0xfffffc00) | currentcmd->para2);
874 
875 				rtl_set_rfreg(hw, (enum radio_path)rfpath,
876 					      currentcmd->para1,
877 					      RFREG_OFFSET_MASK,
878 					      rtlphy->rfreg_chnlval[rfpath]);
879 			}
880 			_rtl92c_phy_sw_rf_seting(hw, channel);
881 			break;
882 		default:
883 			rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
884 				"switch case %#x not processed\n",
885 				currentcmd->cmdid);
886 			break;
887 		}
888 
889 		break;
890 	} while (true);
891 
892 	(*delay) = currentcmd->msdelay;
893 	(*step)++;
894 	return false;
895 }
896 
rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw * hw,u32 rfpath)897 bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw, u32 rfpath)
898 {
899 	return true;
900 }
901 EXPORT_SYMBOL(rtl8192_phy_check_is_legal_rfpath);
902 
_rtl92c_phy_path_a_iqk(struct ieee80211_hw * hw,bool config_pathb)903 static u8 _rtl92c_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
904 {
905 	u32 reg_eac, reg_e94, reg_e9c, reg_ea4;
906 	u8 result = 0x00;
907 
908 	rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
909 	rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
910 	rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
911 	rtl_set_bbreg(hw, 0xe3c, MASKDWORD,
912 		      config_pathb ? 0x28160202 : 0x28160502);
913 
914 	if (config_pathb) {
915 		rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
916 		rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
917 		rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
918 		rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160202);
919 	}
920 
921 	rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x001028d1);
922 	rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
923 	rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
924 
925 	mdelay(IQK_DELAY_TIME);
926 
927 	reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
928 	reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
929 	reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
930 	reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
931 
932 	if (!(reg_eac & BIT(28)) &&
933 	    (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
934 	    (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
935 		result |= 0x01;
936 	else
937 		return result;
938 
939 	if (!(reg_eac & BIT(27)) &&
940 	    (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
941 	    (((reg_eac & 0x03FF0000) >> 16) != 0x36))
942 		result |= 0x02;
943 	return result;
944 }
945 
_rtl92c_phy_path_b_iqk(struct ieee80211_hw * hw)946 static u8 _rtl92c_phy_path_b_iqk(struct ieee80211_hw *hw)
947 {
948 	u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
949 	u8 result = 0x00;
950 
951 	rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
952 	rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
953 	mdelay(IQK_DELAY_TIME);
954 	reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
955 	reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
956 	reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
957 	reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
958 	reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
959 
960 	if (!(reg_eac & BIT(31)) &&
961 	    (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
962 	    (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
963 		result |= 0x01;
964 	else
965 		return result;
966 	if (!(reg_eac & BIT(30)) &&
967 	    (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
968 	    (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
969 		result |= 0x02;
970 	return result;
971 }
972 
_rtl92c_phy_path_a_fill_iqk_matrix(struct ieee80211_hw * hw,bool b_iqk_ok,long result[][8],u8 final_candidate,bool btxonly)973 static void _rtl92c_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw,
974 					       bool b_iqk_ok, long result[][8],
975 					       u8 final_candidate, bool btxonly)
976 {
977 	u32 oldval_0, x, tx0_a, reg;
978 	long y, tx0_c;
979 
980 	if (final_candidate == 0xFF) {
981 		return;
982 	} else if (b_iqk_ok) {
983 		oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
984 					  MASKDWORD) >> 22) & 0x3FF;
985 		x = result[final_candidate][0];
986 		if ((x & 0x00000200) != 0)
987 			x = x | 0xFFFFFC00;
988 		tx0_a = (x * oldval_0) >> 8;
989 		rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
990 		rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31),
991 			      ((x * oldval_0 >> 7) & 0x1));
992 		y = result[final_candidate][1];
993 		if ((y & 0x00000200) != 0)
994 			y = y | 0xFFFFFC00;
995 		tx0_c = (y * oldval_0) >> 8;
996 		rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
997 			      ((tx0_c & 0x3C0) >> 6));
998 		rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
999 			      (tx0_c & 0x3F));
1000 		rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29),
1001 			      ((y * oldval_0 >> 7) & 0x1));
1002 		if (btxonly)
1003 			return;
1004 		reg = result[final_candidate][2];
1005 		rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
1006 		reg = result[final_candidate][3] & 0x3F;
1007 		rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
1008 		reg = (result[final_candidate][3] >> 6) & 0xF;
1009 		rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
1010 	}
1011 }
1012 
_rtl92c_phy_path_b_fill_iqk_matrix(struct ieee80211_hw * hw,bool b_iqk_ok,long result[][8],u8 final_candidate,bool btxonly)1013 static void _rtl92c_phy_path_b_fill_iqk_matrix(struct ieee80211_hw *hw,
1014 					       bool b_iqk_ok, long result[][8],
1015 					       u8 final_candidate, bool btxonly)
1016 {
1017 	u32 oldval_1, x, tx1_a, reg;
1018 	long y, tx1_c;
1019 
1020 	if (final_candidate == 0xFF) {
1021 		return;
1022 	} else if (b_iqk_ok) {
1023 		oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
1024 					  MASKDWORD) >> 22) & 0x3FF;
1025 		x = result[final_candidate][4];
1026 		if ((x & 0x00000200) != 0)
1027 			x = x | 0xFFFFFC00;
1028 		tx1_a = (x * oldval_1) >> 8;
1029 		rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a);
1030 		rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27),
1031 			      ((x * oldval_1 >> 7) & 0x1));
1032 		y = result[final_candidate][5];
1033 		if ((y & 0x00000200) != 0)
1034 			y = y | 0xFFFFFC00;
1035 		tx1_c = (y * oldval_1) >> 8;
1036 		rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000,
1037 			      ((tx1_c & 0x3C0) >> 6));
1038 		rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000,
1039 			      (tx1_c & 0x3F));
1040 		rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25),
1041 			      ((y * oldval_1 >> 7) & 0x1));
1042 		if (btxonly)
1043 			return;
1044 		reg = result[final_candidate][6];
1045 		rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
1046 		reg = result[final_candidate][7] & 0x3F;
1047 		rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
1048 		reg = (result[final_candidate][7] >> 6) & 0xF;
1049 		rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg);
1050 	}
1051 }
1052 
_rtl92c_phy_save_adda_registers(struct ieee80211_hw * hw,u32 * addareg,u32 * addabackup,u32 registernum)1053 static void _rtl92c_phy_save_adda_registers(struct ieee80211_hw *hw,
1054 					    u32 *addareg, u32 *addabackup,
1055 					    u32 registernum)
1056 {
1057 	u32 i;
1058 
1059 	for (i = 0; i < registernum; i++)
1060 		addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
1061 }
1062 
_rtl92c_phy_save_mac_registers(struct ieee80211_hw * hw,u32 * macreg,u32 * macbackup)1063 static void _rtl92c_phy_save_mac_registers(struct ieee80211_hw *hw,
1064 					   u32 *macreg, u32 *macbackup)
1065 {
1066 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1067 	u32 i;
1068 
1069 	for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1070 		macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1071 	macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1072 }
1073 
_rtl92c_phy_reload_adda_registers(struct ieee80211_hw * hw,u32 * addareg,u32 * addabackup,u32 regiesternum)1074 static void _rtl92c_phy_reload_adda_registers(struct ieee80211_hw *hw,
1075 					      u32 *addareg, u32 *addabackup,
1076 					      u32 regiesternum)
1077 {
1078 	u32 i;
1079 
1080 	for (i = 0; i < regiesternum; i++)
1081 		rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);
1082 }
1083 
_rtl92c_phy_reload_mac_registers(struct ieee80211_hw * hw,u32 * macreg,u32 * macbackup)1084 static void _rtl92c_phy_reload_mac_registers(struct ieee80211_hw *hw,
1085 					     u32 *macreg, u32 *macbackup)
1086 {
1087 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1088 	u32 i;
1089 
1090 	for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1091 		rtl_write_byte(rtlpriv, macreg[i], (u8)macbackup[i]);
1092 	rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
1093 }
1094 
_rtl92c_phy_path_adda_on(struct ieee80211_hw * hw,u32 * addareg,bool is_patha_on,bool is2t)1095 static void _rtl92c_phy_path_adda_on(struct ieee80211_hw *hw,
1096 				     u32 *addareg, bool is_patha_on, bool is2t)
1097 {
1098 	u32 pathon;
1099 	u32 i;
1100 
1101 	pathon = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
1102 	if (!is2t) {
1103 		pathon = 0x0bdb25a0;
1104 		rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);
1105 	} else {
1106 		rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon);
1107 	}
1108 
1109 	for (i = 1; i < IQK_ADDA_REG_NUM; i++)
1110 		rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon);
1111 }
1112 
_rtl92c_phy_mac_setting_calibration(struct ieee80211_hw * hw,u32 * macreg,u32 * macbackup)1113 static void _rtl92c_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1114 						u32 *macreg, u32 *macbackup)
1115 {
1116 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1117 	u32 i = 0;
1118 
1119 	rtl_write_byte(rtlpriv, macreg[i], 0x3F);
1120 
1121 	for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1122 		rtl_write_byte(rtlpriv, macreg[i],
1123 			       (u8)(macbackup[i] & (~BIT(3))));
1124 	rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] & (~BIT(5))));
1125 }
1126 
_rtl92c_phy_path_a_standby(struct ieee80211_hw * hw)1127 static void _rtl92c_phy_path_a_standby(struct ieee80211_hw *hw)
1128 {
1129 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1130 	rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1131 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1132 }
1133 
_rtl92c_phy_pi_mode_switch(struct ieee80211_hw * hw,bool pi_mode)1134 static void _rtl92c_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode)
1135 {
1136 	u32 mode;
1137 
1138 	mode = pi_mode ? 0x01000100 : 0x01000000;
1139 	rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1140 	rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1141 }
1142 
_rtl92c_phy_simularity_compare(struct ieee80211_hw * hw,long result[][8],u8 c1,u8 c2)1143 static bool _rtl92c_phy_simularity_compare(struct ieee80211_hw *hw,
1144 					   long result[][8], u8 c1, u8 c2)
1145 {
1146 	u32 i, j, diff, simularity_bitmap, bound;
1147 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1148 
1149 	u8 final_candidate[2] = { 0xFF, 0xFF };
1150 	bool bresult = true, is2t = IS_92C_SERIAL(rtlhal->version);
1151 
1152 	if (is2t)
1153 		bound = 8;
1154 	else
1155 		bound = 4;
1156 
1157 	simularity_bitmap = 0;
1158 
1159 	for (i = 0; i < bound; i++) {
1160 		diff = (result[c1][i] > result[c2][i]) ?
1161 		    (result[c1][i] - result[c2][i]) :
1162 		    (result[c2][i] - result[c1][i]);
1163 
1164 		if (diff > MAX_TOLERANCE) {
1165 			if ((i == 2 || i == 6) && !simularity_bitmap) {
1166 				if (result[c1][i] + result[c1][i + 1] == 0)
1167 					final_candidate[(i / 4)] = c2;
1168 				else if (result[c2][i] + result[c2][i + 1] == 0)
1169 					final_candidate[(i / 4)] = c1;
1170 				else
1171 					simularity_bitmap = simularity_bitmap |
1172 					    (1 << i);
1173 			} else
1174 				simularity_bitmap =
1175 				    simularity_bitmap | (1 << i);
1176 		}
1177 	}
1178 
1179 	if (simularity_bitmap == 0) {
1180 		for (i = 0; i < (bound / 4); i++) {
1181 			if (final_candidate[i] != 0xFF) {
1182 				for (j = i * 4; j < (i + 1) * 4 - 2; j++)
1183 					result[3][j] =
1184 					    result[final_candidate[i]][j];
1185 				bresult = false;
1186 			}
1187 		}
1188 		return bresult;
1189 	} else if (!(simularity_bitmap & 0x0F)) {
1190 		for (i = 0; i < 4; i++)
1191 			result[3][i] = result[c1][i];
1192 		return false;
1193 	} else if (!(simularity_bitmap & 0xF0) && is2t) {
1194 		for (i = 4; i < 8; i++)
1195 			result[3][i] = result[c1][i];
1196 		return false;
1197 	} else {
1198 		return false;
1199 	}
1200 }
1201 
_rtl92c_phy_iq_calibrate(struct ieee80211_hw * hw,long result[][8],u8 t,bool is2t)1202 static void _rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw,
1203 				     long result[][8], u8 t, bool is2t)
1204 {
1205 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1206 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1207 	u32 i;
1208 	u8 patha_ok, pathb_ok;
1209 	u32 adda_reg[IQK_ADDA_REG_NUM] = {
1210 		0x85c, 0xe6c, 0xe70, 0xe74,
1211 		0xe78, 0xe7c, 0xe80, 0xe84,
1212 		0xe88, 0xe8c, 0xed0, 0xed4,
1213 		0xed8, 0xedc, 0xee0, 0xeec
1214 	};
1215 	u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1216 		0x522, 0x550, 0x551, 0x040
1217 	};
1218 	const u32 retrycount = 2;
1219 
1220 	if (t == 0) {
1221 		rtl_get_bbreg(hw, 0x800, MASKDWORD);
1222 
1223 		_rtl92c_phy_save_adda_registers(hw, adda_reg,
1224 						rtlphy->adda_backup, 16);
1225 		_rtl92c_phy_save_mac_registers(hw, iqk_mac_reg,
1226 					       rtlphy->iqk_mac_backup);
1227 	}
1228 	_rtl92c_phy_path_adda_on(hw, adda_reg, true, is2t);
1229 	if (t == 0) {
1230 		rtlphy->rfpi_enable =
1231 		   (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
1232 				     BIT(8));
1233 	}
1234 
1235 	if (!rtlphy->rfpi_enable)
1236 		_rtl92c_phy_pi_mode_switch(hw, true);
1237 	if (t == 0) {
1238 		rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD);
1239 		rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD);
1240 		rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD);
1241 	}
1242 	rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);
1243 	rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);
1244 	rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);
1245 	if (is2t) {
1246 		rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1247 		rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000);
1248 	}
1249 	_rtl92c_phy_mac_setting_calibration(hw, iqk_mac_reg,
1250 					    rtlphy->iqk_mac_backup);
1251 	rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000);
1252 	if (is2t)
1253 		rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x00080000);
1254 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1255 	rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1256 	rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1257 	for (i = 0; i < retrycount; i++) {
1258 		patha_ok = _rtl92c_phy_path_a_iqk(hw, is2t);
1259 		if (patha_ok == 0x03) {
1260 			result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1261 					0x3FF0000) >> 16;
1262 			result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1263 					0x3FF0000) >> 16;
1264 			result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1265 					0x3FF0000) >> 16;
1266 			result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1267 					0x3FF0000) >> 16;
1268 			break;
1269 		} else if (i == (retrycount - 1) && patha_ok == 0x01)
1270 
1271 			result[t][0] = (rtl_get_bbreg(hw, 0xe94,
1272 						      MASKDWORD) & 0x3FF0000) >>
1273 			    16;
1274 		result[t][1] =
1275 		    (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 0x3FF0000) >> 16;
1276 
1277 	}
1278 
1279 	if (is2t) {
1280 		_rtl92c_phy_path_a_standby(hw);
1281 		_rtl92c_phy_path_adda_on(hw, adda_reg, false, is2t);
1282 		for (i = 0; i < retrycount; i++) {
1283 			pathb_ok = _rtl92c_phy_path_b_iqk(hw);
1284 			if (pathb_ok == 0x03) {
1285 				result[t][4] = (rtl_get_bbreg(hw,
1286 							      0xeb4,
1287 							      MASKDWORD) &
1288 						0x3FF0000) >> 16;
1289 				result[t][5] =
1290 				    (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1291 				     0x3FF0000) >> 16;
1292 				result[t][6] =
1293 				    (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
1294 				     0x3FF0000) >> 16;
1295 				result[t][7] =
1296 				    (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
1297 				     0x3FF0000) >> 16;
1298 				break;
1299 			} else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1300 				result[t][4] = (rtl_get_bbreg(hw,
1301 							      0xeb4,
1302 							      MASKDWORD) &
1303 						0x3FF0000) >> 16;
1304 			}
1305 			result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1306 					0x3FF0000) >> 16;
1307 		}
1308 	}
1309 	rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04);
1310 	rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874);
1311 	rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08);
1312 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1313 	rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3);
1314 	if (is2t)
1315 		rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3);
1316 	if (t != 0) {
1317 		if (!rtlphy->rfpi_enable)
1318 			_rtl92c_phy_pi_mode_switch(hw, false);
1319 		_rtl92c_phy_reload_adda_registers(hw, adda_reg,
1320 						  rtlphy->adda_backup, 16);
1321 		_rtl92c_phy_reload_mac_registers(hw, iqk_mac_reg,
1322 						 rtlphy->iqk_mac_backup);
1323 	}
1324 }
1325 
_rtl92c_phy_ap_calibrate(struct ieee80211_hw * hw,s8 delta,bool is2t)1326 static void _rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw,
1327 				     s8 delta, bool is2t)
1328 {
1329 }
1330 
_rtl92c_phy_set_rfpath_switch(struct ieee80211_hw * hw,bool bmain,bool is2t)1331 static void _rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw,
1332 					  bool bmain, bool is2t)
1333 {
1334 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1335 
1336 	if (is_hal_stop(rtlhal)) {
1337 		rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01);
1338 		rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1339 	}
1340 	if (is2t) {
1341 		if (bmain)
1342 			rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1343 				      BIT(5) | BIT(6), 0x1);
1344 		else
1345 			rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1346 				      BIT(5) | BIT(6), 0x2);
1347 	} else {
1348 		if (bmain)
1349 			rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x2);
1350 		else
1351 			rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1);
1352 	}
1353 }
1354 
1355 #undef IQK_ADDA_REG_NUM
1356 #undef IQK_DELAY_TIME
1357 
rtl92c_phy_iq_calibrate(struct ieee80211_hw * hw,bool b_recovery)1358 void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
1359 {
1360 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1361 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1362 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1363 
1364 	long result[4][8];
1365 	u8 i, final_candidate;
1366 	bool b_patha_ok, b_pathb_ok;
1367 	long reg_e94, reg_e9c, reg_ea4, reg_eb4, reg_ebc, reg_ec4,
1368 	    reg_tmp = 0;
1369 	bool is12simular, is13simular, is23simular;
1370 	u32 iqk_bb_reg[10] = {
1371 		ROFDM0_XARXIQIMBALANCE,
1372 		ROFDM0_XBRXIQIMBALANCE,
1373 		ROFDM0_ECCATHRESHOLD,
1374 		ROFDM0_AGCRSSITABLE,
1375 		ROFDM0_XATXIQIMBALANCE,
1376 		ROFDM0_XBTXIQIMBALANCE,
1377 		ROFDM0_XCTXIQIMBALANCE,
1378 		ROFDM0_XCTXAFE,
1379 		ROFDM0_XDTXAFE,
1380 		ROFDM0_RXIQEXTANTA
1381 	};
1382 
1383 	if (b_recovery) {
1384 		_rtl92c_phy_reload_adda_registers(hw,
1385 						  iqk_bb_reg,
1386 						  rtlphy->iqk_bb_backup, 10);
1387 		return;
1388 	}
1389 	for (i = 0; i < 8; i++) {
1390 		result[0][i] = 0;
1391 		result[1][i] = 0;
1392 		result[2][i] = 0;
1393 		result[3][i] = 0;
1394 	}
1395 	final_candidate = 0xff;
1396 	b_patha_ok = false;
1397 	b_pathb_ok = false;
1398 	is12simular = false;
1399 	is23simular = false;
1400 	is13simular = false;
1401 	for (i = 0; i < 3; i++) {
1402 		if (IS_92C_SERIAL(rtlhal->version))
1403 			_rtl92c_phy_iq_calibrate(hw, result, i, true);
1404 		else
1405 			_rtl92c_phy_iq_calibrate(hw, result, i, false);
1406 		if (i == 1) {
1407 			is12simular = _rtl92c_phy_simularity_compare(hw,
1408 								     result, 0,
1409 								     1);
1410 			if (is12simular) {
1411 				final_candidate = 0;
1412 				break;
1413 			}
1414 		}
1415 		if (i == 2) {
1416 			is13simular = _rtl92c_phy_simularity_compare(hw,
1417 								     result, 0,
1418 								     2);
1419 			if (is13simular) {
1420 				final_candidate = 0;
1421 				break;
1422 			}
1423 			is23simular = _rtl92c_phy_simularity_compare(hw,
1424 								     result, 1,
1425 								     2);
1426 			if (is23simular)
1427 				final_candidate = 1;
1428 			else {
1429 				for (i = 0; i < 8; i++)
1430 					reg_tmp += result[3][i];
1431 
1432 				if (reg_tmp != 0)
1433 					final_candidate = 3;
1434 				else
1435 					final_candidate = 0xFF;
1436 			}
1437 		}
1438 	}
1439 	for (i = 0; i < 4; i++) {
1440 		reg_e94 = result[i][0];
1441 		reg_e9c = result[i][1];
1442 		reg_ea4 = result[i][2];
1443 		reg_eb4 = result[i][4];
1444 		reg_ebc = result[i][5];
1445 		reg_ec4 = result[i][6];
1446 	}
1447 	if (final_candidate != 0xff) {
1448 		rtlphy->reg_e94 = reg_e94 = result[final_candidate][0];
1449 		rtlphy->reg_e9c = reg_e9c = result[final_candidate][1];
1450 		reg_ea4 = result[final_candidate][2];
1451 		rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4];
1452 		rtlphy->reg_ebc = reg_ebc = result[final_candidate][5];
1453 		reg_ec4 = result[final_candidate][6];
1454 		b_patha_ok = true;
1455 		b_pathb_ok = true;
1456 	} else {
1457 		rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100;
1458 		rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;
1459 	}
1460 	if (reg_e94 != 0) /*&&(reg_ea4 != 0) */
1461 		_rtl92c_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result,
1462 						   final_candidate,
1463 						   (reg_ea4 == 0));
1464 	if (IS_92C_SERIAL(rtlhal->version)) {
1465 		if (reg_eb4 != 0) /*&&(reg_ec4 != 0) */
1466 			_rtl92c_phy_path_b_fill_iqk_matrix(hw, b_pathb_ok,
1467 							   result,
1468 							   final_candidate,
1469 							   (reg_ec4 == 0));
1470 	}
1471 	_rtl92c_phy_save_adda_registers(hw, iqk_bb_reg,
1472 					rtlphy->iqk_bb_backup, 10);
1473 }
1474 EXPORT_SYMBOL(rtl92c_phy_iq_calibrate);
1475 
rtl92c_phy_lc_calibrate(struct ieee80211_hw * hw)1476 void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw)
1477 {
1478 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1479 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1480 
1481 	if (IS_92C_SERIAL(rtlhal->version))
1482 		rtlpriv->cfg->ops->phy_lc_calibrate(hw, true);
1483 	else
1484 		rtlpriv->cfg->ops->phy_lc_calibrate(hw, false);
1485 }
1486 EXPORT_SYMBOL(rtl92c_phy_lc_calibrate);
1487 
rtl92c_phy_ap_calibrate(struct ieee80211_hw * hw,s8 delta)1488 void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta)
1489 {
1490 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1491 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1492 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1493 
1494 	if (rtlphy->apk_done)
1495 		return;
1496 	if (IS_92C_SERIAL(rtlhal->version))
1497 		_rtl92c_phy_ap_calibrate(hw, delta, true);
1498 	else
1499 		_rtl92c_phy_ap_calibrate(hw, delta, false);
1500 }
1501 EXPORT_SYMBOL(rtl92c_phy_ap_calibrate);
1502 
rtl92c_phy_set_rfpath_switch(struct ieee80211_hw * hw,bool bmain)1503 void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
1504 {
1505 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1506 
1507 	if (IS_92C_SERIAL(rtlhal->version))
1508 		_rtl92c_phy_set_rfpath_switch(hw, bmain, true);
1509 	else
1510 		_rtl92c_phy_set_rfpath_switch(hw, bmain, false);
1511 }
1512 EXPORT_SYMBOL(rtl92c_phy_set_rfpath_switch);
1513 
rtl92c_phy_set_io_cmd(struct ieee80211_hw * hw,enum io_type iotype)1514 bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
1515 {
1516 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1517 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1518 	bool postprocessing = false;
1519 
1520 	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
1521 		"-->IO Cmd(%#x), set_io_inprogress(%d)\n",
1522 		iotype, rtlphy->set_io_inprogress);
1523 	do {
1524 		switch (iotype) {
1525 		case IO_CMD_RESUME_DM_BY_SCAN:
1526 			rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
1527 				"[IO CMD] Resume DM after scan.\n");
1528 			postprocessing = true;
1529 			break;
1530 		case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
1531 			rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
1532 				"[IO CMD] Pause DM before scan.\n");
1533 			postprocessing = true;
1534 			break;
1535 		default:
1536 			rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
1537 				"switch case %#x not processed\n", iotype);
1538 			break;
1539 		}
1540 	} while (false);
1541 	if (postprocessing && !rtlphy->set_io_inprogress) {
1542 		rtlphy->set_io_inprogress = true;
1543 		rtlphy->current_io_type = iotype;
1544 	} else {
1545 		return false;
1546 	}
1547 	rtl92c_phy_set_io(hw);
1548 	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype);
1549 	return true;
1550 }
1551 EXPORT_SYMBOL(rtl92c_phy_set_io_cmd);
1552 
rtl92c_phy_set_io(struct ieee80211_hw * hw)1553 void rtl92c_phy_set_io(struct ieee80211_hw *hw)
1554 {
1555 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1556 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1557 	struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
1558 
1559 	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
1560 		"--->Cmd(%#x), set_io_inprogress(%d)\n",
1561 		rtlphy->current_io_type, rtlphy->set_io_inprogress);
1562 	switch (rtlphy->current_io_type) {
1563 	case IO_CMD_RESUME_DM_BY_SCAN:
1564 		dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
1565 		rtl92c_dm_write_dig(hw);
1566 		rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
1567 		break;
1568 	case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
1569 		rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue;
1570 		dm_digtable->cur_igvalue = 0x17;
1571 		rtl92c_dm_write_dig(hw);
1572 		break;
1573 	default:
1574 		rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
1575 			"switch case %#x not processed\n",
1576 			rtlphy->current_io_type);
1577 		break;
1578 	}
1579 	rtlphy->set_io_inprogress = false;
1580 	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
1581 		"(%#x)\n", rtlphy->current_io_type);
1582 }
1583 EXPORT_SYMBOL(rtl92c_phy_set_io);
1584 
rtl92ce_phy_set_rf_on(struct ieee80211_hw * hw)1585 void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw)
1586 {
1587 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1588 
1589 	rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
1590 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1591 	rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
1592 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1593 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1594 	rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1595 }
1596 EXPORT_SYMBOL(rtl92ce_phy_set_rf_on);
1597 
_rtl92c_phy_set_rf_sleep(struct ieee80211_hw * hw)1598 void _rtl92c_phy_set_rf_sleep(struct ieee80211_hw *hw)
1599 {
1600 	u32 u4b_tmp;
1601 	u8 delay = 5;
1602 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1603 
1604 	rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1605 	rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1606 	rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1607 	u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
1608 	while (u4b_tmp != 0 && delay > 0) {
1609 		rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
1610 		rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1611 		rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1612 		u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
1613 		delay--;
1614 	}
1615 	if (delay == 0) {
1616 		rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
1617 		rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1618 		rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1619 		rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1620 		rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
1621 			"Switch RF timeout !!!.\n");
1622 		return;
1623 	}
1624 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1625 	rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
1626 }
1627 EXPORT_SYMBOL(_rtl92c_phy_set_rf_sleep);
1628