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/linux-6.6.21/drivers/clk/bcm/
Dclk-kona.h91 #define POLICY(_offset, _bit) \ argument
151 #define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
163 #define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
174 #define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
185 #define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \ argument
195 #define HW_ONLY_GATE(_offset, _status_bit) \ argument
211 #define HYST(_offset, _en_bit, _val_bit) \ argument
291 #define DIVIDER(_offset, _shift, _width) \ argument
301 #define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \ argument
342 #define SELECTOR(_offset, _shift, _width) \ argument
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/linux-6.6.21/drivers/net/ethernet/mellanox/mlxsw/
Ditem.h266 #define MLXSW_ITEM8(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
284 #define MLXSW_ITEM8_INDEXED(_type, _cname, _iname, _offset, _shift, _sizebits, \ argument
309 #define MLXSW_ITEM16(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
327 #define MLXSW_ITEM16_INDEXED(_type, _cname, _iname, _offset, _shift, _sizebits, \ argument
352 #define MLXSW_ITEM32(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
406 #define MLXSW_ITEM32_INDEXED(_type, _cname, _iname, _offset, _shift, _sizebits, \ argument
431 #define MLXSW_ITEM64(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
449 #define MLXSW_ITEM64_INDEXED(_type, _cname, _iname, _offset, _shift, \ argument
474 #define MLXSW_ITEM_BUF(_type, _cname, _iname, _offset, _sizebytes) \ argument
498 #define MLXSW_ITEM_BUF_INDEXED(_type, _cname, _iname, _offset, _sizebytes, \ argument
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Dcore_acl_flex_keys.h54 #define MLXSW_AFK_ELEMENT_INFO(_type, _element, _offset, _shift, _size) \ argument
66 #define MLXSW_AFK_ELEMENT_INFO_U32(_element, _offset, _shift, _size) \ argument
70 #define MLXSW_AFK_ELEMENT_INFO_BUF(_element, _offset, _size) \ argument
86 #define MLXSW_AFK_ELEMENT_INST(_type, _element, _offset, \ argument
101 #define MLXSW_AFK_ELEMENT_INST_U32(_element, _offset, _shift, _size) \ argument
105 #define MLXSW_AFK_ELEMENT_INST_EXT_U32(_element, _offset, \ argument
112 #define MLXSW_AFK_ELEMENT_INST_BUF(_element, _offset, _size) \ argument
Dspectrum_acl.c531 #define MLXSW_SP_ACL_MANGLE_ACTION(_htype, _offset, _mask, _shift, _field) \ argument
540 #define MLXSW_SP_ACL_MANGLE_ACTION_IP4(_offset, _mask, _shift, _field) \ argument
544 #define MLXSW_SP_ACL_MANGLE_ACTION_IP6(_offset, _mask, _shift, _field) \ argument
548 #define MLXSW_SP_ACL_MANGLE_ACTION_TCP(_offset, _mask, _shift, _field) \ argument
551 #define MLXSW_SP_ACL_MANGLE_ACTION_UDP(_offset, _mask, _shift, _field) \ argument
/linux-6.6.21/drivers/clk/tegra/
Dclk-tegra-periph.c132 #define MUX(_name, _parents, _offset, \ argument
139 #define MUX_FLAGS(_name, _parents, _offset,\ argument
146 #define MUX8(_name, _parents, _offset, \ argument
153 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \ argument
159 #define MUX8_NOGATE(_name, _parents, _offset, _clk_id) \ argument
165 #define INT(_name, _parents, _offset, \ argument
172 #define INT_FLAGS(_name, _parents, _offset,\ argument
179 #define INT8(_name, _parents, _offset,\ argument
186 #define UART(_name, _parents, _offset,\ argument
193 #define UART8(_name, _parents, _offset,\ argument
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Dclk-tegra-audio.c52 #define AUDIO(_name, _offset) \ argument
71 #define AUDIO2X(_name, _num, _offset) \ argument
Dclk-tegra30.c157 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \ argument
163 #define TEGRA_INIT_DATA_MUX8(_name, _parents, _offset, \ argument
169 #define TEGRA_INIT_DATA_INT(_name, _parents, _offset, \ argument
176 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \ argument
Dclk-tegra20.c135 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \ argument
142 #define TEGRA_INIT_DATA_DIV16(_name, _parents, _offset, \ argument
149 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \ argument
/linux-6.6.21/drivers/clk/mediatek/
Dclk-mt6795-apmixedsys.c76 #define _FH(_pllid, _fhid, _slope, _offset) { \ argument
99 #define FH(_pllid, _fhid, _offset) _FH(_pllid, _fhid, 0x6003c97, _offset) argument
100 #define FH_M(_pllid, _fhid, _offset) _FH(_pllid, _fhid, 0x6000140, _offset) argument
/linux-6.6.21/drivers/clk/renesas/
Drcar-gen4-cpg.h36 #define DEF_GEN4_SDH(_name, _id, _parent, _offset) \ argument
39 #define DEF_GEN4_SD(_name, _id, _parent, _offset) \ argument
50 #define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset) \ argument
Drcar-gen3-cpg.h37 #define DEF_GEN3_SDH(_name, _id, _parent, _offset) \ argument
40 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ argument
60 #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ argument
Drenesas-cpg-mssr.h53 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
55 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ argument
Dr8a779a0-cpg-mssr.c60 #define DEF_PLL(_name, _id, _offset) \ argument
/linux-6.6.21/drivers/bcma/
Dsprom.c185 #define SPEX(_field, _offset, _mask, _shift) \ argument
188 #define SPEX32(_field, _offset, _mask, _shift) \ argument
192 #define SPEX_ARRAY8(_field, _offset, _mask, _shift) \ argument
/linux-6.6.21/drivers/clk/sunxi-ng/
Dccu_mult.h17 #define _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, _min, _max) \ argument
29 #define _SUNXI_CCU_MULT_OFFSET(_shift, _width, _offset) \ argument
/linux-6.6.21/drivers/ssb/
Dpci.c171 #define SPEX16(_outvar, _offset, _mask, _shift) \ argument
173 #define SPEX32(_outvar, _offset, _mask, _shift) \ argument
176 #define SPEX(_outvar, _offset, _mask, _shift) \ argument
179 #define SPEX_ARRAY8(_field, _offset, _mask, _shift) \ argument
/linux-6.6.21/drivers/clk/stm32/
Dclk-stm32mp13.c138 #define _CFG_GATE(_id, _offset, _bit_idx, _offset_clr)\ argument
145 #define CFG_GATE(_id, _offset, _bit_idx)\ argument
148 #define CFG_GATE_SETCLR(_id, _offset, _bit_idx)\ argument
288 #define CFG_DIV(_id, _offset, _shift, _width, _flags, _table, _ready)\ argument
350 #define _CFG_MUX(_id, _offset, _shift, _witdh, _ready, _flags)\ argument
359 #define CFG_MUX(_id, _offset, _shift, _witdh)\ argument
362 #define CFG_MUX_SAFE(_id, _offset, _shift, _witdh)\ argument
469 #define SECF(_sec_id, _offset, _bit_idx)[_sec_id] = {\ argument
/linux-6.6.21/drivers/clk/
Dclk-loongson1.c153 #define LS1X_CLK_PLL(_name, _offset, _fixed, _shift, \ argument
177 #define LS1X_CLK_DIV(_name, _pname, _offset, _shift, _width, \ argument
Dclk-stm32mp1.c1166 #define GATE(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\ argument
1193 #define DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\ argument
1210 #define DIV(_id, _name, _parent, _flags, _offset, _shift, _width, _div_flags)\ argument
1214 #define MUX(_id, _name, _parents, _flags, _offset, _shift, _width, _mux_flags)\ argument
1307 #define GATE_MP1(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\ argument
1340 #define _STM32_MUX(_offset, _shift, _width, _mux_flags, _mmux, _ops)\ argument
1353 #define _MUX(_offset, _shift, _width, _mux_flags)\ argument
1694 #define _K_MUX(_id, _offset, _shift, _width, _mux_flags, _mmux, _ops)\ argument
1707 #define K_MUX(_id, _offset, _shift, _width, _mux_flags)\ argument
1711 #define K_MMUX(_id, _offset, _shift, _width, _mux_flags)\ argument
/linux-6.6.21/drivers/clk/st/
Dclkgen.h38 #define CLKGEN_FIELD(_offset, _mask, _shift) { \ argument
/linux-6.6.21/net/rxrpc/
Dinsecure.c21 size_t *_buf_size, size_t *_data_size, size_t *_offset) in none_how_much_data()
/linux-6.6.21/drivers/clk/microchip/
Dclk-mpfs-ccc.c101 #define CLK_CCC_PLL(_id, _parents, _shift, _width, _flags, _offset) { \ argument
124 #define CLK_CCC_OUT(_id, _shift, _width, _flags, _offset) { \ argument
/linux-6.6.21/drivers/pinctrl/mediatek/
Dpinctrl-mt2701.c30 #define MTK_PINMUX_SPEC(_pin, _offset, _bit) \ argument
Dpinctrl-mtk-common.h109 #define MTK_PIN_DRV_GRP(_pin, _offset, _bit, _grp) \ argument
134 #define MTK_PIN_PUPD_SPEC_SR(_pin, _offset, _pupd, _r1, _r0) \ argument
157 #define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \ argument
/linux-6.6.21/drivers/pinctrl/berlin/
Dberlin.h37 #define BERLIN_PINCTRL_GROUP(_name, _offset, _width, _lsb, ...) \ argument

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