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Searched defs:_clk (Results 1 – 6 of 6) sorted by relevance

/linux-5.19.10/drivers/clk/stm32/
Dclk-stm32-core.h166 #define STM32_CLOCK_CFG(_binding, _clk, _sec_id, _struct, _register)\ argument
174 #define STM32_MUX_CFG(_binding, _clk, _sec_id)\ argument
178 #define STM32_GATE_CFG(_binding, _clk, _sec_id)\ argument
182 #define STM32_DIV_CFG(_binding, _clk, _sec_id)\ argument
186 #define STM32_COMPOSITE_CFG(_binding, _clk, _sec_id)\ argument
/linux-5.19.10/include/linux/
Dsh_clk.h200 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } argument
201 #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk } argument
202 #define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk } argument
/linux-5.19.10/arch/arm/mach-omap2/
Domap_hwmod.h181 struct clk *_clk; member
244 struct clk *_clk; member
585 struct clk *_clk; member
/linux-5.19.10/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dgm20b.c852 struct gm20b_clk *_clk = gm20b_clk(base); in gm20b_clk_init() local
/linux-5.19.10/drivers/clk/renesas/
Dr9a06g032-clocks.c64 #define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) \ argument
/linux-5.19.10/drivers/ufs/host/
Dufs-exynos.c503 unsigned long clk = 0, _clk, clk_period; in exynos_ufs_calc_pwm_clk_div() local