1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #include <linux/vmalloc.h>
6
7 #include "coex.h"
8 #include "debug.h"
9 #include "fw.h"
10 #include "mac.h"
11 #include "ps.h"
12 #include "reg.h"
13 #include "sar.h"
14
15 #ifdef CONFIG_RTW89_DEBUGMSG
16 unsigned int rtw89_debug_mask;
17 EXPORT_SYMBOL(rtw89_debug_mask);
18 module_param_named(debug_mask, rtw89_debug_mask, uint, 0644);
19 MODULE_PARM_DESC(debug_mask, "Debugging mask");
20 #endif
21
22 #ifdef CONFIG_RTW89_DEBUGFS
23 struct rtw89_debugfs_priv {
24 struct rtw89_dev *rtwdev;
25 int (*cb_read)(struct seq_file *m, void *v);
26 ssize_t (*cb_write)(struct file *filp, const char __user *buffer,
27 size_t count, loff_t *loff);
28 union {
29 u32 cb_data;
30 struct {
31 u32 addr;
32 u8 len;
33 } read_reg;
34 struct {
35 u32 addr;
36 u32 mask;
37 u8 path;
38 } read_rf;
39 struct {
40 u8 ss_dbg:1;
41 u8 dle_dbg:1;
42 u8 dmac_dbg:1;
43 u8 cmac_dbg:1;
44 u8 dbg_port:1;
45 } dbgpkg_en;
46 struct {
47 u32 start;
48 u32 len;
49 u8 sel;
50 } mac_mem;
51 };
52 };
53
rtw89_debugfs_single_show(struct seq_file * m,void * v)54 static int rtw89_debugfs_single_show(struct seq_file *m, void *v)
55 {
56 struct rtw89_debugfs_priv *debugfs_priv = m->private;
57
58 return debugfs_priv->cb_read(m, v);
59 }
60
rtw89_debugfs_single_write(struct file * filp,const char __user * buffer,size_t count,loff_t * loff)61 static ssize_t rtw89_debugfs_single_write(struct file *filp,
62 const char __user *buffer,
63 size_t count, loff_t *loff)
64 {
65 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
66
67 return debugfs_priv->cb_write(filp, buffer, count, loff);
68 }
69
rtw89_debugfs_seq_file_write(struct file * filp,const char __user * buffer,size_t count,loff_t * loff)70 static ssize_t rtw89_debugfs_seq_file_write(struct file *filp,
71 const char __user *buffer,
72 size_t count, loff_t *loff)
73 {
74 struct seq_file *seqpriv = (struct seq_file *)filp->private_data;
75 struct rtw89_debugfs_priv *debugfs_priv = seqpriv->private;
76
77 return debugfs_priv->cb_write(filp, buffer, count, loff);
78 }
79
rtw89_debugfs_single_open(struct inode * inode,struct file * filp)80 static int rtw89_debugfs_single_open(struct inode *inode, struct file *filp)
81 {
82 return single_open(filp, rtw89_debugfs_single_show, inode->i_private);
83 }
84
rtw89_debugfs_close(struct inode * inode,struct file * filp)85 static int rtw89_debugfs_close(struct inode *inode, struct file *filp)
86 {
87 return 0;
88 }
89
90 static const struct file_operations file_ops_single_r = {
91 .owner = THIS_MODULE,
92 .open = rtw89_debugfs_single_open,
93 .read = seq_read,
94 .llseek = seq_lseek,
95 .release = single_release,
96 };
97
98 static const struct file_operations file_ops_common_rw = {
99 .owner = THIS_MODULE,
100 .open = rtw89_debugfs_single_open,
101 .release = single_release,
102 .read = seq_read,
103 .llseek = seq_lseek,
104 .write = rtw89_debugfs_seq_file_write,
105 };
106
107 static const struct file_operations file_ops_single_w = {
108 .owner = THIS_MODULE,
109 .write = rtw89_debugfs_single_write,
110 .open = simple_open,
111 .release = rtw89_debugfs_close,
112 };
113
114 static ssize_t
rtw89_debug_priv_read_reg_select(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)115 rtw89_debug_priv_read_reg_select(struct file *filp,
116 const char __user *user_buf,
117 size_t count, loff_t *loff)
118 {
119 struct seq_file *m = (struct seq_file *)filp->private_data;
120 struct rtw89_debugfs_priv *debugfs_priv = m->private;
121 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
122 char buf[32];
123 size_t buf_size;
124 u32 addr, len;
125 int num;
126
127 buf_size = min(count, sizeof(buf) - 1);
128 if (copy_from_user(buf, user_buf, buf_size))
129 return -EFAULT;
130
131 buf[buf_size] = '\0';
132 num = sscanf(buf, "%x %x", &addr, &len);
133 if (num != 2) {
134 rtw89_info(rtwdev, "invalid format: <addr> <len>\n");
135 return -EINVAL;
136 }
137
138 debugfs_priv->read_reg.addr = addr;
139 debugfs_priv->read_reg.len = len;
140
141 rtw89_info(rtwdev, "select read %d bytes from 0x%08x\n", len, addr);
142
143 return count;
144 }
145
rtw89_debug_priv_read_reg_get(struct seq_file * m,void * v)146 static int rtw89_debug_priv_read_reg_get(struct seq_file *m, void *v)
147 {
148 struct rtw89_debugfs_priv *debugfs_priv = m->private;
149 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
150 u32 addr, data;
151 u8 len;
152
153 len = debugfs_priv->read_reg.len;
154 addr = debugfs_priv->read_reg.addr;
155
156 switch (len) {
157 case 1:
158 data = rtw89_read8(rtwdev, addr);
159 break;
160 case 2:
161 data = rtw89_read16(rtwdev, addr);
162 break;
163 case 4:
164 data = rtw89_read32(rtwdev, addr);
165 break;
166 default:
167 rtw89_info(rtwdev, "invalid read reg len %d\n", len);
168 return -EINVAL;
169 }
170
171 seq_printf(m, "get %d bytes at 0x%08x=0x%08x\n", len, addr, data);
172
173 return 0;
174 }
175
rtw89_debug_priv_write_reg_set(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)176 static ssize_t rtw89_debug_priv_write_reg_set(struct file *filp,
177 const char __user *user_buf,
178 size_t count, loff_t *loff)
179 {
180 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
181 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
182 char buf[32];
183 size_t buf_size;
184 u32 addr, val, len;
185 int num;
186
187 buf_size = min(count, sizeof(buf) - 1);
188 if (copy_from_user(buf, user_buf, buf_size))
189 return -EFAULT;
190
191 buf[buf_size] = '\0';
192 num = sscanf(buf, "%x %x %x", &addr, &val, &len);
193 if (num != 3) {
194 rtw89_info(rtwdev, "invalid format: <addr> <val> <len>\n");
195 return -EINVAL;
196 }
197
198 switch (len) {
199 case 1:
200 rtw89_info(rtwdev, "reg write8 0x%08x: 0x%02x\n", addr, val);
201 rtw89_write8(rtwdev, addr, (u8)val);
202 break;
203 case 2:
204 rtw89_info(rtwdev, "reg write16 0x%08x: 0x%04x\n", addr, val);
205 rtw89_write16(rtwdev, addr, (u16)val);
206 break;
207 case 4:
208 rtw89_info(rtwdev, "reg write32 0x%08x: 0x%08x\n", addr, val);
209 rtw89_write32(rtwdev, addr, (u32)val);
210 break;
211 default:
212 rtw89_info(rtwdev, "invalid read write len %d\n", len);
213 break;
214 }
215
216 return count;
217 }
218
219 static ssize_t
rtw89_debug_priv_read_rf_select(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)220 rtw89_debug_priv_read_rf_select(struct file *filp,
221 const char __user *user_buf,
222 size_t count, loff_t *loff)
223 {
224 struct seq_file *m = (struct seq_file *)filp->private_data;
225 struct rtw89_debugfs_priv *debugfs_priv = m->private;
226 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
227 char buf[32];
228 size_t buf_size;
229 u32 addr, mask;
230 u8 path;
231 int num;
232
233 buf_size = min(count, sizeof(buf) - 1);
234 if (copy_from_user(buf, user_buf, buf_size))
235 return -EFAULT;
236
237 buf[buf_size] = '\0';
238 num = sscanf(buf, "%hhd %x %x", &path, &addr, &mask);
239 if (num != 3) {
240 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask>\n");
241 return -EINVAL;
242 }
243
244 if (path >= rtwdev->chip->rf_path_num) {
245 rtw89_info(rtwdev, "wrong rf path\n");
246 return -EINVAL;
247 }
248 debugfs_priv->read_rf.addr = addr;
249 debugfs_priv->read_rf.mask = mask;
250 debugfs_priv->read_rf.path = path;
251
252 rtw89_info(rtwdev, "select read rf path %d from 0x%08x\n", path, addr);
253
254 return count;
255 }
256
rtw89_debug_priv_read_rf_get(struct seq_file * m,void * v)257 static int rtw89_debug_priv_read_rf_get(struct seq_file *m, void *v)
258 {
259 struct rtw89_debugfs_priv *debugfs_priv = m->private;
260 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
261 u32 addr, data, mask;
262 u8 path;
263
264 addr = debugfs_priv->read_rf.addr;
265 mask = debugfs_priv->read_rf.mask;
266 path = debugfs_priv->read_rf.path;
267
268 data = rtw89_read_rf(rtwdev, path, addr, mask);
269
270 seq_printf(m, "path %d, rf register 0x%08x=0x%08x\n", path, addr, data);
271
272 return 0;
273 }
274
rtw89_debug_priv_write_rf_set(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)275 static ssize_t rtw89_debug_priv_write_rf_set(struct file *filp,
276 const char __user *user_buf,
277 size_t count, loff_t *loff)
278 {
279 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
280 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
281 char buf[32];
282 size_t buf_size;
283 u32 addr, val, mask;
284 u8 path;
285 int num;
286
287 buf_size = min(count, sizeof(buf) - 1);
288 if (copy_from_user(buf, user_buf, buf_size))
289 return -EFAULT;
290
291 buf[buf_size] = '\0';
292 num = sscanf(buf, "%hhd %x %x %x", &path, &addr, &mask, &val);
293 if (num != 4) {
294 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask> <val>\n");
295 return -EINVAL;
296 }
297
298 if (path >= rtwdev->chip->rf_path_num) {
299 rtw89_info(rtwdev, "wrong rf path\n");
300 return -EINVAL;
301 }
302
303 rtw89_info(rtwdev, "path %d, rf register write 0x%08x=0x%08x (mask = 0x%08x)\n",
304 path, addr, val, mask);
305 rtw89_write_rf(rtwdev, path, addr, mask, val);
306
307 return count;
308 }
309
rtw89_debug_priv_rf_reg_dump_get(struct seq_file * m,void * v)310 static int rtw89_debug_priv_rf_reg_dump_get(struct seq_file *m, void *v)
311 {
312 struct rtw89_debugfs_priv *debugfs_priv = m->private;
313 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
314 const struct rtw89_chip_info *chip = rtwdev->chip;
315 u32 addr, offset, data;
316 u8 path;
317
318 for (path = 0; path < chip->rf_path_num; path++) {
319 seq_printf(m, "RF path %d:\n\n", path);
320 for (addr = 0; addr < 0x100; addr += 4) {
321 seq_printf(m, "0x%08x: ", addr);
322 for (offset = 0; offset < 4; offset++) {
323 data = rtw89_read_rf(rtwdev, path,
324 addr + offset, RFREG_MASK);
325 seq_printf(m, "0x%05x ", data);
326 }
327 seq_puts(m, "\n");
328 }
329 seq_puts(m, "\n");
330 }
331
332 return 0;
333 }
334
335 struct txpwr_ent {
336 const char *txt;
337 u8 len;
338 };
339
340 struct txpwr_map {
341 const struct txpwr_ent *ent;
342 u8 size;
343 u32 addr_from;
344 u32 addr_to;
345 };
346
347 #define __GEN_TXPWR_ENT2(_t, _e0, _e1) \
348 { .len = 2, .txt = _t "\t- " _e0 " " _e1 }
349
350 #define __GEN_TXPWR_ENT4(_t, _e0, _e1, _e2, _e3) \
351 { .len = 4, .txt = _t "\t- " _e0 " " _e1 " " _e2 " " _e3 }
352
353 #define __GEN_TXPWR_ENT8(_t, _e0, _e1, _e2, _e3, _e4, _e5, _e6, _e7) \
354 { .len = 8, .txt = _t "\t- " \
355 _e0 " " _e1 " " _e2 " " _e3 " " \
356 _e4 " " _e5 " " _e6 " " _e7 }
357
358 static const struct txpwr_ent __txpwr_ent_byr[] = {
359 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "),
360 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "),
361 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "),
362 /* 1NSS */
363 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "),
364 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "),
365 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"),
366 __GEN_TXPWR_ENT4("HEDCM_1NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "),
367 /* 2NSS */
368 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "),
369 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "),
370 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"),
371 __GEN_TXPWR_ENT4("HEDCM_2NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "),
372 };
373
374 static_assert((ARRAY_SIZE(__txpwr_ent_byr) * 4) ==
375 (R_AX_PWR_BY_RATE_MAX - R_AX_PWR_BY_RATE + 4));
376
377 static const struct txpwr_map __txpwr_map_byr = {
378 .ent = __txpwr_ent_byr,
379 .size = ARRAY_SIZE(__txpwr_ent_byr),
380 .addr_from = R_AX_PWR_BY_RATE,
381 .addr_to = R_AX_PWR_BY_RATE_MAX,
382 };
383
384 static const struct txpwr_ent __txpwr_ent_lmt[] = {
385 /* 1TX */
386 __GEN_TXPWR_ENT2("CCK_1TX_20M ", "NON_BF", "BF"),
387 __GEN_TXPWR_ENT2("CCK_1TX_40M ", "NON_BF", "BF"),
388 __GEN_TXPWR_ENT2("OFDM_1TX ", "NON_BF", "BF"),
389 __GEN_TXPWR_ENT2("MCS_1TX_20M_0 ", "NON_BF", "BF"),
390 __GEN_TXPWR_ENT2("MCS_1TX_20M_1 ", "NON_BF", "BF"),
391 __GEN_TXPWR_ENT2("MCS_1TX_20M_2 ", "NON_BF", "BF"),
392 __GEN_TXPWR_ENT2("MCS_1TX_20M_3 ", "NON_BF", "BF"),
393 __GEN_TXPWR_ENT2("MCS_1TX_20M_4 ", "NON_BF", "BF"),
394 __GEN_TXPWR_ENT2("MCS_1TX_20M_5 ", "NON_BF", "BF"),
395 __GEN_TXPWR_ENT2("MCS_1TX_20M_6 ", "NON_BF", "BF"),
396 __GEN_TXPWR_ENT2("MCS_1TX_20M_7 ", "NON_BF", "BF"),
397 __GEN_TXPWR_ENT2("MCS_1TX_40M_0 ", "NON_BF", "BF"),
398 __GEN_TXPWR_ENT2("MCS_1TX_40M_1 ", "NON_BF", "BF"),
399 __GEN_TXPWR_ENT2("MCS_1TX_40M_2 ", "NON_BF", "BF"),
400 __GEN_TXPWR_ENT2("MCS_1TX_40M_3 ", "NON_BF", "BF"),
401 __GEN_TXPWR_ENT2("MCS_1TX_80M_0 ", "NON_BF", "BF"),
402 __GEN_TXPWR_ENT2("MCS_1TX_80M_1 ", "NON_BF", "BF"),
403 __GEN_TXPWR_ENT2("MCS_1TX_160M ", "NON_BF", "BF"),
404 __GEN_TXPWR_ENT2("MCS_1TX_40M_0p5", "NON_BF", "BF"),
405 __GEN_TXPWR_ENT2("MCS_1TX_40M_2p5", "NON_BF", "BF"),
406 /* 2TX */
407 __GEN_TXPWR_ENT2("CCK_2TX_20M ", "NON_BF", "BF"),
408 __GEN_TXPWR_ENT2("CCK_2TX_40M ", "NON_BF", "BF"),
409 __GEN_TXPWR_ENT2("OFDM_2TX ", "NON_BF", "BF"),
410 __GEN_TXPWR_ENT2("MCS_2TX_20M_0 ", "NON_BF", "BF"),
411 __GEN_TXPWR_ENT2("MCS_2TX_20M_1 ", "NON_BF", "BF"),
412 __GEN_TXPWR_ENT2("MCS_2TX_20M_2 ", "NON_BF", "BF"),
413 __GEN_TXPWR_ENT2("MCS_2TX_20M_3 ", "NON_BF", "BF"),
414 __GEN_TXPWR_ENT2("MCS_2TX_20M_4 ", "NON_BF", "BF"),
415 __GEN_TXPWR_ENT2("MCS_2TX_20M_5 ", "NON_BF", "BF"),
416 __GEN_TXPWR_ENT2("MCS_2TX_20M_6 ", "NON_BF", "BF"),
417 __GEN_TXPWR_ENT2("MCS_2TX_20M_7 ", "NON_BF", "BF"),
418 __GEN_TXPWR_ENT2("MCS_2TX_40M_0 ", "NON_BF", "BF"),
419 __GEN_TXPWR_ENT2("MCS_2TX_40M_1 ", "NON_BF", "BF"),
420 __GEN_TXPWR_ENT2("MCS_2TX_40M_2 ", "NON_BF", "BF"),
421 __GEN_TXPWR_ENT2("MCS_2TX_40M_3 ", "NON_BF", "BF"),
422 __GEN_TXPWR_ENT2("MCS_2TX_80M_0 ", "NON_BF", "BF"),
423 __GEN_TXPWR_ENT2("MCS_2TX_80M_1 ", "NON_BF", "BF"),
424 __GEN_TXPWR_ENT2("MCS_2TX_160M ", "NON_BF", "BF"),
425 __GEN_TXPWR_ENT2("MCS_2TX_40M_0p5", "NON_BF", "BF"),
426 __GEN_TXPWR_ENT2("MCS_2TX_40M_2p5", "NON_BF", "BF"),
427 };
428
429 static_assert((ARRAY_SIZE(__txpwr_ent_lmt) * 2) ==
430 (R_AX_PWR_LMT_MAX - R_AX_PWR_LMT + 4));
431
432 static const struct txpwr_map __txpwr_map_lmt = {
433 .ent = __txpwr_ent_lmt,
434 .size = ARRAY_SIZE(__txpwr_ent_lmt),
435 .addr_from = R_AX_PWR_LMT,
436 .addr_to = R_AX_PWR_LMT_MAX,
437 };
438
439 static const struct txpwr_ent __txpwr_ent_lmt_ru[] = {
440 /* 1TX */
441 __GEN_TXPWR_ENT8("1TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3",
442 "RU26__4", "RU26__5", "RU26__6", "RU26__7"),
443 __GEN_TXPWR_ENT8("1TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3",
444 "RU52__4", "RU52__5", "RU52__6", "RU52__7"),
445 __GEN_TXPWR_ENT8("1TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3",
446 "RU106_4", "RU106_5", "RU106_6", "RU106_7"),
447 /* 2TX */
448 __GEN_TXPWR_ENT8("2TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3",
449 "RU26__4", "RU26__5", "RU26__6", "RU26__7"),
450 __GEN_TXPWR_ENT8("2TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3",
451 "RU52__4", "RU52__5", "RU52__6", "RU52__7"),
452 __GEN_TXPWR_ENT8("2TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3",
453 "RU106_4", "RU106_5", "RU106_6", "RU106_7"),
454 };
455
456 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru) * 8) ==
457 (R_AX_PWR_RU_LMT_MAX - R_AX_PWR_RU_LMT + 4));
458
459 static const struct txpwr_map __txpwr_map_lmt_ru = {
460 .ent = __txpwr_ent_lmt_ru,
461 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru),
462 .addr_from = R_AX_PWR_RU_LMT,
463 .addr_to = R_AX_PWR_RU_LMT_MAX,
464 };
465
__print_txpwr_ent(struct seq_file * m,const struct txpwr_ent * ent,const u8 * buf,const u8 cur)466 static u8 __print_txpwr_ent(struct seq_file *m, const struct txpwr_ent *ent,
467 const u8 *buf, const u8 cur)
468 {
469 char *fmt;
470
471 switch (ent->len) {
472 case 2:
473 fmt = "%s\t| %3d, %3d,\tdBm\n";
474 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1]);
475 return 2;
476 case 4:
477 fmt = "%s\t| %3d, %3d, %3d, %3d,\tdBm\n";
478 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1],
479 buf[cur + 2], buf[cur + 3]);
480 return 4;
481 case 8:
482 fmt = "%s\t| %3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d,\tdBm\n";
483 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1],
484 buf[cur + 2], buf[cur + 3], buf[cur + 4],
485 buf[cur + 5], buf[cur + 6], buf[cur + 7]);
486 return 8;
487 default:
488 return 0;
489 }
490 }
491
__print_txpwr_map(struct seq_file * m,struct rtw89_dev * rtwdev,const struct txpwr_map * map)492 static int __print_txpwr_map(struct seq_file *m, struct rtw89_dev *rtwdev,
493 const struct txpwr_map *map)
494 {
495 u8 fct = rtwdev->chip->txpwr_factor_mac;
496 u8 *buf, cur, i;
497 u32 val, addr;
498 int ret;
499
500 buf = vzalloc(map->addr_to - map->addr_from + 4);
501 if (!buf)
502 return -ENOMEM;
503
504 for (addr = map->addr_from; addr <= map->addr_to; addr += 4) {
505 ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val);
506 if (ret)
507 val = MASKDWORD;
508
509 cur = addr - map->addr_from;
510 for (i = 0; i < 4; i++, val >>= 8)
511 buf[cur + i] = FIELD_GET(MASKBYTE0, val) >> fct;
512 }
513
514 for (cur = 0, i = 0; i < map->size; i++)
515 cur += __print_txpwr_ent(m, &map->ent[i], buf, cur);
516
517 vfree(buf);
518 return 0;
519 }
520
521 #define case_REGD(_regd) \
522 case RTW89_ ## _regd: \
523 seq_puts(m, #_regd "\n"); \
524 break
525
__print_regd(struct seq_file * m,struct rtw89_dev * rtwdev)526 static void __print_regd(struct seq_file *m, struct rtw89_dev *rtwdev)
527 {
528 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
529 u8 band = chan->band_type;
530 u8 regd = rtw89_regd_get(rtwdev, band);
531
532 switch (regd) {
533 default:
534 seq_printf(m, "UNKNOWN: %d\n", regd);
535 break;
536 case_REGD(WW);
537 case_REGD(ETSI);
538 case_REGD(FCC);
539 case_REGD(MKK);
540 case_REGD(NA);
541 case_REGD(IC);
542 case_REGD(KCC);
543 case_REGD(NCC);
544 case_REGD(CHILE);
545 case_REGD(ACMA);
546 case_REGD(MEXICO);
547 case_REGD(UKRAINE);
548 case_REGD(CN);
549 }
550 }
551
552 #undef case_REGD
553
rtw89_debug_priv_txpwr_table_get(struct seq_file * m,void * v)554 static int rtw89_debug_priv_txpwr_table_get(struct seq_file *m, void *v)
555 {
556 struct rtw89_debugfs_priv *debugfs_priv = m->private;
557 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
558 int ret = 0;
559
560 mutex_lock(&rtwdev->mutex);
561 rtw89_leave_ps_mode(rtwdev);
562
563 seq_puts(m, "[Regulatory] ");
564 __print_regd(m, rtwdev);
565
566 seq_puts(m, "[SAR]\n");
567 rtw89_print_sar(m, rtwdev);
568
569 seq_puts(m, "\n[TX power byrate]\n");
570 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_byr);
571 if (ret)
572 goto err;
573
574 seq_puts(m, "\n[TX power limit]\n");
575 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt);
576 if (ret)
577 goto err;
578
579 seq_puts(m, "\n[TX power limit_ru]\n");
580 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt_ru);
581 if (ret)
582 goto err;
583
584 err:
585 mutex_unlock(&rtwdev->mutex);
586 return ret;
587 }
588
589 static ssize_t
rtw89_debug_priv_mac_reg_dump_select(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)590 rtw89_debug_priv_mac_reg_dump_select(struct file *filp,
591 const char __user *user_buf,
592 size_t count, loff_t *loff)
593 {
594 struct seq_file *m = (struct seq_file *)filp->private_data;
595 struct rtw89_debugfs_priv *debugfs_priv = m->private;
596 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
597 char buf[32];
598 size_t buf_size;
599 int sel;
600 int ret;
601
602 buf_size = min(count, sizeof(buf) - 1);
603 if (copy_from_user(buf, user_buf, buf_size))
604 return -EFAULT;
605
606 buf[buf_size] = '\0';
607 ret = kstrtoint(buf, 0, &sel);
608 if (ret)
609 return ret;
610
611 if (sel < RTW89_DBG_SEL_MAC_00 || sel > RTW89_DBG_SEL_RFC) {
612 rtw89_info(rtwdev, "invalid args: %d\n", sel);
613 return -EINVAL;
614 }
615
616 debugfs_priv->cb_data = sel;
617 rtw89_info(rtwdev, "select mac page dump %d\n", debugfs_priv->cb_data);
618
619 return count;
620 }
621
622 #define RTW89_MAC_PAGE_SIZE 0x100
623
rtw89_debug_priv_mac_reg_dump_get(struct seq_file * m,void * v)624 static int rtw89_debug_priv_mac_reg_dump_get(struct seq_file *m, void *v)
625 {
626 struct rtw89_debugfs_priv *debugfs_priv = m->private;
627 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
628 enum rtw89_debug_mac_reg_sel reg_sel = debugfs_priv->cb_data;
629 u32 start, end;
630 u32 i, j, k, page;
631 u32 val;
632
633 switch (reg_sel) {
634 case RTW89_DBG_SEL_MAC_00:
635 seq_puts(m, "Debug selected MAC page 0x00\n");
636 start = 0x000;
637 end = 0x014;
638 break;
639 case RTW89_DBG_SEL_MAC_30:
640 seq_puts(m, "Debug selected MAC page 0x30\n");
641 start = 0x030;
642 end = 0x033;
643 break;
644 case RTW89_DBG_SEL_MAC_40:
645 seq_puts(m, "Debug selected MAC page 0x40\n");
646 start = 0x040;
647 end = 0x07f;
648 break;
649 case RTW89_DBG_SEL_MAC_80:
650 seq_puts(m, "Debug selected MAC page 0x80\n");
651 start = 0x080;
652 end = 0x09f;
653 break;
654 case RTW89_DBG_SEL_MAC_C0:
655 seq_puts(m, "Debug selected MAC page 0xc0\n");
656 start = 0x0c0;
657 end = 0x0df;
658 break;
659 case RTW89_DBG_SEL_MAC_E0:
660 seq_puts(m, "Debug selected MAC page 0xe0\n");
661 start = 0x0e0;
662 end = 0x0ff;
663 break;
664 case RTW89_DBG_SEL_BB:
665 seq_puts(m, "Debug selected BB register\n");
666 start = 0x100;
667 end = 0x17f;
668 break;
669 case RTW89_DBG_SEL_IQK:
670 seq_puts(m, "Debug selected IQK register\n");
671 start = 0x180;
672 end = 0x1bf;
673 break;
674 case RTW89_DBG_SEL_RFC:
675 seq_puts(m, "Debug selected RFC register\n");
676 start = 0x1c0;
677 end = 0x1ff;
678 break;
679 default:
680 seq_puts(m, "Selected invalid register page\n");
681 return -EINVAL;
682 }
683
684 for (i = start; i <= end; i++) {
685 page = i << 8;
686 for (j = page; j < page + RTW89_MAC_PAGE_SIZE; j += 16) {
687 seq_printf(m, "%08xh : ", 0x18600000 + j);
688 for (k = 0; k < 4; k++) {
689 val = rtw89_read32(rtwdev, j + (k << 2));
690 seq_printf(m, "%08x ", val);
691 }
692 seq_puts(m, "\n");
693 }
694 }
695
696 return 0;
697 }
698
699 static ssize_t
rtw89_debug_priv_mac_mem_dump_select(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)700 rtw89_debug_priv_mac_mem_dump_select(struct file *filp,
701 const char __user *user_buf,
702 size_t count, loff_t *loff)
703 {
704 struct seq_file *m = (struct seq_file *)filp->private_data;
705 struct rtw89_debugfs_priv *debugfs_priv = m->private;
706 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
707 char buf[32];
708 size_t buf_size;
709 u32 sel, start_addr, len;
710 int num;
711
712 buf_size = min(count, sizeof(buf) - 1);
713 if (copy_from_user(buf, user_buf, buf_size))
714 return -EFAULT;
715
716 buf[buf_size] = '\0';
717 num = sscanf(buf, "%x %x %x", &sel, &start_addr, &len);
718 if (num != 3) {
719 rtw89_info(rtwdev, "invalid format: <sel> <start> <len>\n");
720 return -EINVAL;
721 }
722
723 debugfs_priv->mac_mem.sel = sel;
724 debugfs_priv->mac_mem.start = start_addr;
725 debugfs_priv->mac_mem.len = len;
726
727 rtw89_info(rtwdev, "select mem %d start %d len %d\n",
728 sel, start_addr, len);
729
730 return count;
731 }
732
rtw89_debug_dump_mac_mem(struct seq_file * m,struct rtw89_dev * rtwdev,u8 sel,u32 start_addr,u32 len)733 static void rtw89_debug_dump_mac_mem(struct seq_file *m,
734 struct rtw89_dev *rtwdev,
735 u8 sel, u32 start_addr, u32 len)
736 {
737 u32 base_addr, start_page, residue;
738 u32 i, j, p, pages;
739 u32 dump_len, remain;
740 u32 val;
741
742 remain = len;
743 pages = len / MAC_MEM_DUMP_PAGE_SIZE + 1;
744 start_page = start_addr / MAC_MEM_DUMP_PAGE_SIZE;
745 residue = start_addr % MAC_MEM_DUMP_PAGE_SIZE;
746 base_addr = rtw89_mac_mem_base_addrs[sel];
747 base_addr += start_page * MAC_MEM_DUMP_PAGE_SIZE;
748
749 for (p = 0; p < pages; p++) {
750 dump_len = min_t(u32, remain, MAC_MEM_DUMP_PAGE_SIZE);
751 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, base_addr);
752 for (i = R_AX_INDIR_ACCESS_ENTRY + residue;
753 i < R_AX_INDIR_ACCESS_ENTRY + dump_len;) {
754 seq_printf(m, "%08xh:", i);
755 for (j = 0;
756 j < 4 && i < R_AX_INDIR_ACCESS_ENTRY + dump_len;
757 j++, i += 4) {
758 val = rtw89_read32(rtwdev, i);
759 seq_printf(m, " %08x", val);
760 remain -= 4;
761 }
762 seq_puts(m, "\n");
763 }
764 base_addr += MAC_MEM_DUMP_PAGE_SIZE;
765 }
766 }
767
768 static int
rtw89_debug_priv_mac_mem_dump_get(struct seq_file * m,void * v)769 rtw89_debug_priv_mac_mem_dump_get(struct seq_file *m, void *v)
770 {
771 struct rtw89_debugfs_priv *debugfs_priv = m->private;
772 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
773
774 mutex_lock(&rtwdev->mutex);
775 rtw89_leave_ps_mode(rtwdev);
776 rtw89_debug_dump_mac_mem(m, rtwdev,
777 debugfs_priv->mac_mem.sel,
778 debugfs_priv->mac_mem.start,
779 debugfs_priv->mac_mem.len);
780 mutex_unlock(&rtwdev->mutex);
781
782 return 0;
783 }
784
785 static ssize_t
rtw89_debug_priv_mac_dbg_port_dump_select(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)786 rtw89_debug_priv_mac_dbg_port_dump_select(struct file *filp,
787 const char __user *user_buf,
788 size_t count, loff_t *loff)
789 {
790 struct seq_file *m = (struct seq_file *)filp->private_data;
791 struct rtw89_debugfs_priv *debugfs_priv = m->private;
792 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
793 char buf[32];
794 size_t buf_size;
795 int sel, set;
796 int num;
797 bool enable;
798
799 buf_size = min(count, sizeof(buf) - 1);
800 if (copy_from_user(buf, user_buf, buf_size))
801 return -EFAULT;
802
803 buf[buf_size] = '\0';
804 num = sscanf(buf, "%d %d", &sel, &set);
805 if (num != 2) {
806 rtw89_info(rtwdev, "invalid format: <sel> <set>\n");
807 return -EINVAL;
808 }
809
810 enable = set != 0;
811 switch (sel) {
812 case 0:
813 debugfs_priv->dbgpkg_en.ss_dbg = enable;
814 break;
815 case 1:
816 debugfs_priv->dbgpkg_en.dle_dbg = enable;
817 break;
818 case 2:
819 debugfs_priv->dbgpkg_en.dmac_dbg = enable;
820 break;
821 case 3:
822 debugfs_priv->dbgpkg_en.cmac_dbg = enable;
823 break;
824 case 4:
825 debugfs_priv->dbgpkg_en.dbg_port = enable;
826 break;
827 default:
828 rtw89_info(rtwdev, "invalid args: sel %d set %d\n", sel, set);
829 return -EINVAL;
830 }
831
832 rtw89_info(rtwdev, "%s debug port dump %d\n",
833 enable ? "Enable" : "Disable", sel);
834
835 return count;
836 }
837
rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev * rtwdev,struct seq_file * m)838 static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev,
839 struct seq_file *m)
840 {
841 return 0;
842 }
843
rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev * rtwdev,struct seq_file * m)844 static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev,
845 struct seq_file *m)
846 {
847 #define DLE_DFI_DUMP(__type, __target, __sel) \
848 ({ \
849 u32 __ctrl; \
850 u32 __reg_ctrl = R_AX_##__type##_DBG_FUN_INTF_CTL; \
851 u32 __reg_data = R_AX_##__type##_DBG_FUN_INTF_DATA; \
852 u32 __data, __val32; \
853 int __ret; \
854 \
855 __ctrl = FIELD_PREP(B_AX_##__type##_DFI_TRGSEL_MASK, \
856 DLE_DFI_TYPE_##__target) | \
857 FIELD_PREP(B_AX_##__type##_DFI_ADDR_MASK, __sel) | \
858 B_AX_WDE_DFI_ACTIVE; \
859 rtw89_write32(rtwdev, __reg_ctrl, __ctrl); \
860 __ret = read_poll_timeout(rtw89_read32, __val32, \
861 !(__val32 & B_AX_##__type##_DFI_ACTIVE), \
862 1000, 50000, false, \
863 rtwdev, __reg_ctrl); \
864 if (__ret) { \
865 rtw89_err(rtwdev, "failed to dump DLE %s %s %d\n", \
866 #__type, #__target, __sel); \
867 return __ret; \
868 } \
869 \
870 __data = rtw89_read32(rtwdev, __reg_data); \
871 __data; \
872 })
873
874 #define DLE_DFI_FREE_PAGE_DUMP(__m, __type) \
875 ({ \
876 u32 __freepg, __pubpg; \
877 u32 __freepg_head, __freepg_tail, __pubpg_num; \
878 \
879 __freepg = DLE_DFI_DUMP(__type, FREEPG, 0); \
880 __pubpg = DLE_DFI_DUMP(__type, FREEPG, 1); \
881 __freepg_head = FIELD_GET(B_AX_DLE_FREE_HEADPG, __freepg); \
882 __freepg_tail = FIELD_GET(B_AX_DLE_FREE_TAILPG, __freepg); \
883 __pubpg_num = FIELD_GET(B_AX_DLE_PUB_PGNUM, __pubpg); \
884 seq_printf(__m, "[%s] freepg head: %d\n", \
885 #__type, __freepg_head); \
886 seq_printf(__m, "[%s] freepg tail: %d\n", \
887 #__type, __freepg_tail); \
888 seq_printf(__m, "[%s] pubpg num : %d\n", \
889 #__type, __pubpg_num); \
890 })
891
892 #define case_QUOTA(__m, __type, __id) \
893 case __type##_QTAID_##__id: \
894 val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \
895 rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \
896 use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \
897 seq_printf(__m, "[%s][%s] rsv_pgnum: %d\n", \
898 #__type, #__id, rsv_pgnum); \
899 seq_printf(__m, "[%s][%s] use_pgnum: %d\n", \
900 #__type, #__id, use_pgnum); \
901 break
902 u32 quota_id;
903 u32 val32;
904 u16 rsv_pgnum, use_pgnum;
905 int ret;
906
907 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL);
908 if (ret) {
909 seq_puts(m, "[DLE] : DMAC not enabled\n");
910 return ret;
911 }
912
913 DLE_DFI_FREE_PAGE_DUMP(m, WDE);
914 DLE_DFI_FREE_PAGE_DUMP(m, PLE);
915 for (quota_id = 0; quota_id <= WDE_QTAID_CPUIO; quota_id++) {
916 switch (quota_id) {
917 case_QUOTA(m, WDE, HOST_IF);
918 case_QUOTA(m, WDE, WLAN_CPU);
919 case_QUOTA(m, WDE, DATA_CPU);
920 case_QUOTA(m, WDE, PKTIN);
921 case_QUOTA(m, WDE, CPUIO);
922 }
923 }
924 for (quota_id = 0; quota_id <= PLE_QTAID_CPUIO; quota_id++) {
925 switch (quota_id) {
926 case_QUOTA(m, PLE, B0_TXPL);
927 case_QUOTA(m, PLE, B1_TXPL);
928 case_QUOTA(m, PLE, C2H);
929 case_QUOTA(m, PLE, H2C);
930 case_QUOTA(m, PLE, WLAN_CPU);
931 case_QUOTA(m, PLE, MPDU);
932 case_QUOTA(m, PLE, CMAC0_RX);
933 case_QUOTA(m, PLE, CMAC1_RX);
934 case_QUOTA(m, PLE, CMAC1_BBRPT);
935 case_QUOTA(m, PLE, WDRLS);
936 case_QUOTA(m, PLE, CPUIO);
937 }
938 }
939
940 return 0;
941
942 #undef case_QUOTA
943 #undef DLE_DFI_DUMP
944 #undef DLE_DFI_FREE_PAGE_DUMP
945 }
946
rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev * rtwdev,struct seq_file * m)947 static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev,
948 struct seq_file *m)
949 {
950 int ret;
951
952 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL);
953 if (ret) {
954 seq_puts(m, "[DMAC] : DMAC not enabled\n");
955 return ret;
956 }
957
958 seq_printf(m, "R_AX_DMAC_ERR_ISR=0x%08x\n",
959 rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR));
960 seq_printf(m, "[0]R_AX_WDRLS_ERR_ISR=0x%08x\n",
961 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR));
962 seq_printf(m, "[1]R_AX_SEC_ERR_IMR_ISR=0x%08x\n",
963 rtw89_read32(rtwdev, R_AX_SEC_ERR_IMR_ISR));
964 seq_printf(m, "[2.1]R_AX_MPDU_TX_ERR_ISR=0x%08x\n",
965 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR));
966 seq_printf(m, "[2.2]R_AX_MPDU_RX_ERR_ISR=0x%08x\n",
967 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR));
968 seq_printf(m, "[3]R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n",
969 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR));
970 seq_printf(m, "[4]R_AX_WDE_ERR_ISR=0x%08x\n",
971 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
972 seq_printf(m, "[5.1]R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n",
973 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR));
974 seq_printf(m, "[5.2]R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n",
975 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1));
976 seq_printf(m, "[6]R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
977 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
978 seq_printf(m, "[7]R_AX_PKTIN_ERR_ISR=0x%08x\n",
979 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR));
980 seq_printf(m, "[8.1]R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n",
981 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR));
982 seq_printf(m, "[8.2]R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n",
983 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR));
984 seq_printf(m, "[8.3]R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n",
985 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR));
986 seq_printf(m, "[10]R_AX_CPUIO_ERR_ISR=0x%08x\n",
987 rtw89_read32(rtwdev, R_AX_CPUIO_ERR_ISR));
988 seq_printf(m, "[11.1]R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n",
989 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR));
990 seq_printf(m, "[11.2]R_AX_BBRPT_CHINFO_ERR_IMR_ISR=0x%08x\n",
991 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR_ISR));
992 seq_printf(m, "[11.3]R_AX_BBRPT_DFS_ERR_IMR_ISR=0x%08x\n",
993 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR_ISR));
994 seq_printf(m, "[11.4]R_AX_LA_ERRFLAG=0x%08x\n",
995 rtw89_read32(rtwdev, R_AX_LA_ERRFLAG));
996
997 return 0;
998 }
999
rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev * rtwdev,struct seq_file * m)1000 static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev,
1001 struct seq_file *m)
1002 {
1003 int ret;
1004
1005 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL);
1006 if (ret) {
1007 seq_puts(m, "[CMAC] : CMAC 0 not enabled\n");
1008 return ret;
1009 }
1010
1011 seq_printf(m, "R_AX_CMAC_ERR_ISR=0x%08x\n",
1012 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR));
1013 seq_printf(m, "[0]R_AX_SCHEDULE_ERR_ISR=0x%08x\n",
1014 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR));
1015 seq_printf(m, "[1]R_AX_PTCL_ISR0=0x%08x\n",
1016 rtw89_read32(rtwdev, R_AX_PTCL_ISR0));
1017 seq_printf(m, "[3]R_AX_DLE_CTRL=0x%08x\n",
1018 rtw89_read32(rtwdev, R_AX_DLE_CTRL));
1019 seq_printf(m, "[4]R_AX_PHYINFO_ERR_ISR=0x%08x\n",
1020 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR));
1021 seq_printf(m, "[5]R_AX_TXPWR_ISR=0x%08x\n",
1022 rtw89_read32(rtwdev, R_AX_TXPWR_ISR));
1023 seq_printf(m, "[6]R_AX_RMAC_ERR_ISR=0x%08x\n",
1024 rtw89_read32(rtwdev, R_AX_RMAC_ERR_ISR));
1025 seq_printf(m, "[7]R_AX_TMAC_ERR_IMR_ISR=0x%08x\n",
1026 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR));
1027
1028 ret = rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL);
1029 if (ret) {
1030 seq_puts(m, "[CMAC] : CMAC 1 not enabled\n");
1031 return ret;
1032 }
1033
1034 seq_printf(m, "R_AX_CMAC_ERR_ISR_C1=0x%08x\n",
1035 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR_C1));
1036 seq_printf(m, "[0]R_AX_SCHEDULE_ERR_ISR_C1=0x%08x\n",
1037 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR_C1));
1038 seq_printf(m, "[1]R_AX_PTCL_ISR0_C1=0x%08x\n",
1039 rtw89_read32(rtwdev, R_AX_PTCL_ISR0_C1));
1040 seq_printf(m, "[3]R_AX_DLE_CTRL_C1=0x%08x\n",
1041 rtw89_read32(rtwdev, R_AX_DLE_CTRL_C1));
1042 seq_printf(m, "[4]R_AX_PHYINFO_ERR_ISR_C1=0x%02x\n",
1043 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR_C1));
1044 seq_printf(m, "[5]R_AX_TXPWR_ISR_C1=0x%08x\n",
1045 rtw89_read32(rtwdev, R_AX_TXPWR_ISR_C1));
1046 seq_printf(m, "[6]R_AX_RMAC_ERR_ISR_C1=0x%08x\n",
1047 rtw89_read32(rtwdev, R_AX_RMAC_ERR_ISR_C1));
1048 seq_printf(m, "[7]R_AX_TMAC_ERR_IMR_ISR_C1=0x%08x\n",
1049 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR_C1));
1050
1051 return 0;
1052 }
1053
1054 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = {
1055 .sel_addr = R_AX_PTCL_DBG,
1056 .sel_byte = 1,
1057 .sel_msk = B_AX_PTCL_DBG_SEL_MASK,
1058 .srt = 0x00,
1059 .end = 0x3F,
1060 .rd_addr = R_AX_PTCL_DBG_INFO,
1061 .rd_byte = 4,
1062 .rd_msk = B_AX_PTCL_DBG_INFO_MASK
1063 };
1064
1065 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = {
1066 .sel_addr = R_AX_PTCL_DBG_C1,
1067 .sel_byte = 1,
1068 .sel_msk = B_AX_PTCL_DBG_SEL_MASK,
1069 .srt = 0x00,
1070 .end = 0x3F,
1071 .rd_addr = R_AX_PTCL_DBG_INFO_C1,
1072 .rd_byte = 4,
1073 .rd_msk = B_AX_PTCL_DBG_INFO_MASK
1074 };
1075
1076 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = {
1077 .sel_addr = R_AX_SCH_DBG_SEL,
1078 .sel_byte = 1,
1079 .sel_msk = B_AX_SCH_DBG_SEL_MASK,
1080 .srt = 0x00,
1081 .end = 0x2F,
1082 .rd_addr = R_AX_SCH_DBG,
1083 .rd_byte = 4,
1084 .rd_msk = B_AX_SCHEDULER_DBG_MASK
1085 };
1086
1087 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = {
1088 .sel_addr = R_AX_SCH_DBG_SEL_C1,
1089 .sel_byte = 1,
1090 .sel_msk = B_AX_SCH_DBG_SEL_MASK,
1091 .srt = 0x00,
1092 .end = 0x2F,
1093 .rd_addr = R_AX_SCH_DBG_C1,
1094 .rd_byte = 4,
1095 .rd_msk = B_AX_SCHEDULER_DBG_MASK
1096 };
1097
1098 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = {
1099 .sel_addr = R_AX_MACTX_DBG_SEL_CNT,
1100 .sel_byte = 1,
1101 .sel_msk = B_AX_DBGSEL_MACTX_MASK,
1102 .srt = 0x00,
1103 .end = 0x19,
1104 .rd_addr = R_AX_DBG_PORT_SEL,
1105 .rd_byte = 4,
1106 .rd_msk = B_AX_DEBUG_ST_MASK
1107 };
1108
1109 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = {
1110 .sel_addr = R_AX_MACTX_DBG_SEL_CNT_C1,
1111 .sel_byte = 1,
1112 .sel_msk = B_AX_DBGSEL_MACTX_MASK,
1113 .srt = 0x00,
1114 .end = 0x19,
1115 .rd_addr = R_AX_DBG_PORT_SEL,
1116 .rd_byte = 4,
1117 .rd_msk = B_AX_DEBUG_ST_MASK
1118 };
1119
1120 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = {
1121 .sel_addr = R_AX_RX_DEBUG_SELECT,
1122 .sel_byte = 1,
1123 .sel_msk = B_AX_DEBUG_SEL_MASK,
1124 .srt = 0x00,
1125 .end = 0x58,
1126 .rd_addr = R_AX_DBG_PORT_SEL,
1127 .rd_byte = 4,
1128 .rd_msk = B_AX_DEBUG_ST_MASK
1129 };
1130
1131 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = {
1132 .sel_addr = R_AX_RX_DEBUG_SELECT_C1,
1133 .sel_byte = 1,
1134 .sel_msk = B_AX_DEBUG_SEL_MASK,
1135 .srt = 0x00,
1136 .end = 0x58,
1137 .rd_addr = R_AX_DBG_PORT_SEL,
1138 .rd_byte = 4,
1139 .rd_msk = B_AX_DEBUG_ST_MASK
1140 };
1141
1142 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = {
1143 .sel_addr = R_AX_RX_STATE_MONITOR,
1144 .sel_byte = 1,
1145 .sel_msk = B_AX_STATE_SEL_MASK,
1146 .srt = 0x00,
1147 .end = 0x17,
1148 .rd_addr = R_AX_RX_STATE_MONITOR,
1149 .rd_byte = 4,
1150 .rd_msk = B_AX_RX_STATE_MONITOR_MASK
1151 };
1152
1153 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = {
1154 .sel_addr = R_AX_RX_STATE_MONITOR_C1,
1155 .sel_byte = 1,
1156 .sel_msk = B_AX_STATE_SEL_MASK,
1157 .srt = 0x00,
1158 .end = 0x17,
1159 .rd_addr = R_AX_RX_STATE_MONITOR_C1,
1160 .rd_byte = 4,
1161 .rd_msk = B_AX_RX_STATE_MONITOR_MASK
1162 };
1163
1164 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = {
1165 .sel_addr = R_AX_RMAC_PLCP_MON,
1166 .sel_byte = 4,
1167 .sel_msk = B_AX_PCLP_MON_SEL_MASK,
1168 .srt = 0x0,
1169 .end = 0xF,
1170 .rd_addr = R_AX_RMAC_PLCP_MON,
1171 .rd_byte = 4,
1172 .rd_msk = B_AX_RMAC_PLCP_MON_MASK
1173 };
1174
1175 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = {
1176 .sel_addr = R_AX_RMAC_PLCP_MON_C1,
1177 .sel_byte = 4,
1178 .sel_msk = B_AX_PCLP_MON_SEL_MASK,
1179 .srt = 0x0,
1180 .end = 0xF,
1181 .rd_addr = R_AX_RMAC_PLCP_MON_C1,
1182 .rd_byte = 4,
1183 .rd_msk = B_AX_RMAC_PLCP_MON_MASK
1184 };
1185
1186 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = {
1187 .sel_addr = R_AX_DBGSEL_TRXPTCL,
1188 .sel_byte = 1,
1189 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK,
1190 .srt = 0x08,
1191 .end = 0x10,
1192 .rd_addr = R_AX_DBG_PORT_SEL,
1193 .rd_byte = 4,
1194 .rd_msk = B_AX_DEBUG_ST_MASK
1195 };
1196
1197 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = {
1198 .sel_addr = R_AX_DBGSEL_TRXPTCL_C1,
1199 .sel_byte = 1,
1200 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK,
1201 .srt = 0x08,
1202 .end = 0x10,
1203 .rd_addr = R_AX_DBG_PORT_SEL,
1204 .rd_byte = 4,
1205 .rd_msk = B_AX_DEBUG_ST_MASK
1206 };
1207
1208 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = {
1209 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG,
1210 .sel_byte = 1,
1211 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK,
1212 .srt = 0x00,
1213 .end = 0x07,
1214 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG,
1215 .rd_byte = 4,
1216 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK
1217 };
1218
1219 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = {
1220 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG,
1221 .sel_byte = 1,
1222 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK,
1223 .srt = 0x00,
1224 .end = 0x07,
1225 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG,
1226 .rd_byte = 4,
1227 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK
1228 };
1229
1230 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = {
1231 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1,
1232 .sel_byte = 1,
1233 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK,
1234 .srt = 0x00,
1235 .end = 0x07,
1236 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG_C1,
1237 .rd_byte = 4,
1238 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK
1239 };
1240
1241 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = {
1242 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1,
1243 .sel_byte = 1,
1244 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK,
1245 .srt = 0x00,
1246 .end = 0x07,
1247 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG_C1,
1248 .rd_byte = 4,
1249 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK
1250 };
1251
1252 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = {
1253 .sel_addr = R_AX_WMAC_TX_TF_INFO_0,
1254 .sel_byte = 1,
1255 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK,
1256 .srt = 0x00,
1257 .end = 0x04,
1258 .rd_addr = R_AX_WMAC_TX_TF_INFO_1,
1259 .rd_byte = 4,
1260 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK
1261 };
1262
1263 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = {
1264 .sel_addr = R_AX_WMAC_TX_TF_INFO_0,
1265 .sel_byte = 1,
1266 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK,
1267 .srt = 0x00,
1268 .end = 0x04,
1269 .rd_addr = R_AX_WMAC_TX_TF_INFO_2,
1270 .rd_byte = 4,
1271 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK
1272 };
1273
1274 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = {
1275 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1,
1276 .sel_byte = 1,
1277 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK,
1278 .srt = 0x00,
1279 .end = 0x04,
1280 .rd_addr = R_AX_WMAC_TX_TF_INFO_1_C1,
1281 .rd_byte = 4,
1282 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK
1283 };
1284
1285 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = {
1286 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1,
1287 .sel_byte = 1,
1288 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK,
1289 .srt = 0x00,
1290 .end = 0x04,
1291 .rd_addr = R_AX_WMAC_TX_TF_INFO_2_C1,
1292 .rd_byte = 4,
1293 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK
1294 };
1295
1296 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = {
1297 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1298 .sel_byte = 4,
1299 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1300 .srt = 0x80000000,
1301 .end = 0x80000001,
1302 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1303 .rd_byte = 4,
1304 .rd_msk = B_AX_WDE_DFI_DATA_MASK
1305 };
1306
1307 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = {
1308 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1309 .sel_byte = 4,
1310 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1311 .srt = 0x80010000,
1312 .end = 0x80010004,
1313 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1314 .rd_byte = 4,
1315 .rd_msk = B_AX_WDE_DFI_DATA_MASK
1316 };
1317
1318 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = {
1319 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1320 .sel_byte = 4,
1321 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1322 .srt = 0x80020000,
1323 .end = 0x80020FFF,
1324 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1325 .rd_byte = 4,
1326 .rd_msk = B_AX_WDE_DFI_DATA_MASK
1327 };
1328
1329 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = {
1330 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1331 .sel_byte = 4,
1332 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1333 .srt = 0x80030000,
1334 .end = 0x80030FFF,
1335 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1336 .rd_byte = 4,
1337 .rd_msk = B_AX_WDE_DFI_DATA_MASK
1338 };
1339
1340 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = {
1341 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1342 .sel_byte = 4,
1343 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1344 .srt = 0x80040000,
1345 .end = 0x80040FFF,
1346 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1347 .rd_byte = 4,
1348 .rd_msk = B_AX_WDE_DFI_DATA_MASK
1349 };
1350
1351 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = {
1352 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1353 .sel_byte = 4,
1354 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1355 .srt = 0x80050000,
1356 .end = 0x80050FFF,
1357 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1358 .rd_byte = 4,
1359 .rd_msk = B_AX_WDE_DFI_DATA_MASK
1360 };
1361
1362 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = {
1363 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1364 .sel_byte = 4,
1365 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1366 .srt = 0x80060000,
1367 .end = 0x80060453,
1368 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1369 .rd_byte = 4,
1370 .rd_msk = B_AX_WDE_DFI_DATA_MASK
1371 };
1372
1373 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = {
1374 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1375 .sel_byte = 4,
1376 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1377 .srt = 0x80070000,
1378 .end = 0x80070011,
1379 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1380 .rd_byte = 4,
1381 .rd_msk = B_AX_WDE_DFI_DATA_MASK
1382 };
1383
1384 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = {
1385 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
1386 .sel_byte = 4,
1387 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
1388 .srt = 0x80000000,
1389 .end = 0x80000001,
1390 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
1391 .rd_byte = 4,
1392 .rd_msk = B_AX_PLE_DFI_DATA_MASK
1393 };
1394
1395 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = {
1396 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
1397 .sel_byte = 4,
1398 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
1399 .srt = 0x80010000,
1400 .end = 0x8001000A,
1401 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
1402 .rd_byte = 4,
1403 .rd_msk = B_AX_PLE_DFI_DATA_MASK
1404 };
1405
1406 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = {
1407 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
1408 .sel_byte = 4,
1409 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
1410 .srt = 0x80020000,
1411 .end = 0x80020DBF,
1412 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
1413 .rd_byte = 4,
1414 .rd_msk = B_AX_PLE_DFI_DATA_MASK
1415 };
1416
1417 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = {
1418 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
1419 .sel_byte = 4,
1420 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
1421 .srt = 0x80030000,
1422 .end = 0x80030DBF,
1423 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
1424 .rd_byte = 4,
1425 .rd_msk = B_AX_PLE_DFI_DATA_MASK
1426 };
1427
1428 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = {
1429 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
1430 .sel_byte = 4,
1431 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
1432 .srt = 0x80040000,
1433 .end = 0x80040DBF,
1434 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
1435 .rd_byte = 4,
1436 .rd_msk = B_AX_PLE_DFI_DATA_MASK
1437 };
1438
1439 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = {
1440 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
1441 .sel_byte = 4,
1442 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
1443 .srt = 0x80050000,
1444 .end = 0x80050DBF,
1445 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
1446 .rd_byte = 4,
1447 .rd_msk = B_AX_PLE_DFI_DATA_MASK
1448 };
1449
1450 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = {
1451 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
1452 .sel_byte = 4,
1453 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
1454 .srt = 0x80060000,
1455 .end = 0x80060041,
1456 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
1457 .rd_byte = 4,
1458 .rd_msk = B_AX_PLE_DFI_DATA_MASK
1459 };
1460
1461 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = {
1462 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
1463 .sel_byte = 4,
1464 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
1465 .srt = 0x80070000,
1466 .end = 0x80070001,
1467 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
1468 .rd_byte = 4,
1469 .rd_msk = B_AX_PLE_DFI_DATA_MASK
1470 };
1471
1472 static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = {
1473 .sel_addr = R_AX_DBG_FUN_INTF_CTL,
1474 .sel_byte = 4,
1475 .sel_msk = B_AX_DFI_DATA_MASK,
1476 .srt = 0x80000000,
1477 .end = 0x8000017f,
1478 .rd_addr = R_AX_DBG_FUN_INTF_DATA,
1479 .rd_byte = 4,
1480 .rd_msk = B_AX_DFI_DATA_MASK
1481 };
1482
1483 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = {
1484 .sel_addr = R_AX_PCIE_DBG_CTRL,
1485 .sel_byte = 2,
1486 .sel_msk = B_AX_DBG_SEL_MASK,
1487 .srt = 0x00,
1488 .end = 0x03,
1489 .rd_addr = R_AX_DBG_PORT_SEL,
1490 .rd_byte = 4,
1491 .rd_msk = B_AX_DEBUG_ST_MASK
1492 };
1493
1494 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = {
1495 .sel_addr = R_AX_PCIE_DBG_CTRL,
1496 .sel_byte = 2,
1497 .sel_msk = B_AX_DBG_SEL_MASK,
1498 .srt = 0x00,
1499 .end = 0x04,
1500 .rd_addr = R_AX_DBG_PORT_SEL,
1501 .rd_byte = 4,
1502 .rd_msk = B_AX_DEBUG_ST_MASK
1503 };
1504
1505 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = {
1506 .sel_addr = R_AX_PCIE_DBG_CTRL,
1507 .sel_byte = 2,
1508 .sel_msk = B_AX_DBG_SEL_MASK,
1509 .srt = 0x00,
1510 .end = 0x01,
1511 .rd_addr = R_AX_DBG_PORT_SEL,
1512 .rd_byte = 4,
1513 .rd_msk = B_AX_DEBUG_ST_MASK
1514 };
1515
1516 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = {
1517 .sel_addr = R_AX_PCIE_DBG_CTRL,
1518 .sel_byte = 2,
1519 .sel_msk = B_AX_DBG_SEL_MASK,
1520 .srt = 0x00,
1521 .end = 0x05,
1522 .rd_addr = R_AX_DBG_PORT_SEL,
1523 .rd_byte = 4,
1524 .rd_msk = B_AX_DEBUG_ST_MASK
1525 };
1526
1527 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = {
1528 .sel_addr = R_AX_PCIE_DBG_CTRL,
1529 .sel_byte = 2,
1530 .sel_msk = B_AX_DBG_SEL_MASK,
1531 .srt = 0x00,
1532 .end = 0x05,
1533 .rd_addr = R_AX_DBG_PORT_SEL,
1534 .rd_byte = 4,
1535 .rd_msk = B_AX_DEBUG_ST_MASK
1536 };
1537
1538 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = {
1539 .sel_addr = R_AX_PCIE_DBG_CTRL,
1540 .sel_byte = 2,
1541 .sel_msk = B_AX_DBG_SEL_MASK,
1542 .srt = 0x00,
1543 .end = 0x06,
1544 .rd_addr = R_AX_DBG_PORT_SEL,
1545 .rd_byte = 4,
1546 .rd_msk = B_AX_DEBUG_ST_MASK
1547 };
1548
1549 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = {
1550 .sel_addr = R_AX_DBG_CTRL,
1551 .sel_byte = 1,
1552 .sel_msk = B_AX_DBG_SEL0,
1553 .srt = 0x34,
1554 .end = 0x3C,
1555 .rd_addr = R_AX_DBG_PORT_SEL,
1556 .rd_byte = 4,
1557 .rd_msk = B_AX_DEBUG_ST_MASK
1558 };
1559
1560 static const struct rtw89_mac_dbg_port_info *
rtw89_debug_mac_dbg_port_sel(struct seq_file * m,struct rtw89_dev * rtwdev,u32 sel)1561 rtw89_debug_mac_dbg_port_sel(struct seq_file *m,
1562 struct rtw89_dev *rtwdev, u32 sel)
1563 {
1564 const struct rtw89_mac_dbg_port_info *info;
1565 u32 val32;
1566 u16 val16;
1567 u8 val8;
1568
1569 switch (sel) {
1570 case RTW89_DBG_PORT_SEL_PTCL_C0:
1571 info = &dbg_port_ptcl_c0;
1572 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG);
1573 val16 |= B_AX_PTCL_DBG_EN;
1574 rtw89_write16(rtwdev, R_AX_PTCL_DBG, val16);
1575 seq_puts(m, "Enable PTCL C0 dbgport.\n");
1576 break;
1577 case RTW89_DBG_PORT_SEL_PTCL_C1:
1578 info = &dbg_port_ptcl_c1;
1579 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG_C1);
1580 val16 |= B_AX_PTCL_DBG_EN;
1581 rtw89_write16(rtwdev, R_AX_PTCL_DBG_C1, val16);
1582 seq_puts(m, "Enable PTCL C1 dbgport.\n");
1583 break;
1584 case RTW89_DBG_PORT_SEL_SCH_C0:
1585 info = &dbg_port_sch_c0;
1586 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL);
1587 val32 |= B_AX_SCH_DBG_EN;
1588 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32);
1589 seq_puts(m, "Enable SCH C0 dbgport.\n");
1590 break;
1591 case RTW89_DBG_PORT_SEL_SCH_C1:
1592 info = &dbg_port_sch_c1;
1593 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1);
1594 val32 |= B_AX_SCH_DBG_EN;
1595 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL_C1, val32);
1596 seq_puts(m, "Enable SCH C1 dbgport.\n");
1597 break;
1598 case RTW89_DBG_PORT_SEL_TMAC_C0:
1599 info = &dbg_port_tmac_c0;
1600 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL);
1601 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC,
1602 B_AX_DBGSEL_TRXPTCL_MASK);
1603 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32);
1604
1605 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1606 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0);
1607 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1);
1608 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1609
1610 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
1611 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
1612 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
1613 seq_puts(m, "Enable TMAC C0 dbgport.\n");
1614 break;
1615 case RTW89_DBG_PORT_SEL_TMAC_C1:
1616 info = &dbg_port_tmac_c1;
1617 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1);
1618 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC,
1619 B_AX_DBGSEL_TRXPTCL_MASK);
1620 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32);
1621
1622 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1623 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0);
1624 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1);
1625 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1626
1627 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
1628 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
1629 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
1630 seq_puts(m, "Enable TMAC C1 dbgport.\n");
1631 break;
1632 case RTW89_DBG_PORT_SEL_RMAC_C0:
1633 info = &dbg_port_rmac_c0;
1634 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL);
1635 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC,
1636 B_AX_DBGSEL_TRXPTCL_MASK);
1637 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32);
1638
1639 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1640 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0);
1641 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1);
1642 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1643
1644 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
1645 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
1646 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
1647
1648 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL);
1649 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL,
1650 B_AX_DBGSEL_TRXPTCL_MASK);
1651 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8);
1652 seq_puts(m, "Enable RMAC C0 dbgport.\n");
1653 break;
1654 case RTW89_DBG_PORT_SEL_RMAC_C1:
1655 info = &dbg_port_rmac_c1;
1656 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1);
1657 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC,
1658 B_AX_DBGSEL_TRXPTCL_MASK);
1659 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32);
1660
1661 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1662 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0);
1663 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1);
1664 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1665
1666 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
1667 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
1668 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
1669
1670 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1);
1671 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL,
1672 B_AX_DBGSEL_TRXPTCL_MASK);
1673 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8);
1674 seq_puts(m, "Enable RMAC C1 dbgport.\n");
1675 break;
1676 case RTW89_DBG_PORT_SEL_RMACST_C0:
1677 info = &dbg_port_rmacst_c0;
1678 seq_puts(m, "Enable RMAC state C0 dbgport.\n");
1679 break;
1680 case RTW89_DBG_PORT_SEL_RMACST_C1:
1681 info = &dbg_port_rmacst_c1;
1682 seq_puts(m, "Enable RMAC state C1 dbgport.\n");
1683 break;
1684 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C0:
1685 info = &dbg_port_rmac_plcp_c0;
1686 seq_puts(m, "Enable RMAC PLCP C0 dbgport.\n");
1687 break;
1688 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C1:
1689 info = &dbg_port_rmac_plcp_c1;
1690 seq_puts(m, "Enable RMAC PLCP C1 dbgport.\n");
1691 break;
1692 case RTW89_DBG_PORT_SEL_TRXPTCL_C0:
1693 info = &dbg_port_trxptcl_c0;
1694 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1695 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0);
1696 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1);
1697 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1698
1699 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
1700 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
1701 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
1702 seq_puts(m, "Enable TRXPTCL C0 dbgport.\n");
1703 break;
1704 case RTW89_DBG_PORT_SEL_TRXPTCL_C1:
1705 info = &dbg_port_trxptcl_c1;
1706 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1707 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0);
1708 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1);
1709 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1710
1711 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
1712 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
1713 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
1714 seq_puts(m, "Enable TRXPTCL C1 dbgport.\n");
1715 break;
1716 case RTW89_DBG_PORT_SEL_TX_INFOL_C0:
1717 info = &dbg_port_tx_infol_c0;
1718 val32 = rtw89_read32(rtwdev, R_AX_TCR1);
1719 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
1720 rtw89_write32(rtwdev, R_AX_TCR1, val32);
1721 seq_puts(m, "Enable tx infol dump.\n");
1722 break;
1723 case RTW89_DBG_PORT_SEL_TX_INFOH_C0:
1724 info = &dbg_port_tx_infoh_c0;
1725 val32 = rtw89_read32(rtwdev, R_AX_TCR1);
1726 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
1727 rtw89_write32(rtwdev, R_AX_TCR1, val32);
1728 seq_puts(m, "Enable tx infoh dump.\n");
1729 break;
1730 case RTW89_DBG_PORT_SEL_TX_INFOL_C1:
1731 info = &dbg_port_tx_infol_c1;
1732 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1);
1733 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
1734 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32);
1735 seq_puts(m, "Enable tx infol dump.\n");
1736 break;
1737 case RTW89_DBG_PORT_SEL_TX_INFOH_C1:
1738 info = &dbg_port_tx_infoh_c1;
1739 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1);
1740 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
1741 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32);
1742 seq_puts(m, "Enable tx infoh dump.\n");
1743 break;
1744 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C0:
1745 info = &dbg_port_txtf_infol_c0;
1746 val32 = rtw89_read32(rtwdev, R_AX_TCR1);
1747 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
1748 rtw89_write32(rtwdev, R_AX_TCR1, val32);
1749 seq_puts(m, "Enable tx tf infol dump.\n");
1750 break;
1751 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C0:
1752 info = &dbg_port_txtf_infoh_c0;
1753 val32 = rtw89_read32(rtwdev, R_AX_TCR1);
1754 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
1755 rtw89_write32(rtwdev, R_AX_TCR1, val32);
1756 seq_puts(m, "Enable tx tf infoh dump.\n");
1757 break;
1758 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C1:
1759 info = &dbg_port_txtf_infol_c1;
1760 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1);
1761 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
1762 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32);
1763 seq_puts(m, "Enable tx tf infol dump.\n");
1764 break;
1765 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C1:
1766 info = &dbg_port_txtf_infoh_c1;
1767 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1);
1768 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
1769 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32);
1770 seq_puts(m, "Enable tx tf infoh dump.\n");
1771 break;
1772 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG:
1773 info = &dbg_port_wde_bufmgn_freepg;
1774 seq_puts(m, "Enable wde bufmgn freepg dump.\n");
1775 break;
1776 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA:
1777 info = &dbg_port_wde_bufmgn_quota;
1778 seq_puts(m, "Enable wde bufmgn quota dump.\n");
1779 break;
1780 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT:
1781 info = &dbg_port_wde_bufmgn_pagellt;
1782 seq_puts(m, "Enable wde bufmgn pagellt dump.\n");
1783 break;
1784 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO:
1785 info = &dbg_port_wde_bufmgn_pktinfo;
1786 seq_puts(m, "Enable wde bufmgn pktinfo dump.\n");
1787 break;
1788 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT:
1789 info = &dbg_port_wde_quemgn_prepkt;
1790 seq_puts(m, "Enable wde quemgn prepkt dump.\n");
1791 break;
1792 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT:
1793 info = &dbg_port_wde_quemgn_nxtpkt;
1794 seq_puts(m, "Enable wde quemgn nxtpkt dump.\n");
1795 break;
1796 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL:
1797 info = &dbg_port_wde_quemgn_qlnktbl;
1798 seq_puts(m, "Enable wde quemgn qlnktbl dump.\n");
1799 break;
1800 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY:
1801 info = &dbg_port_wde_quemgn_qempty;
1802 seq_puts(m, "Enable wde quemgn qempty dump.\n");
1803 break;
1804 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG:
1805 info = &dbg_port_ple_bufmgn_freepg;
1806 seq_puts(m, "Enable ple bufmgn freepg dump.\n");
1807 break;
1808 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA:
1809 info = &dbg_port_ple_bufmgn_quota;
1810 seq_puts(m, "Enable ple bufmgn quota dump.\n");
1811 break;
1812 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT:
1813 info = &dbg_port_ple_bufmgn_pagellt;
1814 seq_puts(m, "Enable ple bufmgn pagellt dump.\n");
1815 break;
1816 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO:
1817 info = &dbg_port_ple_bufmgn_pktinfo;
1818 seq_puts(m, "Enable ple bufmgn pktinfo dump.\n");
1819 break;
1820 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT:
1821 info = &dbg_port_ple_quemgn_prepkt;
1822 seq_puts(m, "Enable ple quemgn prepkt dump.\n");
1823 break;
1824 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT:
1825 info = &dbg_port_ple_quemgn_nxtpkt;
1826 seq_puts(m, "Enable ple quemgn nxtpkt dump.\n");
1827 break;
1828 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL:
1829 info = &dbg_port_ple_quemgn_qlnktbl;
1830 seq_puts(m, "Enable ple quemgn qlnktbl dump.\n");
1831 break;
1832 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY:
1833 info = &dbg_port_ple_quemgn_qempty;
1834 seq_puts(m, "Enable ple quemgn qempty dump.\n");
1835 break;
1836 case RTW89_DBG_PORT_SEL_PKTINFO:
1837 info = &dbg_port_pktinfo;
1838 seq_puts(m, "Enable pktinfo dump.\n");
1839 break;
1840 case RTW89_DBG_PORT_SEL_PCIE_TXDMA:
1841 info = &dbg_port_pcie_txdma;
1842 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1843 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0);
1844 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1);
1845 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1846 seq_puts(m, "Enable pcie txdma dump.\n");
1847 break;
1848 case RTW89_DBG_PORT_SEL_PCIE_RXDMA:
1849 info = &dbg_port_pcie_rxdma;
1850 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1851 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0);
1852 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1);
1853 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1854 seq_puts(m, "Enable pcie rxdma dump.\n");
1855 break;
1856 case RTW89_DBG_PORT_SEL_PCIE_CVT:
1857 info = &dbg_port_pcie_cvt;
1858 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1859 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0);
1860 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1);
1861 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1862 seq_puts(m, "Enable pcie cvt dump.\n");
1863 break;
1864 case RTW89_DBG_PORT_SEL_PCIE_CXPL:
1865 info = &dbg_port_pcie_cxpl;
1866 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1867 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL0);
1868 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL1);
1869 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1870 seq_puts(m, "Enable pcie cxpl dump.\n");
1871 break;
1872 case RTW89_DBG_PORT_SEL_PCIE_IO:
1873 info = &dbg_port_pcie_io;
1874 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1875 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL0);
1876 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL1);
1877 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1878 seq_puts(m, "Enable pcie io dump.\n");
1879 break;
1880 case RTW89_DBG_PORT_SEL_PCIE_MISC:
1881 info = &dbg_port_pcie_misc;
1882 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
1883 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL0);
1884 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL1);
1885 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
1886 seq_puts(m, "Enable pcie misc dump.\n");
1887 break;
1888 case RTW89_DBG_PORT_SEL_PCIE_MISC2:
1889 info = &dbg_port_pcie_misc2;
1890 val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL);
1891 val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL,
1892 B_AX_DBG_SEL_MASK);
1893 rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16);
1894 seq_puts(m, "Enable pcie misc2 dump.\n");
1895 break;
1896 default:
1897 seq_puts(m, "Dbg port select err\n");
1898 return NULL;
1899 }
1900
1901 return info;
1902 }
1903
is_dbg_port_valid(struct rtw89_dev * rtwdev,u32 sel)1904 static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel)
1905 {
1906 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE &&
1907 sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA &&
1908 sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2)
1909 return false;
1910 if (rtwdev->chip->chip_id == RTL8852B &&
1911 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 &&
1912 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1)
1913 return false;
1914 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) &&
1915 sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG &&
1916 sel <= RTW89_DBG_PORT_SEL_PKTINFO)
1917 return false;
1918 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) &&
1919 sel >= RTW89_DBG_PORT_SEL_PTCL_C0 &&
1920 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0)
1921 return false;
1922 if (rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL) &&
1923 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 &&
1924 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1)
1925 return false;
1926
1927 return true;
1928 }
1929
rtw89_debug_mac_dbg_port_dump(struct rtw89_dev * rtwdev,struct seq_file * m,u32 sel)1930 static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev,
1931 struct seq_file *m, u32 sel)
1932 {
1933 const struct rtw89_mac_dbg_port_info *info;
1934 u8 val8;
1935 u16 val16;
1936 u32 val32;
1937 u32 i;
1938
1939 info = rtw89_debug_mac_dbg_port_sel(m, rtwdev, sel);
1940 if (!info) {
1941 rtw89_err(rtwdev, "failed to select debug port %d\n", sel);
1942 return -EINVAL;
1943 }
1944
1945 #define case_DBG_SEL(__sel) \
1946 case RTW89_DBG_PORT_SEL_##__sel: \
1947 seq_puts(m, "Dump debug port " #__sel ":\n"); \
1948 break
1949
1950 switch (sel) {
1951 case_DBG_SEL(PTCL_C0);
1952 case_DBG_SEL(PTCL_C1);
1953 case_DBG_SEL(SCH_C0);
1954 case_DBG_SEL(SCH_C1);
1955 case_DBG_SEL(TMAC_C0);
1956 case_DBG_SEL(TMAC_C1);
1957 case_DBG_SEL(RMAC_C0);
1958 case_DBG_SEL(RMAC_C1);
1959 case_DBG_SEL(RMACST_C0);
1960 case_DBG_SEL(RMACST_C1);
1961 case_DBG_SEL(TRXPTCL_C0);
1962 case_DBG_SEL(TRXPTCL_C1);
1963 case_DBG_SEL(TX_INFOL_C0);
1964 case_DBG_SEL(TX_INFOH_C0);
1965 case_DBG_SEL(TX_INFOL_C1);
1966 case_DBG_SEL(TX_INFOH_C1);
1967 case_DBG_SEL(TXTF_INFOL_C0);
1968 case_DBG_SEL(TXTF_INFOH_C0);
1969 case_DBG_SEL(TXTF_INFOL_C1);
1970 case_DBG_SEL(TXTF_INFOH_C1);
1971 case_DBG_SEL(WDE_BUFMGN_FREEPG);
1972 case_DBG_SEL(WDE_BUFMGN_QUOTA);
1973 case_DBG_SEL(WDE_BUFMGN_PAGELLT);
1974 case_DBG_SEL(WDE_BUFMGN_PKTINFO);
1975 case_DBG_SEL(WDE_QUEMGN_PREPKT);
1976 case_DBG_SEL(WDE_QUEMGN_NXTPKT);
1977 case_DBG_SEL(WDE_QUEMGN_QLNKTBL);
1978 case_DBG_SEL(WDE_QUEMGN_QEMPTY);
1979 case_DBG_SEL(PLE_BUFMGN_FREEPG);
1980 case_DBG_SEL(PLE_BUFMGN_QUOTA);
1981 case_DBG_SEL(PLE_BUFMGN_PAGELLT);
1982 case_DBG_SEL(PLE_BUFMGN_PKTINFO);
1983 case_DBG_SEL(PLE_QUEMGN_PREPKT);
1984 case_DBG_SEL(PLE_QUEMGN_NXTPKT);
1985 case_DBG_SEL(PLE_QUEMGN_QLNKTBL);
1986 case_DBG_SEL(PLE_QUEMGN_QEMPTY);
1987 case_DBG_SEL(PKTINFO);
1988 case_DBG_SEL(PCIE_TXDMA);
1989 case_DBG_SEL(PCIE_RXDMA);
1990 case_DBG_SEL(PCIE_CVT);
1991 case_DBG_SEL(PCIE_CXPL);
1992 case_DBG_SEL(PCIE_IO);
1993 case_DBG_SEL(PCIE_MISC);
1994 case_DBG_SEL(PCIE_MISC2);
1995 }
1996
1997 #undef case_DBG_SEL
1998
1999 seq_printf(m, "Sel addr = 0x%X\n", info->sel_addr);
2000 seq_printf(m, "Read addr = 0x%X\n", info->rd_addr);
2001
2002 for (i = info->srt; i <= info->end; i++) {
2003 switch (info->sel_byte) {
2004 case 1:
2005 default:
2006 rtw89_write8_mask(rtwdev, info->sel_addr,
2007 info->sel_msk, i);
2008 seq_printf(m, "0x%02X: ", i);
2009 break;
2010 case 2:
2011 rtw89_write16_mask(rtwdev, info->sel_addr,
2012 info->sel_msk, i);
2013 seq_printf(m, "0x%04X: ", i);
2014 break;
2015 case 4:
2016 rtw89_write32_mask(rtwdev, info->sel_addr,
2017 info->sel_msk, i);
2018 seq_printf(m, "0x%04X: ", i);
2019 break;
2020 }
2021
2022 udelay(10);
2023
2024 switch (info->rd_byte) {
2025 case 1:
2026 default:
2027 val8 = rtw89_read8_mask(rtwdev,
2028 info->rd_addr, info->rd_msk);
2029 seq_printf(m, "0x%02X\n", val8);
2030 break;
2031 case 2:
2032 val16 = rtw89_read16_mask(rtwdev,
2033 info->rd_addr, info->rd_msk);
2034 seq_printf(m, "0x%04X\n", val16);
2035 break;
2036 case 4:
2037 val32 = rtw89_read32_mask(rtwdev,
2038 info->rd_addr, info->rd_msk);
2039 seq_printf(m, "0x%08X\n", val32);
2040 break;
2041 }
2042 }
2043
2044 return 0;
2045 }
2046
rtw89_debug_mac_dump_dbg_port(struct rtw89_dev * rtwdev,struct seq_file * m)2047 static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev,
2048 struct seq_file *m)
2049 {
2050 u32 sel;
2051 int ret = 0;
2052
2053 for (sel = RTW89_DBG_PORT_SEL_PTCL_C0;
2054 sel < RTW89_DBG_PORT_SEL_LAST; sel++) {
2055 if (!is_dbg_port_valid(rtwdev, sel))
2056 continue;
2057 ret = rtw89_debug_mac_dbg_port_dump(rtwdev, m, sel);
2058 if (ret) {
2059 rtw89_err(rtwdev,
2060 "failed to dump debug port %d\n", sel);
2061 break;
2062 }
2063 }
2064
2065 return ret;
2066 }
2067
2068 static int
rtw89_debug_priv_mac_dbg_port_dump_get(struct seq_file * m,void * v)2069 rtw89_debug_priv_mac_dbg_port_dump_get(struct seq_file *m, void *v)
2070 {
2071 struct rtw89_debugfs_priv *debugfs_priv = m->private;
2072 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2073
2074 if (debugfs_priv->dbgpkg_en.ss_dbg)
2075 rtw89_debug_mac_dump_ss_dbg(rtwdev, m);
2076 if (debugfs_priv->dbgpkg_en.dle_dbg)
2077 rtw89_debug_mac_dump_dle_dbg(rtwdev, m);
2078 if (debugfs_priv->dbgpkg_en.dmac_dbg)
2079 rtw89_debug_mac_dump_dmac_dbg(rtwdev, m);
2080 if (debugfs_priv->dbgpkg_en.cmac_dbg)
2081 rtw89_debug_mac_dump_cmac_dbg(rtwdev, m);
2082 if (debugfs_priv->dbgpkg_en.dbg_port)
2083 rtw89_debug_mac_dump_dbg_port(rtwdev, m);
2084
2085 return 0;
2086 };
2087
rtw89_hex2bin_user(struct rtw89_dev * rtwdev,const char __user * user_buf,size_t count)2088 static u8 *rtw89_hex2bin_user(struct rtw89_dev *rtwdev,
2089 const char __user *user_buf, size_t count)
2090 {
2091 char *buf;
2092 u8 *bin;
2093 int num;
2094 int err = 0;
2095
2096 buf = memdup_user(user_buf, count);
2097 if (IS_ERR(buf))
2098 return buf;
2099
2100 num = count / 2;
2101 bin = kmalloc(num, GFP_KERNEL);
2102 if (!bin) {
2103 err = -EFAULT;
2104 goto out;
2105 }
2106
2107 if (hex2bin(bin, buf, num)) {
2108 rtw89_info(rtwdev, "valid format: H1H2H3...\n");
2109 kfree(bin);
2110 err = -EINVAL;
2111 }
2112
2113 out:
2114 kfree(buf);
2115
2116 return err ? ERR_PTR(err) : bin;
2117 }
2118
rtw89_debug_priv_send_h2c_set(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)2119 static ssize_t rtw89_debug_priv_send_h2c_set(struct file *filp,
2120 const char __user *user_buf,
2121 size_t count, loff_t *loff)
2122 {
2123 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
2124 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2125 u8 *h2c;
2126 u16 h2c_len = count / 2;
2127
2128 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count);
2129 if (IS_ERR(h2c))
2130 return -EFAULT;
2131
2132 rtw89_fw_h2c_raw(rtwdev, h2c, h2c_len);
2133
2134 kfree(h2c);
2135
2136 return count;
2137 }
2138
2139 static int
rtw89_debug_priv_early_h2c_get(struct seq_file * m,void * v)2140 rtw89_debug_priv_early_h2c_get(struct seq_file *m, void *v)
2141 {
2142 struct rtw89_debugfs_priv *debugfs_priv = m->private;
2143 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2144 struct rtw89_early_h2c *early_h2c;
2145 int seq = 0;
2146
2147 mutex_lock(&rtwdev->mutex);
2148 list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list)
2149 seq_printf(m, "%d: %*ph\n", ++seq, early_h2c->h2c_len, early_h2c->h2c);
2150 mutex_unlock(&rtwdev->mutex);
2151
2152 return 0;
2153 }
2154
2155 static ssize_t
rtw89_debug_priv_early_h2c_set(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)2156 rtw89_debug_priv_early_h2c_set(struct file *filp, const char __user *user_buf,
2157 size_t count, loff_t *loff)
2158 {
2159 struct seq_file *m = (struct seq_file *)filp->private_data;
2160 struct rtw89_debugfs_priv *debugfs_priv = m->private;
2161 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2162 struct rtw89_early_h2c *early_h2c;
2163 u8 *h2c;
2164 u16 h2c_len = count / 2;
2165
2166 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count);
2167 if (IS_ERR(h2c))
2168 return -EFAULT;
2169
2170 if (h2c_len >= 2 && h2c[0] == 0x00 && h2c[1] == 0x00) {
2171 kfree(h2c);
2172 rtw89_fw_free_all_early_h2c(rtwdev);
2173 goto out;
2174 }
2175
2176 early_h2c = kmalloc(sizeof(*early_h2c), GFP_KERNEL);
2177 if (!early_h2c) {
2178 kfree(h2c);
2179 return -EFAULT;
2180 }
2181
2182 early_h2c->h2c = h2c;
2183 early_h2c->h2c_len = h2c_len;
2184
2185 mutex_lock(&rtwdev->mutex);
2186 list_add_tail(&early_h2c->list, &rtwdev->early_h2c_list);
2187 mutex_unlock(&rtwdev->mutex);
2188
2189 out:
2190 return count;
2191 }
2192
rtw89_dbg_trigger_ctrl_error(struct rtw89_dev * rtwdev)2193 static int rtw89_dbg_trigger_ctrl_error(struct rtw89_dev *rtwdev)
2194 {
2195 struct rtw89_cpuio_ctrl ctrl_para = {0};
2196 u16 pkt_id;
2197
2198 rtw89_leave_ps_mode(rtwdev);
2199
2200 pkt_id = rtw89_mac_dle_buf_req(rtwdev, 0x20, true);
2201 switch (pkt_id) {
2202 case 0xffff:
2203 return -ETIMEDOUT;
2204 case 0xfff:
2205 return -ENOMEM;
2206 default:
2207 break;
2208 }
2209
2210 /* intentionally, enqueue two pkt, but has only one pkt id */
2211 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD;
2212 ctrl_para.start_pktid = pkt_id;
2213 ctrl_para.end_pktid = pkt_id;
2214 ctrl_para.pkt_num = 1; /* start from 0 */
2215 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS;
2216 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT;
2217
2218 if (rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true))
2219 return -EFAULT;
2220
2221 return 0;
2222 }
2223
2224 static int
rtw89_debug_priv_fw_crash_get(struct seq_file * m,void * v)2225 rtw89_debug_priv_fw_crash_get(struct seq_file *m, void *v)
2226 {
2227 struct rtw89_debugfs_priv *debugfs_priv = m->private;
2228 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2229
2230 seq_printf(m, "%d\n",
2231 test_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags));
2232 return 0;
2233 }
2234
2235 enum rtw89_dbg_crash_simulation_type {
2236 RTW89_DBG_SIM_CPU_EXCEPTION = 1,
2237 RTW89_DBG_SIM_CTRL_ERROR = 2,
2238 };
2239
2240 static ssize_t
rtw89_debug_priv_fw_crash_set(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)2241 rtw89_debug_priv_fw_crash_set(struct file *filp, const char __user *user_buf,
2242 size_t count, loff_t *loff)
2243 {
2244 struct seq_file *m = (struct seq_file *)filp->private_data;
2245 struct rtw89_debugfs_priv *debugfs_priv = m->private;
2246 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2247 int (*sim)(struct rtw89_dev *rtwdev);
2248 u8 crash_type;
2249 int ret;
2250
2251 ret = kstrtou8_from_user(user_buf, count, 0, &crash_type);
2252 if (ret)
2253 return -EINVAL;
2254
2255 switch (crash_type) {
2256 case RTW89_DBG_SIM_CPU_EXCEPTION:
2257 if (!RTW89_CHK_FW_FEATURE(CRASH_TRIGGER, &rtwdev->fw))
2258 return -EOPNOTSUPP;
2259 sim = rtw89_fw_h2c_trigger_cpu_exception;
2260 break;
2261 case RTW89_DBG_SIM_CTRL_ERROR:
2262 sim = rtw89_dbg_trigger_ctrl_error;
2263 break;
2264 default:
2265 return -EINVAL;
2266 }
2267
2268 mutex_lock(&rtwdev->mutex);
2269 set_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags);
2270 ret = sim(rtwdev);
2271 mutex_unlock(&rtwdev->mutex);
2272
2273 if (ret)
2274 return ret;
2275
2276 return count;
2277 }
2278
rtw89_debug_priv_btc_info_get(struct seq_file * m,void * v)2279 static int rtw89_debug_priv_btc_info_get(struct seq_file *m, void *v)
2280 {
2281 struct rtw89_debugfs_priv *debugfs_priv = m->private;
2282 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2283
2284 rtw89_btc_dump_info(rtwdev, m);
2285
2286 return 0;
2287 }
2288
rtw89_debug_priv_btc_manual_set(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)2289 static ssize_t rtw89_debug_priv_btc_manual_set(struct file *filp,
2290 const char __user *user_buf,
2291 size_t count, loff_t *loff)
2292 {
2293 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
2294 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2295 struct rtw89_btc *btc = &rtwdev->btc;
2296 bool btc_manual;
2297
2298 if (kstrtobool_from_user(user_buf, count, &btc_manual))
2299 goto out;
2300
2301 btc->ctrl.manual = btc_manual;
2302 out:
2303 return count;
2304 }
2305
rtw89_debug_fw_log_btc_manual_set(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)2306 static ssize_t rtw89_debug_fw_log_btc_manual_set(struct file *filp,
2307 const char __user *user_buf,
2308 size_t count, loff_t *loff)
2309 {
2310 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
2311 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2312 struct rtw89_fw_info *fw_info = &rtwdev->fw;
2313 bool fw_log_manual;
2314
2315 if (kstrtobool_from_user(user_buf, count, &fw_log_manual))
2316 goto out;
2317
2318 mutex_lock(&rtwdev->mutex);
2319 fw_info->fw_log_enable = fw_log_manual;
2320 rtw89_fw_h2c_fw_log(rtwdev, fw_log_manual);
2321 mutex_unlock(&rtwdev->mutex);
2322 out:
2323 return count;
2324 }
2325
rtw89_sta_info_get_iter(void * data,struct ieee80211_sta * sta)2326 static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta)
2327 {
2328 static const char * const he_gi_str[] = {
2329 [NL80211_RATE_INFO_HE_GI_0_8] = "0.8",
2330 [NL80211_RATE_INFO_HE_GI_1_6] = "1.6",
2331 [NL80211_RATE_INFO_HE_GI_3_2] = "3.2",
2332 };
2333 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
2334 struct rate_info *rate = &rtwsta->ra_report.txrate;
2335 struct ieee80211_rx_status *status = &rtwsta->rx_status;
2336 struct seq_file *m = (struct seq_file *)data;
2337 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
2338 struct rtw89_hal *hal = &rtwdev->hal;
2339 u8 rssi;
2340 int i;
2341
2342 seq_printf(m, "TX rate [%d]: ", rtwsta->mac_id);
2343
2344 if (rate->flags & RATE_INFO_FLAGS_MCS)
2345 seq_printf(m, "HT MCS-%d%s", rate->mcs,
2346 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : "");
2347 else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS)
2348 seq_printf(m, "VHT %dSS MCS-%d%s", rate->nss, rate->mcs,
2349 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : "");
2350 else if (rate->flags & RATE_INFO_FLAGS_HE_MCS)
2351 seq_printf(m, "HE %dSS MCS-%d GI:%s", rate->nss, rate->mcs,
2352 rate->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ?
2353 he_gi_str[rate->he_gi] : "N/A");
2354 else
2355 seq_printf(m, "Legacy %d", rate->legacy);
2356 seq_printf(m, "%s", rtwsta->ra_report.might_fallback_legacy ? " FB_G" : "");
2357 seq_printf(m, "\t(hw_rate=0x%x)", rtwsta->ra_report.hw_rate);
2358 seq_printf(m, "\t==> agg_wait=%d (%d)\n", rtwsta->max_agg_wait,
2359 sta->deflink.agg.max_rc_amsdu_len);
2360
2361 seq_printf(m, "RX rate [%d]: ", rtwsta->mac_id);
2362
2363 switch (status->encoding) {
2364 case RX_ENC_LEGACY:
2365 seq_printf(m, "Legacy %d", status->rate_idx +
2366 (status->band != NL80211_BAND_2GHZ ? 4 : 0));
2367 break;
2368 case RX_ENC_HT:
2369 seq_printf(m, "HT MCS-%d%s", status->rate_idx,
2370 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : "");
2371 break;
2372 case RX_ENC_VHT:
2373 seq_printf(m, "VHT %dSS MCS-%d%s", status->nss, status->rate_idx,
2374 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : "");
2375 break;
2376 case RX_ENC_HE:
2377 seq_printf(m, "HE %dSS MCS-%d GI:%s", status->nss, status->rate_idx,
2378 status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ?
2379 he_gi_str[rate->he_gi] : "N/A");
2380 break;
2381 }
2382 seq_printf(m, "\t(hw_rate=0x%x)\n", rtwsta->rx_hw_rate);
2383
2384 rssi = ewma_rssi_read(&rtwsta->avg_rssi);
2385 seq_printf(m, "RSSI: %d dBm (raw=%d, prev=%d) [",
2386 RTW89_RSSI_RAW_TO_DBM(rssi), rssi, rtwsta->prev_rssi);
2387 for (i = 0; i < rtwdev->chip->rf_path_num; i++) {
2388 rssi = ewma_rssi_read(&rtwsta->rssi[i]);
2389 seq_printf(m, "%d%s%s", RTW89_RSSI_RAW_TO_DBM(rssi),
2390 hal->tx_path_diversity && (hal->antenna_tx & BIT(i)) ? "*" : "",
2391 i + 1 == rtwdev->chip->rf_path_num ? "" : ", ");
2392 }
2393 seq_puts(m, "]\n");
2394 }
2395
2396 static void
rtw89_debug_append_rx_rate(struct seq_file * m,struct rtw89_pkt_stat * pkt_stat,enum rtw89_hw_rate first_rate,int len)2397 rtw89_debug_append_rx_rate(struct seq_file *m, struct rtw89_pkt_stat *pkt_stat,
2398 enum rtw89_hw_rate first_rate, int len)
2399 {
2400 int i;
2401
2402 for (i = 0; i < len; i++)
2403 seq_printf(m, "%s%u", i == 0 ? "" : ", ",
2404 pkt_stat->rx_rate_cnt[first_rate + i]);
2405 }
2406
2407 static const struct rtw89_rx_rate_cnt_info {
2408 enum rtw89_hw_rate first_rate;
2409 int len;
2410 int ext;
2411 const char *rate_mode;
2412 } rtw89_rx_rate_cnt_infos[] = {
2413 {RTW89_HW_RATE_CCK1, 4, 0, "Legacy:"},
2414 {RTW89_HW_RATE_OFDM6, 8, 0, "OFDM:"},
2415 {RTW89_HW_RATE_MCS0, 8, 0, "HT 0:"},
2416 {RTW89_HW_RATE_MCS8, 8, 0, "HT 1:"},
2417 {RTW89_HW_RATE_VHT_NSS1_MCS0, 10, 2, "VHT 1SS:"},
2418 {RTW89_HW_RATE_VHT_NSS2_MCS0, 10, 2, "VHT 2SS:"},
2419 {RTW89_HW_RATE_HE_NSS1_MCS0, 12, 0, "HE 1SS:"},
2420 {RTW89_HW_RATE_HE_NSS2_MCS0, 12, 0, "HE 2ss:"},
2421 };
2422
rtw89_debug_priv_phy_info_get(struct seq_file * m,void * v)2423 static int rtw89_debug_priv_phy_info_get(struct seq_file *m, void *v)
2424 {
2425 struct rtw89_debugfs_priv *debugfs_priv = m->private;
2426 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2427 struct rtw89_traffic_stats *stats = &rtwdev->stats;
2428 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat;
2429 const struct rtw89_rx_rate_cnt_info *info;
2430 int i;
2431
2432 seq_printf(m, "TP TX: %u [%u] Mbps (lv: %d), RX: %u [%u] Mbps (lv: %d)\n",
2433 stats->tx_throughput, stats->tx_throughput_raw, stats->tx_tfc_lv,
2434 stats->rx_throughput, stats->rx_throughput_raw, stats->rx_tfc_lv);
2435 seq_printf(m, "Beacon: %u, TF: %u\n", pkt_stat->beacon_nr,
2436 stats->rx_tf_periodic);
2437 seq_printf(m, "Avg packet length: TX=%u, RX=%u\n", stats->tx_avg_len,
2438 stats->rx_avg_len);
2439
2440 seq_puts(m, "RX count:\n");
2441 for (i = 0; i < ARRAY_SIZE(rtw89_rx_rate_cnt_infos); i++) {
2442 info = &rtw89_rx_rate_cnt_infos[i];
2443 seq_printf(m, "%10s [", info->rate_mode);
2444 rtw89_debug_append_rx_rate(m, pkt_stat,
2445 info->first_rate, info->len);
2446 if (info->ext) {
2447 seq_puts(m, "][");
2448 rtw89_debug_append_rx_rate(m, pkt_stat,
2449 info->first_rate + info->len, info->ext);
2450 }
2451 seq_puts(m, "]\n");
2452 }
2453
2454 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, m);
2455
2456 return 0;
2457 }
2458
rtw89_dump_addr_cam(struct seq_file * m,struct rtw89_addr_cam_entry * addr_cam)2459 static void rtw89_dump_addr_cam(struct seq_file *m,
2460 struct rtw89_addr_cam_entry *addr_cam)
2461 {
2462 struct rtw89_sec_cam_entry *sec_entry;
2463 int i;
2464
2465 seq_printf(m, "\taddr_cam_idx=%u\n", addr_cam->addr_cam_idx);
2466 seq_printf(m, "\t-> bssid_cam_idx=%u\n", addr_cam->bssid_cam_idx);
2467 seq_printf(m, "\tsec_cam_bitmap=%*ph\n", (int)sizeof(addr_cam->sec_cam_map),
2468 addr_cam->sec_cam_map);
2469 for (i = 0; i < RTW89_SEC_CAM_IN_ADDR_CAM; i++) {
2470 sec_entry = addr_cam->sec_entries[i];
2471 if (!sec_entry)
2472 continue;
2473 seq_printf(m, "\tsec[%d]: sec_cam_idx %u", i, sec_entry->sec_cam_idx);
2474 if (sec_entry->ext_key)
2475 seq_printf(m, ", %u", sec_entry->sec_cam_idx + 1);
2476 seq_puts(m, "\n");
2477 }
2478 }
2479
2480 static
rtw89_vif_ids_get_iter(void * data,u8 * mac,struct ieee80211_vif * vif)2481 void rtw89_vif_ids_get_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
2482 {
2483 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
2484 struct seq_file *m = (struct seq_file *)data;
2485 struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif->bssid_cam;
2486
2487 seq_printf(m, "VIF [%d] %pM\n", rtwvif->mac_id, rtwvif->mac_addr);
2488 seq_printf(m, "\tbssid_cam_idx=%u\n", bssid_cam->bssid_cam_idx);
2489 rtw89_dump_addr_cam(m, &rtwvif->addr_cam);
2490 }
2491
rtw89_dump_ba_cam(struct seq_file * m,struct rtw89_sta * rtwsta)2492 static void rtw89_dump_ba_cam(struct seq_file *m, struct rtw89_sta *rtwsta)
2493 {
2494 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
2495 struct rtw89_dev *rtwdev = rtwvif->rtwdev;
2496 struct rtw89_ba_cam_entry *entry;
2497 bool first = true;
2498
2499 list_for_each_entry(entry, &rtwsta->ba_cam_list, list) {
2500 if (first) {
2501 seq_puts(m, "\tba_cam ");
2502 first = false;
2503 } else {
2504 seq_puts(m, ", ");
2505 }
2506 seq_printf(m, "tid[%u]=%d", entry->tid,
2507 (int)(entry - rtwdev->cam_info.ba_cam_entry));
2508 }
2509 seq_puts(m, "\n");
2510 }
2511
rtw89_sta_ids_get_iter(void * data,struct ieee80211_sta * sta)2512 static void rtw89_sta_ids_get_iter(void *data, struct ieee80211_sta *sta)
2513 {
2514 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
2515 struct seq_file *m = (struct seq_file *)data;
2516
2517 seq_printf(m, "STA [%d] %pM %s\n", rtwsta->mac_id, sta->addr,
2518 sta->tdls ? "(TDLS)" : "");
2519 rtw89_dump_addr_cam(m, &rtwsta->addr_cam);
2520 rtw89_dump_ba_cam(m, rtwsta);
2521 }
2522
rtw89_debug_priv_stations_get(struct seq_file * m,void * v)2523 static int rtw89_debug_priv_stations_get(struct seq_file *m, void *v)
2524 {
2525 struct rtw89_debugfs_priv *debugfs_priv = m->private;
2526 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2527 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
2528
2529 mutex_lock(&rtwdev->mutex);
2530
2531 seq_puts(m, "map:\n");
2532 seq_printf(m, "\tmac_id: %*ph\n", (int)sizeof(rtwdev->mac_id_map),
2533 rtwdev->mac_id_map);
2534 seq_printf(m, "\taddr_cam: %*ph\n", (int)sizeof(cam_info->addr_cam_map),
2535 cam_info->addr_cam_map);
2536 seq_printf(m, "\tbssid_cam: %*ph\n", (int)sizeof(cam_info->bssid_cam_map),
2537 cam_info->bssid_cam_map);
2538 seq_printf(m, "\tsec_cam: %*ph\n", (int)sizeof(cam_info->sec_cam_map),
2539 cam_info->sec_cam_map);
2540 seq_printf(m, "\tba_cam: %*ph\n", (int)sizeof(cam_info->ba_cam_map),
2541 cam_info->ba_cam_map);
2542
2543 ieee80211_iterate_active_interfaces_atomic(rtwdev->hw,
2544 IEEE80211_IFACE_ITER_NORMAL, rtw89_vif_ids_get_iter, m);
2545
2546 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_ids_get_iter, m);
2547
2548 mutex_unlock(&rtwdev->mutex);
2549
2550 return 0;
2551 }
2552
2553 static struct rtw89_debugfs_priv rtw89_debug_priv_read_reg = {
2554 .cb_read = rtw89_debug_priv_read_reg_get,
2555 .cb_write = rtw89_debug_priv_read_reg_select,
2556 };
2557
2558 static struct rtw89_debugfs_priv rtw89_debug_priv_write_reg = {
2559 .cb_write = rtw89_debug_priv_write_reg_set,
2560 };
2561
2562 static struct rtw89_debugfs_priv rtw89_debug_priv_read_rf = {
2563 .cb_read = rtw89_debug_priv_read_rf_get,
2564 .cb_write = rtw89_debug_priv_read_rf_select,
2565 };
2566
2567 static struct rtw89_debugfs_priv rtw89_debug_priv_write_rf = {
2568 .cb_write = rtw89_debug_priv_write_rf_set,
2569 };
2570
2571 static struct rtw89_debugfs_priv rtw89_debug_priv_rf_reg_dump = {
2572 .cb_read = rtw89_debug_priv_rf_reg_dump_get,
2573 };
2574
2575 static struct rtw89_debugfs_priv rtw89_debug_priv_txpwr_table = {
2576 .cb_read = rtw89_debug_priv_txpwr_table_get,
2577 };
2578
2579 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_reg_dump = {
2580 .cb_read = rtw89_debug_priv_mac_reg_dump_get,
2581 .cb_write = rtw89_debug_priv_mac_reg_dump_select,
2582 };
2583
2584 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_mem_dump = {
2585 .cb_read = rtw89_debug_priv_mac_mem_dump_get,
2586 .cb_write = rtw89_debug_priv_mac_mem_dump_select,
2587 };
2588
2589 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_dbg_port_dump = {
2590 .cb_read = rtw89_debug_priv_mac_dbg_port_dump_get,
2591 .cb_write = rtw89_debug_priv_mac_dbg_port_dump_select,
2592 };
2593
2594 static struct rtw89_debugfs_priv rtw89_debug_priv_send_h2c = {
2595 .cb_write = rtw89_debug_priv_send_h2c_set,
2596 };
2597
2598 static struct rtw89_debugfs_priv rtw89_debug_priv_early_h2c = {
2599 .cb_read = rtw89_debug_priv_early_h2c_get,
2600 .cb_write = rtw89_debug_priv_early_h2c_set,
2601 };
2602
2603 static struct rtw89_debugfs_priv rtw89_debug_priv_fw_crash = {
2604 .cb_read = rtw89_debug_priv_fw_crash_get,
2605 .cb_write = rtw89_debug_priv_fw_crash_set,
2606 };
2607
2608 static struct rtw89_debugfs_priv rtw89_debug_priv_btc_info = {
2609 .cb_read = rtw89_debug_priv_btc_info_get,
2610 };
2611
2612 static struct rtw89_debugfs_priv rtw89_debug_priv_btc_manual = {
2613 .cb_write = rtw89_debug_priv_btc_manual_set,
2614 };
2615
2616 static struct rtw89_debugfs_priv rtw89_debug_priv_fw_log_manual = {
2617 .cb_write = rtw89_debug_fw_log_btc_manual_set,
2618 };
2619
2620 static struct rtw89_debugfs_priv rtw89_debug_priv_phy_info = {
2621 .cb_read = rtw89_debug_priv_phy_info_get,
2622 };
2623
2624 static struct rtw89_debugfs_priv rtw89_debug_priv_stations = {
2625 .cb_read = rtw89_debug_priv_stations_get,
2626 };
2627
2628 #define rtw89_debugfs_add(name, mode, fopname, parent) \
2629 do { \
2630 rtw89_debug_priv_ ##name.rtwdev = rtwdev; \
2631 if (!debugfs_create_file(#name, mode, \
2632 parent, &rtw89_debug_priv_ ##name, \
2633 &file_ops_ ##fopname)) \
2634 pr_debug("Unable to initialize debugfs:%s\n", #name); \
2635 } while (0)
2636
2637 #define rtw89_debugfs_add_w(name) \
2638 rtw89_debugfs_add(name, S_IFREG | 0222, single_w, debugfs_topdir)
2639 #define rtw89_debugfs_add_rw(name) \
2640 rtw89_debugfs_add(name, S_IFREG | 0666, common_rw, debugfs_topdir)
2641 #define rtw89_debugfs_add_r(name) \
2642 rtw89_debugfs_add(name, S_IFREG | 0444, single_r, debugfs_topdir)
2643
rtw89_debugfs_init(struct rtw89_dev * rtwdev)2644 void rtw89_debugfs_init(struct rtw89_dev *rtwdev)
2645 {
2646 struct dentry *debugfs_topdir;
2647
2648 debugfs_topdir = debugfs_create_dir("rtw89",
2649 rtwdev->hw->wiphy->debugfsdir);
2650
2651 rtw89_debugfs_add_rw(read_reg);
2652 rtw89_debugfs_add_w(write_reg);
2653 rtw89_debugfs_add_rw(read_rf);
2654 rtw89_debugfs_add_w(write_rf);
2655 rtw89_debugfs_add_r(rf_reg_dump);
2656 rtw89_debugfs_add_r(txpwr_table);
2657 rtw89_debugfs_add_rw(mac_reg_dump);
2658 rtw89_debugfs_add_rw(mac_mem_dump);
2659 rtw89_debugfs_add_rw(mac_dbg_port_dump);
2660 rtw89_debugfs_add_w(send_h2c);
2661 rtw89_debugfs_add_rw(early_h2c);
2662 rtw89_debugfs_add_rw(fw_crash);
2663 rtw89_debugfs_add_r(btc_info);
2664 rtw89_debugfs_add_w(btc_manual);
2665 rtw89_debugfs_add_w(fw_log_manual);
2666 rtw89_debugfs_add_r(phy_info);
2667 rtw89_debugfs_add_r(stations);
2668 }
2669 #endif
2670
2671 #ifdef CONFIG_RTW89_DEBUGMSG
__rtw89_debug(struct rtw89_dev * rtwdev,enum rtw89_debug_mask mask,const char * fmt,...)2672 void __rtw89_debug(struct rtw89_dev *rtwdev,
2673 enum rtw89_debug_mask mask,
2674 const char *fmt, ...)
2675 {
2676 struct va_format vaf = {
2677 .fmt = fmt,
2678 };
2679
2680 va_list args;
2681
2682 va_start(args, fmt);
2683 vaf.va = &args;
2684
2685 if (rtw89_debug_mask & mask)
2686 dev_printk(KERN_DEBUG, rtwdev->dev, "%pV", &vaf);
2687
2688 va_end(args);
2689 }
2690 EXPORT_SYMBOL(__rtw89_debug);
2691 #endif
2692