1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ALPHA_PGTABLE_H
3 #define _ALPHA_PGTABLE_H
4
5 #include <asm-generic/pgtable-nopud.h>
6
7 /*
8 * This file contains the functions and defines necessary to modify and use
9 * the Alpha page table tree.
10 *
11 * This hopefully works with any standard Alpha page-size, as defined
12 * in <asm/page.h> (currently 8192).
13 */
14 #include <linux/mmzone.h>
15
16 #include <asm/page.h>
17 #include <asm/processor.h> /* For TASK_SIZE */
18 #include <asm/machvec.h>
19 #include <asm/setup.h>
20
21 struct mm_struct;
22 struct vm_area_struct;
23
24 /* Certain architectures need to do special things when PTEs
25 * within a page table are directly modified. Thus, the following
26 * hook is made available.
27 */
28 #define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
29 #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
30
31 /* PMD_SHIFT determines the size of the area a second-level page table can map */
32 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3))
33 #define PMD_SIZE (1UL << PMD_SHIFT)
34 #define PMD_MASK (~(PMD_SIZE-1))
35
36 /* PGDIR_SHIFT determines what a third-level page table entry can map */
37 #define PGDIR_SHIFT (PAGE_SHIFT + 2*(PAGE_SHIFT-3))
38 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
39 #define PGDIR_MASK (~(PGDIR_SIZE-1))
40
41 /*
42 * Entries per page directory level: the Alpha is three-level, with
43 * all levels having a one-page page table.
44 */
45 #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3))
46 #define PTRS_PER_PMD (1UL << (PAGE_SHIFT-3))
47 #define PTRS_PER_PGD (1UL << (PAGE_SHIFT-3))
48 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
49
50 /* Number of pointers that fit on a page: this will go away. */
51 #define PTRS_PER_PAGE (1UL << (PAGE_SHIFT-3))
52
53 #ifdef CONFIG_ALPHA_LARGE_VMALLOC
54 #define VMALLOC_START 0xfffffe0000000000
55 #else
56 #define VMALLOC_START (-2*PGDIR_SIZE)
57 #endif
58 #define VMALLOC_END (-PGDIR_SIZE)
59
60 /*
61 * OSF/1 PAL-code-imposed page table bits
62 */
63 #define _PAGE_VALID 0x0001
64 #define _PAGE_FOR 0x0002 /* used for page protection (fault on read) */
65 #define _PAGE_FOW 0x0004 /* used for page protection (fault on write) */
66 #define _PAGE_FOE 0x0008 /* used for page protection (fault on exec) */
67 #define _PAGE_ASM 0x0010
68 #define _PAGE_KRE 0x0100 /* xxx - see below on the "accessed" bit */
69 #define _PAGE_URE 0x0200 /* xxx */
70 #define _PAGE_KWE 0x1000 /* used to do the dirty bit in software */
71 #define _PAGE_UWE 0x2000 /* used to do the dirty bit in software */
72
73 /* .. and these are ours ... */
74 #define _PAGE_DIRTY 0x20000
75 #define _PAGE_ACCESSED 0x40000
76
77 /*
78 * NOTE! The "accessed" bit isn't necessarily exact: it can be kept exactly
79 * by software (use the KRE/URE/KWE/UWE bits appropriately), but I'll fake it.
80 * Under Linux/AXP, the "accessed" bit just means "read", and I'll just use
81 * the KRE/URE bits to watch for it. That way we don't need to overload the
82 * KWE/UWE bits with both handling dirty and accessed.
83 *
84 * Note that the kernel uses the accessed bit just to check whether to page
85 * out a page or not, so it doesn't have to be exact anyway.
86 */
87
88 #define __DIRTY_BITS (_PAGE_DIRTY | _PAGE_KWE | _PAGE_UWE)
89 #define __ACCESS_BITS (_PAGE_ACCESSED | _PAGE_KRE | _PAGE_URE)
90
91 #define _PFN_MASK 0xFFFFFFFF00000000UL
92
93 #define _PAGE_TABLE (_PAGE_VALID | __DIRTY_BITS | __ACCESS_BITS)
94 #define _PAGE_CHG_MASK (_PFN_MASK | __DIRTY_BITS | __ACCESS_BITS)
95
96 /*
97 * All the normal masks have the "page accessed" bits on, as any time they are used,
98 * the page is accessed. They are cleared only by the page-out routines
99 */
100 #define PAGE_NONE __pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOR | _PAGE_FOW | _PAGE_FOE)
101 #define PAGE_SHARED __pgprot(_PAGE_VALID | __ACCESS_BITS)
102 #define PAGE_COPY __pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOW)
103 #define PAGE_READONLY __pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOW)
104 #define PAGE_KERNEL __pgprot(_PAGE_VALID | _PAGE_ASM | _PAGE_KRE | _PAGE_KWE)
105
106 #define _PAGE_NORMAL(x) __pgprot(_PAGE_VALID | __ACCESS_BITS | (x))
107
108 #define _PAGE_P(x) _PAGE_NORMAL((x) | (((x) & _PAGE_FOW)?0:_PAGE_FOW))
109 #define _PAGE_S(x) _PAGE_NORMAL(x)
110
111 /*
112 * The hardware can handle write-only mappings, but as the Alpha
113 * architecture does byte-wide writes with a read-modify-write
114 * sequence, it's not practical to have write-without-read privs.
115 * Thus the "-w- -> rw-" and "-wx -> rwx" mapping here (and in
116 * arch/alpha/mm/fault.c)
117 */
118 /* xwr */
119
120 /*
121 * pgprot_noncached() is only for infiniband pci support, and a real
122 * implementation for RAM would be more complicated.
123 */
124 #define pgprot_noncached(prot) (prot)
125
126 /*
127 * BAD_PAGETABLE is used when we need a bogus page-table, while
128 * BAD_PAGE is used for a bogus page.
129 *
130 * ZERO_PAGE is a global shared page that is always zero: used
131 * for zero-mapped memory areas etc..
132 */
133 extern pte_t __bad_page(void);
134 extern pmd_t * __bad_pagetable(void);
135
136 extern unsigned long __zero_page(void);
137
138 #define BAD_PAGETABLE __bad_pagetable()
139 #define BAD_PAGE __bad_page()
140 #define ZERO_PAGE(vaddr) (virt_to_page(ZERO_PGE))
141
142 /* number of bits that fit into a memory pointer */
143 #define BITS_PER_PTR (8*sizeof(unsigned long))
144
145 /* to align the pointer to a pointer address */
146 #define PTR_MASK (~(sizeof(void*)-1))
147
148 /* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */
149 #define SIZEOF_PTR_LOG2 3
150
151 /* to find an entry in a page-table */
152 #define PAGE_PTR(address) \
153 ((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK)
154
155 /*
156 * On certain platforms whose physical address space can overlap KSEG,
157 * namely EV6 and above, we must re-twiddle the physaddr to restore the
158 * correct high-order bits.
159 *
160 * This is extremely confusing until you realize that this is actually
161 * just working around a userspace bug. The X server was intending to
162 * provide the physical address but instead provided the KSEG address.
163 * Or tried to, except it's not representable.
164 *
165 * On Tsunami there's nothing meaningful at 0x40000000000, so this is
166 * a safe thing to do. Come the first core logic that does put something
167 * in this area -- memory or whathaveyou -- then this hack will have
168 * to go away. So be prepared!
169 */
170
171 #if defined(CONFIG_ALPHA_GENERIC) && defined(USE_48_BIT_KSEG)
172 #error "EV6-only feature in a generic kernel"
173 #endif
174 #if defined(CONFIG_ALPHA_GENERIC) || \
175 (defined(CONFIG_ALPHA_EV6) && !defined(USE_48_BIT_KSEG))
176 #define KSEG_PFN (0xc0000000000UL >> PAGE_SHIFT)
177 #define PHYS_TWIDDLE(pfn) \
178 ((((pfn) & KSEG_PFN) == (0x40000000000UL >> PAGE_SHIFT)) \
179 ? ((pfn) ^= KSEG_PFN) : (pfn))
180 #else
181 #define PHYS_TWIDDLE(pfn) (pfn)
182 #endif
183
184 /*
185 * Conversion functions: convert a page and protection to a page entry,
186 * and a page entry and page directory to the page they refer to.
187 */
188 #define page_to_pa(page) (page_to_pfn(page) << PAGE_SHIFT)
189 #define pte_pfn(pte) (pte_val(pte) >> 32)
190
191 #define pte_page(pte) pfn_to_page(pte_pfn(pte))
192 #define mk_pte(page, pgprot) \
193 ({ \
194 pte_t pte; \
195 \
196 pte_val(pte) = (page_to_pfn(page) << 32) | pgprot_val(pgprot); \
197 pte; \
198 })
199
pfn_pte(unsigned long physpfn,pgprot_t pgprot)200 extern inline pte_t pfn_pte(unsigned long physpfn, pgprot_t pgprot)
201 { pte_t pte; pte_val(pte) = (PHYS_TWIDDLE(physpfn) << 32) | pgprot_val(pgprot); return pte; }
202
pte_modify(pte_t pte,pgprot_t newprot)203 extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
204 { pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
205
pmd_set(pmd_t * pmdp,pte_t * ptep)206 extern inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
207 { pmd_val(*pmdp) = _PAGE_TABLE | ((((unsigned long) ptep) - PAGE_OFFSET) << (32-PAGE_SHIFT)); }
208
pud_set(pud_t * pudp,pmd_t * pmdp)209 extern inline void pud_set(pud_t * pudp, pmd_t * pmdp)
210 { pud_val(*pudp) = _PAGE_TABLE | ((((unsigned long) pmdp) - PAGE_OFFSET) << (32-PAGE_SHIFT)); }
211
212
213 extern inline unsigned long
pmd_page_vaddr(pmd_t pmd)214 pmd_page_vaddr(pmd_t pmd)
215 {
216 return ((pmd_val(pmd) & _PFN_MASK) >> (32-PAGE_SHIFT)) + PAGE_OFFSET;
217 }
218
219 #define pmd_pfn(pmd) (pmd_val(pmd) >> 32)
220 #define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> 32))
221 #define pud_page(pud) (pfn_to_page(pud_val(pud) >> 32))
222
pud_pgtable(pud_t pgd)223 extern inline pmd_t *pud_pgtable(pud_t pgd)
224 {
225 return (pmd_t *)(PAGE_OFFSET + ((pud_val(pgd) & _PFN_MASK) >> (32-PAGE_SHIFT)));
226 }
227
pte_none(pte_t pte)228 extern inline int pte_none(pte_t pte) { return !pte_val(pte); }
pte_present(pte_t pte)229 extern inline int pte_present(pte_t pte) { return pte_val(pte) & _PAGE_VALID; }
pte_clear(struct mm_struct * mm,unsigned long addr,pte_t * ptep)230 extern inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
231 {
232 pte_val(*ptep) = 0;
233 }
234
pmd_none(pmd_t pmd)235 extern inline int pmd_none(pmd_t pmd) { return !pmd_val(pmd); }
pmd_bad(pmd_t pmd)236 extern inline int pmd_bad(pmd_t pmd) { return (pmd_val(pmd) & ~_PFN_MASK) != _PAGE_TABLE; }
pmd_present(pmd_t pmd)237 extern inline int pmd_present(pmd_t pmd) { return pmd_val(pmd) & _PAGE_VALID; }
pmd_clear(pmd_t * pmdp)238 extern inline void pmd_clear(pmd_t * pmdp) { pmd_val(*pmdp) = 0; }
239
pud_none(pud_t pud)240 extern inline int pud_none(pud_t pud) { return !pud_val(pud); }
pud_bad(pud_t pud)241 extern inline int pud_bad(pud_t pud) { return (pud_val(pud) & ~_PFN_MASK) != _PAGE_TABLE; }
pud_present(pud_t pud)242 extern inline int pud_present(pud_t pud) { return pud_val(pud) & _PAGE_VALID; }
pud_clear(pud_t * pudp)243 extern inline void pud_clear(pud_t * pudp) { pud_val(*pudp) = 0; }
244
245 /*
246 * The following only work if pte_present() is true.
247 * Undefined behaviour if not..
248 */
pte_write(pte_t pte)249 extern inline int pte_write(pte_t pte) { return !(pte_val(pte) & _PAGE_FOW); }
pte_dirty(pte_t pte)250 extern inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
pte_young(pte_t pte)251 extern inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
252
pte_wrprotect(pte_t pte)253 extern inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) |= _PAGE_FOW; return pte; }
pte_mkclean(pte_t pte)254 extern inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~(__DIRTY_BITS); return pte; }
pte_mkold(pte_t pte)255 extern inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~(__ACCESS_BITS); return pte; }
pte_mkwrite(pte_t pte)256 extern inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) &= ~_PAGE_FOW; return pte; }
pte_mkdirty(pte_t pte)257 extern inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= __DIRTY_BITS; return pte; }
pte_mkyoung(pte_t pte)258 extern inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= __ACCESS_BITS; return pte; }
259
260 /*
261 * The smp_rmb() in the following functions are required to order the load of
262 * *dir (the pointer in the top level page table) with any subsequent load of
263 * the returned pmd_t *ret (ret is data dependent on *dir).
264 *
265 * If this ordering is not enforced, the CPU might load an older value of
266 * *ret, which may be uninitialized data. See mm/memory.c:__pte_alloc for
267 * more details.
268 *
269 * Note that we never change the mm->pgd pointer after the task is running, so
270 * pgd_offset does not require such a barrier.
271 */
272
273 /* Find an entry in the second-level page table.. */
pmd_offset(pud_t * dir,unsigned long address)274 extern inline pmd_t * pmd_offset(pud_t * dir, unsigned long address)
275 {
276 pmd_t *ret = pud_pgtable(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PAGE - 1));
277 smp_rmb(); /* see above */
278 return ret;
279 }
280 #define pmd_offset pmd_offset
281
282 /* Find an entry in the third-level page table.. */
pte_offset_kernel(pmd_t * dir,unsigned long address)283 extern inline pte_t * pte_offset_kernel(pmd_t * dir, unsigned long address)
284 {
285 pte_t *ret = (pte_t *) pmd_page_vaddr(*dir)
286 + ((address >> PAGE_SHIFT) & (PTRS_PER_PAGE - 1));
287 smp_rmb(); /* see above */
288 return ret;
289 }
290 #define pte_offset_kernel pte_offset_kernel
291
292 extern pgd_t swapper_pg_dir[1024];
293
294 /*
295 * The Alpha doesn't have any external MMU info: the kernel page
296 * tables contain all the necessary information.
297 */
update_mmu_cache(struct vm_area_struct * vma,unsigned long address,pte_t * ptep)298 extern inline void update_mmu_cache(struct vm_area_struct * vma,
299 unsigned long address, pte_t *ptep)
300 {
301 }
302
303 /*
304 * Non-present pages: high 24 bits are offset, next 8 bits type,
305 * low 32 bits zero.
306 */
mk_swap_pte(unsigned long type,unsigned long offset)307 extern inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
308 { pte_t pte; pte_val(pte) = (type << 32) | (offset << 40); return pte; }
309
310 #define __swp_type(x) (((x).val >> 32) & 0xff)
311 #define __swp_offset(x) ((x).val >> 40)
312 #define __swp_entry(type, off) ((swp_entry_t) { pte_val(mk_swap_pte((type), (off))) })
313 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
314 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
315
316 #define kern_addr_valid(addr) (1)
317
318 #define pte_ERROR(e) \
319 printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
320 #define pmd_ERROR(e) \
321 printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
322 #define pgd_ERROR(e) \
323 printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
324
325 extern void paging_init(void);
326
327 /* We have our own get_unmapped_area to cope with ADDR_LIMIT_32BIT. */
328 #define HAVE_ARCH_UNMAPPED_AREA
329
330 #endif /* _ALPHA_PGTABLE_H */
331