1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2022 Intel Corporation
4  */
5 
6 #ifndef __I915_REG_DEFS__
7 #define __I915_REG_DEFS__
8 
9 #include <linux/bitfield.h>
10 #include <linux/bits.h>
11 
12 /**
13  * REG_BIT() - Prepare a u32 bit value
14  * @__n: 0-based bit number
15  *
16  * Local wrapper for BIT() to force u32, with compile time checks.
17  *
18  * @return: Value with bit @__n set.
19  */
20 #define REG_BIT(__n)							\
21 	((u32)(BIT(__n) +						\
22 	       BUILD_BUG_ON_ZERO(__is_constexpr(__n) &&		\
23 				 ((__n) < 0 || (__n) > 31))))
24 
25 /**
26  * REG_GENMASK() - Prepare a continuous u32 bitmask
27  * @__high: 0-based high bit
28  * @__low: 0-based low bit
29  *
30  * Local wrapper for GENMASK() to force u32, with compile time checks.
31  *
32  * @return: Continuous bitmask from @__high to @__low, inclusive.
33  */
34 #define REG_GENMASK(__high, __low)					\
35 	((u32)(GENMASK(__high, __low) +					\
36 	       BUILD_BUG_ON_ZERO(__is_constexpr(__high) &&	\
37 				 __is_constexpr(__low) &&		\
38 				 ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
39 
40 /**
41  * REG_GENMASK64() - Prepare a continuous u64 bitmask
42  * @__high: 0-based high bit
43  * @__low: 0-based low bit
44  *
45  * Local wrapper for GENMASK_ULL() to force u64, with compile time checks.
46  *
47  * @return: Continuous bitmask from @__high to @__low, inclusive.
48  */
49 #define REG_GENMASK64(__high, __low)					\
50 	((u64)(GENMASK_ULL(__high, __low) +				\
51 	       BUILD_BUG_ON_ZERO(__is_constexpr(__high) &&		\
52 				 __is_constexpr(__low) &&		\
53 				 ((__low) < 0 || (__high) > 63 || (__low) > (__high)))))
54 
55 /*
56  * Local integer constant expression version of is_power_of_2().
57  */
58 #define IS_POWER_OF_2(__x)		((__x) && (((__x) & ((__x) - 1)) == 0))
59 
60 /**
61  * REG_FIELD_PREP() - Prepare a u32 bitfield value
62  * @__mask: shifted mask defining the field's length and position
63  * @__val: value to put in the field
64  *
65  * Local copy of FIELD_PREP() to generate an integer constant expression, force
66  * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
67  *
68  * @return: @__val masked and shifted into the field defined by @__mask.
69  */
70 #define REG_FIELD_PREP(__mask, __val)						\
71 	((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) +	\
72 	       BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) +		\
73 	       BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) +		\
74 	       BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
75 	       BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
76 
77 /**
78  * REG_FIELD_GET() - Extract a u32 bitfield value
79  * @__mask: shifted mask defining the field's length and position
80  * @__val: value to extract the bitfield value from
81  *
82  * Local wrapper for FIELD_GET() to force u32 and for consistency with
83  * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
84  *
85  * @return: Masked and shifted value of the field defined by @__mask in @__val.
86  */
87 #define REG_FIELD_GET(__mask, __val)	((u32)FIELD_GET(__mask, __val))
88 
89 /**
90  * REG_FIELD_GET64() - Extract a u64 bitfield value
91  * @__mask: shifted mask defining the field's length and position
92  * @__val: value to extract the bitfield value from
93  *
94  * Local wrapper for FIELD_GET() to force u64 and for consistency with
95  * REG_GENMASK64().
96  *
97  * @return: Masked and shifted value of the field defined by @__mask in @__val.
98  */
99 #define REG_FIELD_GET64(__mask, __val)	((u64)FIELD_GET(__mask, __val))
100 
101 typedef struct {
102 	u32 reg;
103 } i915_reg_t;
104 
105 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
106 
107 #define INVALID_MMIO_REG _MMIO(0)
108 
i915_mmio_reg_offset(i915_reg_t reg)109 static __always_inline u32 i915_mmio_reg_offset(i915_reg_t reg)
110 {
111 	return reg.reg;
112 }
113 
i915_mmio_reg_equal(i915_reg_t a,i915_reg_t b)114 static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
115 {
116 	return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
117 }
118 
i915_mmio_reg_valid(i915_reg_t reg)119 static inline bool i915_mmio_reg_valid(i915_reg_t reg)
120 {
121 	return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
122 }
123 
124 #define VLV_DISPLAY_BASE		0x180000
125 
126 #endif /* __I915_REG_DEFS__ */
127