1 /* SPDX-License-Identifier: GPL-2.0 */
2
3 /*
4 * xHCI host controller driver
5 *
6 * Copyright (C) 2008 Intel Corp.
7 *
8 * Author: Sarah Sharp
9 * Some code borrowed from the Linux EHCI driver.
10 */
11
12 #ifndef __LINUX_XHCI_HCD_H
13 #define __LINUX_XHCI_HCD_H
14
15 #include <linux/usb.h>
16 #include <linux/timer.h>
17 #include <linux/kernel.h>
18 #include <linux/usb/hcd.h>
19 #include <linux/io-64-nonatomic-lo-hi.h>
20
21 /* Code sharing between pci-quirks and xhci hcd */
22 #include "xhci-ext-caps.h"
23 #include "pci-quirks.h"
24
25 /* max buffer size for trace and debug messages */
26 #define XHCI_MSG_MAX 500
27
28 /* xHCI PCI Configuration Registers */
29 #define XHCI_SBRN_OFFSET (0x60)
30
31 /* Max number of USB devices for any host controller - limit in section 6.1 */
32 #define MAX_HC_SLOTS 256
33 /* Section 5.3.3 - MaxPorts */
34 #define MAX_HC_PORTS 127
35
36 /*
37 * xHCI register interface.
38 * This corresponds to the eXtensible Host Controller Interface (xHCI)
39 * Revision 0.95 specification
40 */
41
42 /**
43 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
44 * @hc_capbase: length of the capabilities register and HC version number
45 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
46 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
47 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
48 * @hcc_params: HCCPARAMS - Capability Parameters
49 * @db_off: DBOFF - Doorbell array offset
50 * @run_regs_off: RTSOFF - Runtime register space offset
51 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only
52 */
53 struct xhci_cap_regs {
54 __le32 hc_capbase;
55 __le32 hcs_params1;
56 __le32 hcs_params2;
57 __le32 hcs_params3;
58 __le32 hcc_params;
59 __le32 db_off;
60 __le32 run_regs_off;
61 __le32 hcc_params2; /* xhci 1.1 */
62 /* Reserved up to (CAPLENGTH - 0x1C) */
63 };
64
65 /* hc_capbase bitmasks */
66 /* bits 7:0 - how long is the Capabilities register */
67 #define HC_LENGTH(p) XHCI_HC_LENGTH(p)
68 /* bits 31:16 */
69 #define HC_VERSION(p) (((p) >> 16) & 0xffff)
70
71 /* HCSPARAMS1 - hcs_params1 - bitmasks */
72 /* bits 0:7, Max Device Slots */
73 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
74 #define HCS_SLOTS_MASK 0xff
75 /* bits 8:18, Max Interrupters */
76 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
77 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
78 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
79
80 /* HCSPARAMS2 - hcs_params2 - bitmasks */
81 /* bits 0:3, frames or uframes that SW needs to queue transactions
82 * ahead of the HW to meet periodic deadlines */
83 #define HCS_IST(p) (((p) >> 0) & 0xf)
84 /* bits 4:7, max number of Event Ring segments */
85 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
86 /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */
87 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
88 /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */
89 #define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
90
91 /* HCSPARAMS3 - hcs_params3 - bitmasks */
92 /* bits 0:7, Max U1 to U0 latency for the roothub ports */
93 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
94 /* bits 16:31, Max U2 to U0 latency for the roothub ports */
95 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
96
97 /* HCCPARAMS - hcc_params - bitmasks */
98 /* true: HC can use 64-bit address pointers */
99 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
100 /* true: HC can do bandwidth negotiation */
101 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
102 /* true: HC uses 64-byte Device Context structures
103 * FIXME 64-byte context structures aren't supported yet.
104 */
105 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
106 /* true: HC has port power switches */
107 #define HCC_PPC(p) ((p) & (1 << 3))
108 /* true: HC has port indicators */
109 #define HCS_INDICATOR(p) ((p) & (1 << 4))
110 /* true: HC has Light HC Reset Capability */
111 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
112 /* true: HC supports latency tolerance messaging */
113 #define HCC_LTC(p) ((p) & (1 << 6))
114 /* true: no secondary Stream ID Support */
115 #define HCC_NSS(p) ((p) & (1 << 7))
116 /* true: HC supports Stopped - Short Packet */
117 #define HCC_SPC(p) ((p) & (1 << 9))
118 /* true: HC has Contiguous Frame ID Capability */
119 #define HCC_CFC(p) ((p) & (1 << 11))
120 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
121 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
122 /* Extended Capabilities pointer from PCI base - section 5.3.6 */
123 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
124
125 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
126
127 /* db_off bitmask - bits 0:1 reserved */
128 #define DBOFF_MASK (~0x3)
129
130 /* run_regs_off bitmask - bits 0:4 reserved */
131 #define RTSOFF_MASK (~0x1f)
132
133 /* HCCPARAMS2 - hcc_params2 - bitmasks */
134 /* true: HC supports U3 entry Capability */
135 #define HCC2_U3C(p) ((p) & (1 << 0))
136 /* true: HC supports Configure endpoint command Max exit latency too large */
137 #define HCC2_CMC(p) ((p) & (1 << 1))
138 /* true: HC supports Force Save context Capability */
139 #define HCC2_FSC(p) ((p) & (1 << 2))
140 /* true: HC supports Compliance Transition Capability */
141 #define HCC2_CTC(p) ((p) & (1 << 3))
142 /* true: HC support Large ESIT payload Capability > 48k */
143 #define HCC2_LEC(p) ((p) & (1 << 4))
144 /* true: HC support Configuration Information Capability */
145 #define HCC2_CIC(p) ((p) & (1 << 5))
146 /* true: HC support Extended TBC Capability, Isoc burst count > 65535 */
147 #define HCC2_ETC(p) ((p) & (1 << 6))
148
149 /* Number of registers per port */
150 #define NUM_PORT_REGS 4
151
152 #define PORTSC 0
153 #define PORTPMSC 1
154 #define PORTLI 2
155 #define PORTHLPMC 3
156
157 /**
158 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
159 * @command: USBCMD - xHC command register
160 * @status: USBSTS - xHC status register
161 * @page_size: This indicates the page size that the host controller
162 * supports. If bit n is set, the HC supports a page size
163 * of 2^(n+12), up to a 128MB page size.
164 * 4K is the minimum page size.
165 * @cmd_ring: CRP - 64-bit Command Ring Pointer
166 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
167 * @config_reg: CONFIG - Configure Register
168 * @port_status_base: PORTSCn - base address for Port Status and Control
169 * Each port has a Port Status and Control register,
170 * followed by a Port Power Management Status and Control
171 * register, a Port Link Info register, and a reserved
172 * register.
173 * @port_power_base: PORTPMSCn - base address for
174 * Port Power Management Status and Control
175 * @port_link_base: PORTLIn - base address for Port Link Info (current
176 * Link PM state and control) for USB 2.1 and USB 3.0
177 * devices.
178 */
179 struct xhci_op_regs {
180 __le32 command;
181 __le32 status;
182 __le32 page_size;
183 __le32 reserved1;
184 __le32 reserved2;
185 __le32 dev_notification;
186 __le64 cmd_ring;
187 /* rsvd: offset 0x20-2F */
188 __le32 reserved3[4];
189 __le64 dcbaa_ptr;
190 __le32 config_reg;
191 /* rsvd: offset 0x3C-3FF */
192 __le32 reserved4[241];
193 /* port 1 registers, which serve as a base address for other ports */
194 __le32 port_status_base;
195 __le32 port_power_base;
196 __le32 port_link_base;
197 __le32 reserved5;
198 /* registers for ports 2-255 */
199 __le32 reserved6[NUM_PORT_REGS*254];
200 };
201
202 /* USBCMD - USB command - command bitmasks */
203 /* start/stop HC execution - do not write unless HC is halted*/
204 #define CMD_RUN XHCI_CMD_RUN
205 /* Reset HC - resets internal HC state machine and all registers (except
206 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
207 * The xHCI driver must reinitialize the xHC after setting this bit.
208 */
209 #define CMD_RESET (1 << 1)
210 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
211 #define CMD_EIE XHCI_CMD_EIE
212 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
213 #define CMD_HSEIE XHCI_CMD_HSEIE
214 /* bits 4:6 are reserved (and should be preserved on writes). */
215 /* light reset (port status stays unchanged) - reset completed when this is 0 */
216 #define CMD_LRESET (1 << 7)
217 /* host controller save/restore state. */
218 #define CMD_CSS (1 << 8)
219 #define CMD_CRS (1 << 9)
220 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
221 #define CMD_EWE XHCI_CMD_EWE
222 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
223 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
224 * '0' means the xHC can power it off if all ports are in the disconnect,
225 * disabled, or powered-off state.
226 */
227 #define CMD_PM_INDEX (1 << 11)
228 /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */
229 #define CMD_ETE (1 << 14)
230 /* bits 15:31 are reserved (and should be preserved on writes). */
231
232 #define XHCI_RESET_LONG_USEC (10 * 1000 * 1000)
233 #define XHCI_RESET_SHORT_USEC (250 * 1000)
234
235 /* IMAN - Interrupt Management Register */
236 #define IMAN_IE (1 << 1)
237 #define IMAN_IP (1 << 0)
238
239 /* USBSTS - USB status - status bitmasks */
240 /* HC not running - set to 1 when run/stop bit is cleared. */
241 #define STS_HALT XHCI_STS_HALT
242 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
243 #define STS_FATAL (1 << 2)
244 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
245 #define STS_EINT (1 << 3)
246 /* port change detect */
247 #define STS_PORT (1 << 4)
248 /* bits 5:7 reserved and zeroed */
249 /* save state status - '1' means xHC is saving state */
250 #define STS_SAVE (1 << 8)
251 /* restore state status - '1' means xHC is restoring state */
252 #define STS_RESTORE (1 << 9)
253 /* true: save or restore error */
254 #define STS_SRE (1 << 10)
255 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
256 #define STS_CNR XHCI_STS_CNR
257 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
258 #define STS_HCE (1 << 12)
259 /* bits 13:31 reserved and should be preserved */
260
261 /*
262 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
263 * Generate a device notification event when the HC sees a transaction with a
264 * notification type that matches a bit set in this bit field.
265 */
266 #define DEV_NOTE_MASK (0xffff)
267 #define ENABLE_DEV_NOTE(x) (1 << (x))
268 /* Most of the device notification types should only be used for debug.
269 * SW does need to pay attention to function wake notifications.
270 */
271 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
272
273 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
274 /* bit 0 is the command ring cycle state */
275 /* stop ring operation after completion of the currently executing command */
276 #define CMD_RING_PAUSE (1 << 1)
277 /* stop ring immediately - abort the currently executing command */
278 #define CMD_RING_ABORT (1 << 2)
279 /* true: command ring is running */
280 #define CMD_RING_RUNNING (1 << 3)
281 /* bits 4:5 reserved and should be preserved */
282 /* Command Ring pointer - bit mask for the lower 32 bits. */
283 #define CMD_RING_RSVD_BITS (0x3f)
284
285 /* CONFIG - Configure Register - config_reg bitmasks */
286 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
287 #define MAX_DEVS(p) ((p) & 0xff)
288 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */
289 #define CONFIG_U3E (1 << 8)
290 /* bit 9: Configuration Information Enable, xhci 1.1 */
291 #define CONFIG_CIE (1 << 9)
292 /* bits 10:31 - reserved and should be preserved */
293
294 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
295 /* true: device connected */
296 #define PORT_CONNECT (1 << 0)
297 /* true: port enabled */
298 #define PORT_PE (1 << 1)
299 /* bit 2 reserved and zeroed */
300 /* true: port has an over-current condition */
301 #define PORT_OC (1 << 3)
302 /* true: port reset signaling asserted */
303 #define PORT_RESET (1 << 4)
304 /* Port Link State - bits 5:8
305 * A read gives the current link PM state of the port,
306 * a write with Link State Write Strobe set sets the link state.
307 */
308 #define PORT_PLS_MASK (0xf << 5)
309 #define XDEV_U0 (0x0 << 5)
310 #define XDEV_U1 (0x1 << 5)
311 #define XDEV_U2 (0x2 << 5)
312 #define XDEV_U3 (0x3 << 5)
313 #define XDEV_DISABLED (0x4 << 5)
314 #define XDEV_RXDETECT (0x5 << 5)
315 #define XDEV_INACTIVE (0x6 << 5)
316 #define XDEV_POLLING (0x7 << 5)
317 #define XDEV_RECOVERY (0x8 << 5)
318 #define XDEV_HOT_RESET (0x9 << 5)
319 #define XDEV_COMP_MODE (0xa << 5)
320 #define XDEV_TEST_MODE (0xb << 5)
321 #define XDEV_RESUME (0xf << 5)
322
323 /* true: port has power (see HCC_PPC) */
324 #define PORT_POWER (1 << 9)
325 /* bits 10:13 indicate device speed:
326 * 0 - undefined speed - port hasn't be initialized by a reset yet
327 * 1 - full speed
328 * 2 - low speed
329 * 3 - high speed
330 * 4 - super speed
331 * 5-15 reserved
332 */
333 #define DEV_SPEED_MASK (0xf << 10)
334 #define XDEV_FS (0x1 << 10)
335 #define XDEV_LS (0x2 << 10)
336 #define XDEV_HS (0x3 << 10)
337 #define XDEV_SS (0x4 << 10)
338 #define XDEV_SSP (0x5 << 10)
339 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
340 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
341 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
342 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
343 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
344 #define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP)
345 #define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS)
346 #define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f)
347
348 /* Bits 20:23 in the Slot Context are the speed for the device */
349 #define SLOT_SPEED_FS (XDEV_FS << 10)
350 #define SLOT_SPEED_LS (XDEV_LS << 10)
351 #define SLOT_SPEED_HS (XDEV_HS << 10)
352 #define SLOT_SPEED_SS (XDEV_SS << 10)
353 #define SLOT_SPEED_SSP (XDEV_SSP << 10)
354 /* Port Indicator Control */
355 #define PORT_LED_OFF (0 << 14)
356 #define PORT_LED_AMBER (1 << 14)
357 #define PORT_LED_GREEN (2 << 14)
358 #define PORT_LED_MASK (3 << 14)
359 /* Port Link State Write Strobe - set this when changing link state */
360 #define PORT_LINK_STROBE (1 << 16)
361 /* true: connect status change */
362 #define PORT_CSC (1 << 17)
363 /* true: port enable change */
364 #define PORT_PEC (1 << 18)
365 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
366 * into an enabled state, and the device into the default state. A "warm" reset
367 * also resets the link, forcing the device through the link training sequence.
368 * SW can also look at the Port Reset register to see when warm reset is done.
369 */
370 #define PORT_WRC (1 << 19)
371 /* true: over-current change */
372 #define PORT_OCC (1 << 20)
373 /* true: reset change - 1 to 0 transition of PORT_RESET */
374 #define PORT_RC (1 << 21)
375 /* port link status change - set on some port link state transitions:
376 * Transition Reason
377 * ------------------------------------------------------------------------------
378 * - U3 to Resume Wakeup signaling from a device
379 * - Resume to Recovery to U0 USB 3.0 device resume
380 * - Resume to U0 USB 2.0 device resume
381 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
382 * - U3 to U0 Software resume of USB 2.0 device complete
383 * - U2 to U0 L1 resume of USB 2.1 device complete
384 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
385 * - U0 to disabled L1 entry error with USB 2.1 device
386 * - Any state to inactive Error on USB 3.0 port
387 */
388 #define PORT_PLC (1 << 22)
389 /* port configure error change - port failed to configure its link partner */
390 #define PORT_CEC (1 << 23)
391 #define PORT_CHANGE_MASK (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
392 PORT_RC | PORT_PLC | PORT_CEC)
393
394
395 /* Cold Attach Status - xHC can set this bit to report device attached during
396 * Sx state. Warm port reset should be perfomed to clear this bit and move port
397 * to connected state.
398 */
399 #define PORT_CAS (1 << 24)
400 /* wake on connect (enable) */
401 #define PORT_WKCONN_E (1 << 25)
402 /* wake on disconnect (enable) */
403 #define PORT_WKDISC_E (1 << 26)
404 /* wake on over-current (enable) */
405 #define PORT_WKOC_E (1 << 27)
406 /* bits 28:29 reserved */
407 /* true: device is non-removable - for USB 3.0 roothub emulation */
408 #define PORT_DEV_REMOVE (1 << 30)
409 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
410 #define PORT_WR (1 << 31)
411
412 /* We mark duplicate entries with -1 */
413 #define DUPLICATE_ENTRY ((u8)(-1))
414
415 /* Port Power Management Status and Control - port_power_base bitmasks */
416 /* Inactivity timer value for transitions into U1, in microseconds.
417 * Timeout can be up to 127us. 0xFF means an infinite timeout.
418 */
419 #define PORT_U1_TIMEOUT(p) ((p) & 0xff)
420 #define PORT_U1_TIMEOUT_MASK 0xff
421 /* Inactivity timer value for transitions into U2 */
422 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
423 #define PORT_U2_TIMEOUT_MASK (0xff << 8)
424 /* Bits 24:31 for port testing */
425
426 /* USB2 Protocol PORTSPMSC */
427 #define PORT_L1S_MASK 7
428 #define PORT_L1S_SUCCESS 1
429 #define PORT_RWE (1 << 3)
430 #define PORT_HIRD(p) (((p) & 0xf) << 4)
431 #define PORT_HIRD_MASK (0xf << 4)
432 #define PORT_L1DS_MASK (0xff << 8)
433 #define PORT_L1DS(p) (((p) & 0xff) << 8)
434 #define PORT_HLE (1 << 16)
435 #define PORT_TEST_MODE_SHIFT 28
436
437 /* USB3 Protocol PORTLI Port Link Information */
438 #define PORT_RX_LANES(p) (((p) >> 16) & 0xf)
439 #define PORT_TX_LANES(p) (((p) >> 20) & 0xf)
440
441 /* USB2 Protocol PORTHLPMC */
442 #define PORT_HIRDM(p)((p) & 3)
443 #define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
444 #define PORT_BESLD(p)(((p) & 0xf) << 10)
445
446 /* use 512 microseconds as USB2 LPM L1 default timeout. */
447 #define XHCI_L1_TIMEOUT 512
448
449 /* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency.
450 * Safe to use with mixed HIRD and BESL systems (host and device) and is used
451 * by other operating systems.
452 *
453 * XHCI 1.0 errata 8/14/12 Table 13 notes:
454 * "Software should choose xHC BESL/BESLD field values that do not violate a
455 * device's resume latency requirements,
456 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached,
457 * or not program values < '4' if BLC = '0' and a BESL device is attached.
458 */
459 #define XHCI_DEFAULT_BESL 4
460
461 /*
462 * USB3 specification define a 360ms tPollingLFPSTiemout for USB3 ports
463 * to complete link training. usually link trainig completes much faster
464 * so check status 10 times with 36ms sleep in places we need to wait for
465 * polling to complete.
466 */
467 #define XHCI_PORT_POLLING_LFPS_TIME 36
468
469 /**
470 * struct xhci_intr_reg - Interrupt Register Set
471 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
472 * interrupts and check for pending interrupts.
473 * @irq_control: IMOD - Interrupt Moderation Register.
474 * Used to throttle interrupts.
475 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
476 * @erst_base: ERST base address.
477 * @erst_dequeue: Event ring dequeue pointer.
478 *
479 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
480 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
481 * multiple segments of the same size. The HC places events on the ring and
482 * "updates the Cycle bit in the TRBs to indicate to software the current
483 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
484 * updates the dequeue pointer.
485 */
486 struct xhci_intr_reg {
487 __le32 irq_pending;
488 __le32 irq_control;
489 __le32 erst_size;
490 __le32 rsvd;
491 __le64 erst_base;
492 __le64 erst_dequeue;
493 };
494
495 /* irq_pending bitmasks */
496 #define ER_IRQ_PENDING(p) ((p) & 0x1)
497 /* bits 2:31 need to be preserved */
498 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
499 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
500 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
501 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
502
503 /* irq_control bitmasks */
504 /* Minimum interval between interrupts (in 250ns intervals). The interval
505 * between interrupts will be longer if there are no events on the event ring.
506 * Default is 4000 (1 ms).
507 */
508 #define ER_IRQ_INTERVAL_MASK (0xffff)
509 /* Counter used to count down the time to the next interrupt - HW use only */
510 #define ER_IRQ_COUNTER_MASK (0xffff << 16)
511
512 /* erst_size bitmasks */
513 /* Preserve bits 16:31 of erst_size */
514 #define ERST_SIZE_MASK (0xffff << 16)
515
516 /* erst_base bitmasks */
517 #define ERST_BASE_RSVDP (GENMASK_ULL(5, 0))
518
519 /* erst_dequeue bitmasks */
520 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
521 * where the current dequeue pointer lies. This is an optional HW hint.
522 */
523 #define ERST_DESI_MASK (0x7)
524 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
525 * a work queue (or delayed service routine)?
526 */
527 #define ERST_EHB (1 << 3)
528 #define ERST_PTR_MASK (0xf)
529
530 /**
531 * struct xhci_run_regs
532 * @microframe_index:
533 * MFINDEX - current microframe number
534 *
535 * Section 5.5 Host Controller Runtime Registers:
536 * "Software should read and write these registers using only Dword (32 bit)
537 * or larger accesses"
538 */
539 struct xhci_run_regs {
540 __le32 microframe_index;
541 __le32 rsvd[7];
542 struct xhci_intr_reg ir_set[128];
543 };
544
545 /**
546 * struct doorbell_array
547 *
548 * Bits 0 - 7: Endpoint target
549 * Bits 8 - 15: RsvdZ
550 * Bits 16 - 31: Stream ID
551 *
552 * Section 5.6
553 */
554 struct xhci_doorbell_array {
555 __le32 doorbell[256];
556 };
557
558 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
559 #define DB_VALUE_HOST 0x00000000
560
561 /**
562 * struct xhci_protocol_caps
563 * @revision: major revision, minor revision, capability ID,
564 * and next capability pointer.
565 * @name_string: Four ASCII characters to say which spec this xHC
566 * follows, typically "USB ".
567 * @port_info: Port offset, count, and protocol-defined information.
568 */
569 struct xhci_protocol_caps {
570 u32 revision;
571 u32 name_string;
572 u32 port_info;
573 };
574
575 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
576 #define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff)
577 #define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f)
578 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
579 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
580
581 #define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f)
582 #define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03)
583 #define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03)
584 #define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01)
585 #define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03)
586 #define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff)
587
588 #define PLT_MASK (0x03 << 6)
589 #define PLT_SYM (0x00 << 6)
590 #define PLT_ASYM_RX (0x02 << 6)
591 #define PLT_ASYM_TX (0x03 << 6)
592
593 /**
594 * struct xhci_container_ctx
595 * @type: Type of context. Used to calculated offsets to contained contexts.
596 * @size: Size of the context data
597 * @bytes: The raw context data given to HW
598 * @dma: dma address of the bytes
599 *
600 * Represents either a Device or Input context. Holds a pointer to the raw
601 * memory used for the context (bytes) and dma address of it (dma).
602 */
603 struct xhci_container_ctx {
604 unsigned type;
605 #define XHCI_CTX_TYPE_DEVICE 0x1
606 #define XHCI_CTX_TYPE_INPUT 0x2
607
608 int size;
609
610 u8 *bytes;
611 dma_addr_t dma;
612 };
613
614 /**
615 * struct xhci_slot_ctx
616 * @dev_info: Route string, device speed, hub info, and last valid endpoint
617 * @dev_info2: Max exit latency for device number, root hub port number
618 * @tt_info: tt_info is used to construct split transaction tokens
619 * @dev_state: slot state and device address
620 *
621 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
622 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
623 * reserved at the end of the slot context for HC internal use.
624 */
625 struct xhci_slot_ctx {
626 __le32 dev_info;
627 __le32 dev_info2;
628 __le32 tt_info;
629 __le32 dev_state;
630 /* offset 0x10 to 0x1f reserved for HC internal use */
631 __le32 reserved[4];
632 };
633
634 /* dev_info bitmasks */
635 /* Route String - 0:19 */
636 #define ROUTE_STRING_MASK (0xfffff)
637 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
638 #define DEV_SPEED (0xf << 20)
639 #define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
640 /* bit 24 reserved */
641 /* Is this LS/FS device connected through a HS hub? - bit 25 */
642 #define DEV_MTT (0x1 << 25)
643 /* Set if the device is a hub - bit 26 */
644 #define DEV_HUB (0x1 << 26)
645 /* Index of the last valid endpoint context in this device context - 27:31 */
646 #define LAST_CTX_MASK (0x1f << 27)
647 #define LAST_CTX(p) ((p) << 27)
648 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
649 #define SLOT_FLAG (1 << 0)
650 #define EP0_FLAG (1 << 1)
651
652 /* dev_info2 bitmasks */
653 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
654 #define MAX_EXIT (0xffff)
655 /* Root hub port number that is needed to access the USB device */
656 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
657 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
658 /* Maximum number of ports under a hub device */
659 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
660 #define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24)
661
662 /* tt_info bitmasks */
663 /*
664 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
665 * The Slot ID of the hub that isolates the high speed signaling from
666 * this low or full-speed device. '0' if attached to root hub port.
667 */
668 #define TT_SLOT (0xff)
669 /*
670 * The number of the downstream facing port of the high-speed hub
671 * '0' if the device is not low or full speed.
672 */
673 #define TT_PORT (0xff << 8)
674 #define TT_THINK_TIME(p) (((p) & 0x3) << 16)
675 #define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16)
676
677 /* dev_state bitmasks */
678 /* USB device address - assigned by the HC */
679 #define DEV_ADDR_MASK (0xff)
680 /* bits 8:26 reserved */
681 /* Slot state */
682 #define SLOT_STATE (0x1f << 27)
683 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
684
685 #define SLOT_STATE_DISABLED 0
686 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
687 #define SLOT_STATE_DEFAULT 1
688 #define SLOT_STATE_ADDRESSED 2
689 #define SLOT_STATE_CONFIGURED 3
690
691 /**
692 * struct xhci_ep_ctx
693 * @ep_info: endpoint state, streams, mult, and interval information.
694 * @ep_info2: information on endpoint type, max packet size, max burst size,
695 * error count, and whether the HC will force an event for all
696 * transactions.
697 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
698 * defines one stream, this points to the endpoint transfer ring.
699 * Otherwise, it points to a stream context array, which has a
700 * ring pointer for each flow.
701 * @tx_info:
702 * Average TRB lengths for the endpoint ring and
703 * max payload within an Endpoint Service Interval Time (ESIT).
704 *
705 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
706 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
707 * reserved at the end of the endpoint context for HC internal use.
708 */
709 struct xhci_ep_ctx {
710 __le32 ep_info;
711 __le32 ep_info2;
712 __le64 deq;
713 __le32 tx_info;
714 /* offset 0x14 - 0x1f reserved for HC internal use */
715 __le32 reserved[3];
716 };
717
718 /* ep_info bitmasks */
719 /*
720 * Endpoint State - bits 0:2
721 * 0 - disabled
722 * 1 - running
723 * 2 - halted due to halt condition - ok to manipulate endpoint ring
724 * 3 - stopped
725 * 4 - TRB error
726 * 5-7 - reserved
727 */
728 #define EP_STATE_MASK (0x7)
729 #define EP_STATE_DISABLED 0
730 #define EP_STATE_RUNNING 1
731 #define EP_STATE_HALTED 2
732 #define EP_STATE_STOPPED 3
733 #define EP_STATE_ERROR 4
734 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
735
736 /* Mult - Max number of burtst within an interval, in EP companion desc. */
737 #define EP_MULT(p) (((p) & 0x3) << 8)
738 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
739 /* bits 10:14 are Max Primary Streams */
740 /* bit 15 is Linear Stream Array */
741 /* Interval - period between requests to an endpoint - 125u increments. */
742 #define EP_INTERVAL(p) (((p) & 0xff) << 16)
743 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
744 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
745 #define EP_MAXPSTREAMS_MASK (0x1f << 10)
746 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
747 #define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
748 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
749 #define EP_HAS_LSA (1 << 15)
750 /* hosts with LEC=1 use bits 31:24 as ESIT high bits. */
751 #define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff)
752
753 /* ep_info2 bitmasks */
754 /*
755 * Force Event - generate transfer events for all TRBs for this endpoint
756 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
757 */
758 #define FORCE_EVENT (0x1)
759 #define ERROR_COUNT(p) (((p) & 0x3) << 1)
760 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
761 #define EP_TYPE(p) ((p) << 3)
762 #define ISOC_OUT_EP 1
763 #define BULK_OUT_EP 2
764 #define INT_OUT_EP 3
765 #define CTRL_EP 4
766 #define ISOC_IN_EP 5
767 #define BULK_IN_EP 6
768 #define INT_IN_EP 7
769 /* bit 6 reserved */
770 /* bit 7 is Host Initiate Disable - for disabling stream selection */
771 #define MAX_BURST(p) (((p)&0xff) << 8)
772 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
773 #define MAX_PACKET(p) (((p)&0xffff) << 16)
774 #define MAX_PACKET_MASK (0xffff << 16)
775 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
776
777 /* tx_info bitmasks */
778 #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
779 #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
780 #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24)
781 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
782
783 /* deq bitmasks */
784 #define EP_CTX_CYCLE_MASK (1 << 0)
785 #define SCTX_DEQ_MASK (~0xfL)
786
787
788 /**
789 * struct xhci_input_control_context
790 * Input control context; see section 6.2.5.
791 *
792 * @drop_context: set the bit of the endpoint context you want to disable
793 * @add_context: set the bit of the endpoint context you want to enable
794 */
795 struct xhci_input_control_ctx {
796 __le32 drop_flags;
797 __le32 add_flags;
798 __le32 rsvd2[6];
799 };
800
801 #define EP_IS_ADDED(ctrl_ctx, i) \
802 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
803 #define EP_IS_DROPPED(ctrl_ctx, i) \
804 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
805
806 /* Represents everything that is needed to issue a command on the command ring.
807 * It's useful to pre-allocate these for commands that cannot fail due to
808 * out-of-memory errors, like freeing streams.
809 */
810 struct xhci_command {
811 /* Input context for changing device state */
812 struct xhci_container_ctx *in_ctx;
813 u32 status;
814 int slot_id;
815 /* If completion is null, no one is waiting on this command
816 * and the structure can be freed after the command completes.
817 */
818 struct completion *completion;
819 union xhci_trb *command_trb;
820 struct list_head cmd_list;
821 };
822
823 /* drop context bitmasks */
824 #define DROP_EP(x) (0x1 << x)
825 /* add context bitmasks */
826 #define ADD_EP(x) (0x1 << x)
827
828 struct xhci_stream_ctx {
829 /* 64-bit stream ring address, cycle state, and stream type */
830 __le64 stream_ring;
831 /* offset 0x14 - 0x1f reserved for HC internal use */
832 __le32 reserved[2];
833 };
834
835 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
836 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
837 /* Secondary stream array type, dequeue pointer is to a transfer ring */
838 #define SCT_SEC_TR 0
839 /* Primary stream array type, dequeue pointer is to a transfer ring */
840 #define SCT_PRI_TR 1
841 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
842 #define SCT_SSA_8 2
843 #define SCT_SSA_16 3
844 #define SCT_SSA_32 4
845 #define SCT_SSA_64 5
846 #define SCT_SSA_128 6
847 #define SCT_SSA_256 7
848
849 /* Assume no secondary streams for now */
850 struct xhci_stream_info {
851 struct xhci_ring **stream_rings;
852 /* Number of streams, including stream 0 (which drivers can't use) */
853 unsigned int num_streams;
854 /* The stream context array may be bigger than
855 * the number of streams the driver asked for
856 */
857 struct xhci_stream_ctx *stream_ctx_array;
858 unsigned int num_stream_ctxs;
859 dma_addr_t ctx_array_dma;
860 /* For mapping physical TRB addresses to segments in stream rings */
861 struct radix_tree_root trb_address_map;
862 struct xhci_command *free_streams_command;
863 };
864
865 #define SMALL_STREAM_ARRAY_SIZE 256
866 #define MEDIUM_STREAM_ARRAY_SIZE 1024
867
868 /* Some Intel xHCI host controllers need software to keep track of the bus
869 * bandwidth. Keep track of endpoint info here. Each root port is allocated
870 * the full bus bandwidth. We must also treat TTs (including each port under a
871 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
872 * (DMI) also limits the total bandwidth (across all domains) that can be used.
873 */
874 struct xhci_bw_info {
875 /* ep_interval is zero-based */
876 unsigned int ep_interval;
877 /* mult and num_packets are one-based */
878 unsigned int mult;
879 unsigned int num_packets;
880 unsigned int max_packet_size;
881 unsigned int max_esit_payload;
882 unsigned int type;
883 };
884
885 /* "Block" sizes in bytes the hardware uses for different device speeds.
886 * The logic in this part of the hardware limits the number of bits the hardware
887 * can use, so must represent bandwidth in a less precise manner to mimic what
888 * the scheduler hardware computes.
889 */
890 #define FS_BLOCK 1
891 #define HS_BLOCK 4
892 #define SS_BLOCK 16
893 #define DMI_BLOCK 32
894
895 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
896 * with each byte transferred. SuperSpeed devices have an initial overhead to
897 * set up bursts. These are in blocks, see above. LS overhead has already been
898 * translated into FS blocks.
899 */
900 #define DMI_OVERHEAD 8
901 #define DMI_OVERHEAD_BURST 4
902 #define SS_OVERHEAD 8
903 #define SS_OVERHEAD_BURST 32
904 #define HS_OVERHEAD 26
905 #define FS_OVERHEAD 20
906 #define LS_OVERHEAD 128
907 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per
908 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
909 * of overhead associated with split transfers crossing microframe boundaries.
910 * 31 blocks is pure protocol overhead.
911 */
912 #define TT_HS_OVERHEAD (31 + 94)
913 #define TT_DMI_OVERHEAD (25 + 12)
914
915 /* Bandwidth limits in blocks */
916 #define FS_BW_LIMIT 1285
917 #define TT_BW_LIMIT 1320
918 #define HS_BW_LIMIT 1607
919 #define SS_BW_LIMIT_IN 3906
920 #define DMI_BW_LIMIT_IN 3906
921 #define SS_BW_LIMIT_OUT 3906
922 #define DMI_BW_LIMIT_OUT 3906
923
924 /* Percentage of bus bandwidth reserved for non-periodic transfers */
925 #define FS_BW_RESERVED 10
926 #define HS_BW_RESERVED 20
927 #define SS_BW_RESERVED 10
928
929 struct xhci_virt_ep {
930 struct xhci_virt_device *vdev; /* parent */
931 unsigned int ep_index;
932 struct xhci_ring *ring;
933 /* Related to endpoints that are configured to use stream IDs only */
934 struct xhci_stream_info *stream_info;
935 /* Temporary storage in case the configure endpoint command fails and we
936 * have to restore the device state to the previous state
937 */
938 struct xhci_ring *new_ring;
939 unsigned int err_count;
940 unsigned int ep_state;
941 #define SET_DEQ_PENDING (1 << 0)
942 #define EP_HALTED (1 << 1) /* For stall handling */
943 #define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */
944 /* Transitioning the endpoint to using streams, don't enqueue URBs */
945 #define EP_GETTING_STREAMS (1 << 3)
946 #define EP_HAS_STREAMS (1 << 4)
947 /* Transitioning the endpoint to not using streams, don't enqueue URBs */
948 #define EP_GETTING_NO_STREAMS (1 << 5)
949 #define EP_HARD_CLEAR_TOGGLE (1 << 6)
950 #define EP_SOFT_CLEAR_TOGGLE (1 << 7)
951 /* usb_hub_clear_tt_buffer is in progress */
952 #define EP_CLEARING_TT (1 << 8)
953 /* ---- Related to URB cancellation ---- */
954 struct list_head cancelled_td_list;
955 struct xhci_hcd *xhci;
956 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
957 * command. We'll need to update the ring's dequeue segment and dequeue
958 * pointer after the command completes.
959 */
960 struct xhci_segment *queued_deq_seg;
961 union xhci_trb *queued_deq_ptr;
962 /*
963 * Sometimes the xHC can not process isochronous endpoint ring quickly
964 * enough, and it will miss some isoc tds on the ring and generate
965 * a Missed Service Error Event.
966 * Set skip flag when receive a Missed Service Error Event and
967 * process the missed tds on the endpoint ring.
968 */
969 bool skip;
970 /* Bandwidth checking storage */
971 struct xhci_bw_info bw_info;
972 struct list_head bw_endpoint_list;
973 /* Isoch Frame ID checking storage */
974 int next_frame_id;
975 /* Use new Isoch TRB layout needed for extended TBC support */
976 bool use_extended_tbc;
977 };
978
979 enum xhci_overhead_type {
980 LS_OVERHEAD_TYPE = 0,
981 FS_OVERHEAD_TYPE,
982 HS_OVERHEAD_TYPE,
983 };
984
985 struct xhci_interval_bw {
986 unsigned int num_packets;
987 /* Sorted by max packet size.
988 * Head of the list is the greatest max packet size.
989 */
990 struct list_head endpoints;
991 /* How many endpoints of each speed are present. */
992 unsigned int overhead[3];
993 };
994
995 #define XHCI_MAX_INTERVAL 16
996
997 struct xhci_interval_bw_table {
998 unsigned int interval0_esit_payload;
999 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
1000 /* Includes reserved bandwidth for async endpoints */
1001 unsigned int bw_used;
1002 unsigned int ss_bw_in;
1003 unsigned int ss_bw_out;
1004 };
1005
1006 #define EP_CTX_PER_DEV 31
1007
1008 struct xhci_virt_device {
1009 int slot_id;
1010 struct usb_device *udev;
1011 /*
1012 * Commands to the hardware are passed an "input context" that
1013 * tells the hardware what to change in its data structures.
1014 * The hardware will return changes in an "output context" that
1015 * software must allocate for the hardware. We need to keep
1016 * track of input and output contexts separately because
1017 * these commands might fail and we don't trust the hardware.
1018 */
1019 struct xhci_container_ctx *out_ctx;
1020 /* Used for addressing devices and configuration changes */
1021 struct xhci_container_ctx *in_ctx;
1022 struct xhci_virt_ep eps[EP_CTX_PER_DEV];
1023 u8 fake_port;
1024 u8 real_port;
1025 struct xhci_interval_bw_table *bw_table;
1026 struct xhci_tt_bw_info *tt_info;
1027 /*
1028 * flags for state tracking based on events and issued commands.
1029 * Software can not rely on states from output contexts because of
1030 * latency between events and xHC updating output context values.
1031 * See xhci 1.1 section 4.8.3 for more details
1032 */
1033 unsigned long flags;
1034 #define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */
1035
1036 /* The current max exit latency for the enabled USB3 link states. */
1037 u16 current_mel;
1038 /* Used for the debugfs interfaces. */
1039 void *debugfs_private;
1040 };
1041
1042 /*
1043 * For each roothub, keep track of the bandwidth information for each periodic
1044 * interval.
1045 *
1046 * If a high speed hub is attached to the roothub, each TT associated with that
1047 * hub is a separate bandwidth domain. The interval information for the
1048 * endpoints on the devices under that TT will appear in the TT structure.
1049 */
1050 struct xhci_root_port_bw_info {
1051 struct list_head tts;
1052 unsigned int num_active_tts;
1053 struct xhci_interval_bw_table bw_table;
1054 };
1055
1056 struct xhci_tt_bw_info {
1057 struct list_head tt_list;
1058 int slot_id;
1059 int ttport;
1060 struct xhci_interval_bw_table bw_table;
1061 int active_eps;
1062 };
1063
1064
1065 /**
1066 * struct xhci_device_context_array
1067 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
1068 */
1069 struct xhci_device_context_array {
1070 /* 64-bit device addresses; we only write 32-bit addresses */
1071 __le64 dev_context_ptrs[MAX_HC_SLOTS];
1072 /* private xHCD pointers */
1073 dma_addr_t dma;
1074 };
1075 /* TODO: write function to set the 64-bit device DMA address */
1076 /*
1077 * TODO: change this to be dynamically sized at HC mem init time since the HC
1078 * might not be able to handle the maximum number of devices possible.
1079 */
1080
1081
1082 struct xhci_transfer_event {
1083 /* 64-bit buffer address, or immediate data */
1084 __le64 buffer;
1085 __le32 transfer_len;
1086 /* This field is interpreted differently based on the type of TRB */
1087 __le32 flags;
1088 };
1089
1090 /* Transfer event TRB length bit mask */
1091 /* bits 0:23 */
1092 #define EVENT_TRB_LEN(p) ((p) & 0xffffff)
1093
1094 /** Transfer Event bit fields **/
1095 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
1096
1097 /* Completion Code - only applicable for some types of TRBs */
1098 #define COMP_CODE_MASK (0xff << 24)
1099 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
1100 #define COMP_INVALID 0
1101 #define COMP_SUCCESS 1
1102 #define COMP_DATA_BUFFER_ERROR 2
1103 #define COMP_BABBLE_DETECTED_ERROR 3
1104 #define COMP_USB_TRANSACTION_ERROR 4
1105 #define COMP_TRB_ERROR 5
1106 #define COMP_STALL_ERROR 6
1107 #define COMP_RESOURCE_ERROR 7
1108 #define COMP_BANDWIDTH_ERROR 8
1109 #define COMP_NO_SLOTS_AVAILABLE_ERROR 9
1110 #define COMP_INVALID_STREAM_TYPE_ERROR 10
1111 #define COMP_SLOT_NOT_ENABLED_ERROR 11
1112 #define COMP_ENDPOINT_NOT_ENABLED_ERROR 12
1113 #define COMP_SHORT_PACKET 13
1114 #define COMP_RING_UNDERRUN 14
1115 #define COMP_RING_OVERRUN 15
1116 #define COMP_VF_EVENT_RING_FULL_ERROR 16
1117 #define COMP_PARAMETER_ERROR 17
1118 #define COMP_BANDWIDTH_OVERRUN_ERROR 18
1119 #define COMP_CONTEXT_STATE_ERROR 19
1120 #define COMP_NO_PING_RESPONSE_ERROR 20
1121 #define COMP_EVENT_RING_FULL_ERROR 21
1122 #define COMP_INCOMPATIBLE_DEVICE_ERROR 22
1123 #define COMP_MISSED_SERVICE_ERROR 23
1124 #define COMP_COMMAND_RING_STOPPED 24
1125 #define COMP_COMMAND_ABORTED 25
1126 #define COMP_STOPPED 26
1127 #define COMP_STOPPED_LENGTH_INVALID 27
1128 #define COMP_STOPPED_SHORT_PACKET 28
1129 #define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29
1130 #define COMP_ISOCH_BUFFER_OVERRUN 31
1131 #define COMP_EVENT_LOST_ERROR 32
1132 #define COMP_UNDEFINED_ERROR 33
1133 #define COMP_INVALID_STREAM_ID_ERROR 34
1134 #define COMP_SECONDARY_BANDWIDTH_ERROR 35
1135 #define COMP_SPLIT_TRANSACTION_ERROR 36
1136
xhci_trb_comp_code_string(u8 status)1137 static inline const char *xhci_trb_comp_code_string(u8 status)
1138 {
1139 switch (status) {
1140 case COMP_INVALID:
1141 return "Invalid";
1142 case COMP_SUCCESS:
1143 return "Success";
1144 case COMP_DATA_BUFFER_ERROR:
1145 return "Data Buffer Error";
1146 case COMP_BABBLE_DETECTED_ERROR:
1147 return "Babble Detected";
1148 case COMP_USB_TRANSACTION_ERROR:
1149 return "USB Transaction Error";
1150 case COMP_TRB_ERROR:
1151 return "TRB Error";
1152 case COMP_STALL_ERROR:
1153 return "Stall Error";
1154 case COMP_RESOURCE_ERROR:
1155 return "Resource Error";
1156 case COMP_BANDWIDTH_ERROR:
1157 return "Bandwidth Error";
1158 case COMP_NO_SLOTS_AVAILABLE_ERROR:
1159 return "No Slots Available Error";
1160 case COMP_INVALID_STREAM_TYPE_ERROR:
1161 return "Invalid Stream Type Error";
1162 case COMP_SLOT_NOT_ENABLED_ERROR:
1163 return "Slot Not Enabled Error";
1164 case COMP_ENDPOINT_NOT_ENABLED_ERROR:
1165 return "Endpoint Not Enabled Error";
1166 case COMP_SHORT_PACKET:
1167 return "Short Packet";
1168 case COMP_RING_UNDERRUN:
1169 return "Ring Underrun";
1170 case COMP_RING_OVERRUN:
1171 return "Ring Overrun";
1172 case COMP_VF_EVENT_RING_FULL_ERROR:
1173 return "VF Event Ring Full Error";
1174 case COMP_PARAMETER_ERROR:
1175 return "Parameter Error";
1176 case COMP_BANDWIDTH_OVERRUN_ERROR:
1177 return "Bandwidth Overrun Error";
1178 case COMP_CONTEXT_STATE_ERROR:
1179 return "Context State Error";
1180 case COMP_NO_PING_RESPONSE_ERROR:
1181 return "No Ping Response Error";
1182 case COMP_EVENT_RING_FULL_ERROR:
1183 return "Event Ring Full Error";
1184 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1185 return "Incompatible Device Error";
1186 case COMP_MISSED_SERVICE_ERROR:
1187 return "Missed Service Error";
1188 case COMP_COMMAND_RING_STOPPED:
1189 return "Command Ring Stopped";
1190 case COMP_COMMAND_ABORTED:
1191 return "Command Aborted";
1192 case COMP_STOPPED:
1193 return "Stopped";
1194 case COMP_STOPPED_LENGTH_INVALID:
1195 return "Stopped - Length Invalid";
1196 case COMP_STOPPED_SHORT_PACKET:
1197 return "Stopped - Short Packet";
1198 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
1199 return "Max Exit Latency Too Large Error";
1200 case COMP_ISOCH_BUFFER_OVERRUN:
1201 return "Isoch Buffer Overrun";
1202 case COMP_EVENT_LOST_ERROR:
1203 return "Event Lost Error";
1204 case COMP_UNDEFINED_ERROR:
1205 return "Undefined Error";
1206 case COMP_INVALID_STREAM_ID_ERROR:
1207 return "Invalid Stream ID Error";
1208 case COMP_SECONDARY_BANDWIDTH_ERROR:
1209 return "Secondary Bandwidth Error";
1210 case COMP_SPLIT_TRANSACTION_ERROR:
1211 return "Split Transaction Error";
1212 default:
1213 return "Unknown!!";
1214 }
1215 }
1216
1217 struct xhci_link_trb {
1218 /* 64-bit segment pointer*/
1219 __le64 segment_ptr;
1220 __le32 intr_target;
1221 __le32 control;
1222 };
1223
1224 /* control bitfields */
1225 #define LINK_TOGGLE (0x1<<1)
1226
1227 /* Command completion event TRB */
1228 struct xhci_event_cmd {
1229 /* Pointer to command TRB, or the value passed by the event data trb */
1230 __le64 cmd_trb;
1231 __le32 status;
1232 __le32 flags;
1233 };
1234
1235 /* flags bitmasks */
1236
1237 /* Address device - disable SetAddress */
1238 #define TRB_BSR (1<<9)
1239
1240 /* Configure Endpoint - Deconfigure */
1241 #define TRB_DC (1<<9)
1242
1243 /* Stop Ring - Transfer State Preserve */
1244 #define TRB_TSP (1<<9)
1245
1246 enum xhci_ep_reset_type {
1247 EP_HARD_RESET,
1248 EP_SOFT_RESET,
1249 };
1250
1251 /* Force Event */
1252 #define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22)
1253 #define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16)
1254
1255 /* Set Latency Tolerance Value */
1256 #define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16)
1257
1258 /* Get Port Bandwidth */
1259 #define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16)
1260
1261 /* Force Header */
1262 #define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f)
1263 #define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24)
1264
1265 enum xhci_setup_dev {
1266 SETUP_CONTEXT_ONLY,
1267 SETUP_CONTEXT_ADDRESS,
1268 };
1269
1270 /* bits 16:23 are the virtual function ID */
1271 /* bits 24:31 are the slot ID */
1272 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1273 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1274
1275 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1276 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1277 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1278
1279 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1280 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1281 #define LAST_EP_INDEX 30
1282
1283 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */
1284 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1285 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1286 #define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
1287
1288 /* Link TRB specific fields */
1289 #define TRB_TC (1<<1)
1290
1291 /* Port Status Change Event TRB fields */
1292 /* Port ID - bits 31:24 */
1293 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1294
1295 #define EVENT_DATA (1 << 2)
1296
1297 /* Normal TRB fields */
1298 /* transfer_len bitmasks - bits 0:16 */
1299 #define TRB_LEN(p) ((p) & 0x1ffff)
1300 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */
1301 #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
1302 #define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17)
1303 /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */
1304 #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17)
1305 /* Interrupter Target - which MSI-X vector to target the completion event at */
1306 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1307 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1308 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */
1309 #define TRB_TBC(p) (((p) & 0x3) << 7)
1310 #define TRB_TLBPC(p) (((p) & 0xf) << 16)
1311
1312 /* Cycle bit - indicates TRB ownership by HC or HCD */
1313 #define TRB_CYCLE (1<<0)
1314 /*
1315 * Force next event data TRB to be evaluated before task switch.
1316 * Used to pass OS data back after a TD completes.
1317 */
1318 #define TRB_ENT (1<<1)
1319 /* Interrupt on short packet */
1320 #define TRB_ISP (1<<2)
1321 /* Set PCIe no snoop attribute */
1322 #define TRB_NO_SNOOP (1<<3)
1323 /* Chain multiple TRBs into a TD */
1324 #define TRB_CHAIN (1<<4)
1325 /* Interrupt on completion */
1326 #define TRB_IOC (1<<5)
1327 /* The buffer pointer contains immediate data */
1328 #define TRB_IDT (1<<6)
1329 /* TDs smaller than this might use IDT */
1330 #define TRB_IDT_MAX_SIZE 8
1331
1332 /* Block Event Interrupt */
1333 #define TRB_BEI (1<<9)
1334
1335 /* Control transfer TRB specific fields */
1336 #define TRB_DIR_IN (1<<16)
1337 #define TRB_TX_TYPE(p) ((p) << 16)
1338 #define TRB_DATA_OUT 2
1339 #define TRB_DATA_IN 3
1340
1341 /* Isochronous TRB specific fields */
1342 #define TRB_SIA (1<<31)
1343 #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
1344
1345 /* TRB cache size for xHC with TRB cache */
1346 #define TRB_CACHE_SIZE_HS 8
1347 #define TRB_CACHE_SIZE_SS 16
1348
1349 struct xhci_generic_trb {
1350 __le32 field[4];
1351 };
1352
1353 union xhci_trb {
1354 struct xhci_link_trb link;
1355 struct xhci_transfer_event trans_event;
1356 struct xhci_event_cmd event_cmd;
1357 struct xhci_generic_trb generic;
1358 };
1359
1360 /* TRB bit mask */
1361 #define TRB_TYPE_BITMASK (0xfc00)
1362 #define TRB_TYPE(p) ((p) << 10)
1363 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1364 /* TRB type IDs */
1365 /* bulk, interrupt, isoc scatter/gather, and control data stage */
1366 #define TRB_NORMAL 1
1367 /* setup stage for control transfers */
1368 #define TRB_SETUP 2
1369 /* data stage for control transfers */
1370 #define TRB_DATA 3
1371 /* status stage for control transfers */
1372 #define TRB_STATUS 4
1373 /* isoc transfers */
1374 #define TRB_ISOC 5
1375 /* TRB for linking ring segments */
1376 #define TRB_LINK 6
1377 #define TRB_EVENT_DATA 7
1378 /* Transfer Ring No-op (not for the command ring) */
1379 #define TRB_TR_NOOP 8
1380 /* Command TRBs */
1381 /* Enable Slot Command */
1382 #define TRB_ENABLE_SLOT 9
1383 /* Disable Slot Command */
1384 #define TRB_DISABLE_SLOT 10
1385 /* Address Device Command */
1386 #define TRB_ADDR_DEV 11
1387 /* Configure Endpoint Command */
1388 #define TRB_CONFIG_EP 12
1389 /* Evaluate Context Command */
1390 #define TRB_EVAL_CONTEXT 13
1391 /* Reset Endpoint Command */
1392 #define TRB_RESET_EP 14
1393 /* Stop Transfer Ring Command */
1394 #define TRB_STOP_RING 15
1395 /* Set Transfer Ring Dequeue Pointer Command */
1396 #define TRB_SET_DEQ 16
1397 /* Reset Device Command */
1398 #define TRB_RESET_DEV 17
1399 /* Force Event Command (opt) */
1400 #define TRB_FORCE_EVENT 18
1401 /* Negotiate Bandwidth Command (opt) */
1402 #define TRB_NEG_BANDWIDTH 19
1403 /* Set Latency Tolerance Value Command (opt) */
1404 #define TRB_SET_LT 20
1405 /* Get port bandwidth Command */
1406 #define TRB_GET_BW 21
1407 /* Force Header Command - generate a transaction or link management packet */
1408 #define TRB_FORCE_HEADER 22
1409 /* No-op Command - not for transfer rings */
1410 #define TRB_CMD_NOOP 23
1411 /* TRB IDs 24-31 reserved */
1412 /* Event TRBS */
1413 /* Transfer Event */
1414 #define TRB_TRANSFER 32
1415 /* Command Completion Event */
1416 #define TRB_COMPLETION 33
1417 /* Port Status Change Event */
1418 #define TRB_PORT_STATUS 34
1419 /* Bandwidth Request Event (opt) */
1420 #define TRB_BANDWIDTH_EVENT 35
1421 /* Doorbell Event (opt) */
1422 #define TRB_DOORBELL 36
1423 /* Host Controller Event */
1424 #define TRB_HC_EVENT 37
1425 /* Device Notification Event - device sent function wake notification */
1426 #define TRB_DEV_NOTE 38
1427 /* MFINDEX Wrap Event - microframe counter wrapped */
1428 #define TRB_MFINDEX_WRAP 39
1429 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1430 #define TRB_VENDOR_DEFINED_LOW 48
1431 /* Nec vendor-specific command completion event. */
1432 #define TRB_NEC_CMD_COMP 48
1433 /* Get NEC firmware revision. */
1434 #define TRB_NEC_GET_FW 49
1435
xhci_trb_type_string(u8 type)1436 static inline const char *xhci_trb_type_string(u8 type)
1437 {
1438 switch (type) {
1439 case TRB_NORMAL:
1440 return "Normal";
1441 case TRB_SETUP:
1442 return "Setup Stage";
1443 case TRB_DATA:
1444 return "Data Stage";
1445 case TRB_STATUS:
1446 return "Status Stage";
1447 case TRB_ISOC:
1448 return "Isoch";
1449 case TRB_LINK:
1450 return "Link";
1451 case TRB_EVENT_DATA:
1452 return "Event Data";
1453 case TRB_TR_NOOP:
1454 return "No-Op";
1455 case TRB_ENABLE_SLOT:
1456 return "Enable Slot Command";
1457 case TRB_DISABLE_SLOT:
1458 return "Disable Slot Command";
1459 case TRB_ADDR_DEV:
1460 return "Address Device Command";
1461 case TRB_CONFIG_EP:
1462 return "Configure Endpoint Command";
1463 case TRB_EVAL_CONTEXT:
1464 return "Evaluate Context Command";
1465 case TRB_RESET_EP:
1466 return "Reset Endpoint Command";
1467 case TRB_STOP_RING:
1468 return "Stop Ring Command";
1469 case TRB_SET_DEQ:
1470 return "Set TR Dequeue Pointer Command";
1471 case TRB_RESET_DEV:
1472 return "Reset Device Command";
1473 case TRB_FORCE_EVENT:
1474 return "Force Event Command";
1475 case TRB_NEG_BANDWIDTH:
1476 return "Negotiate Bandwidth Command";
1477 case TRB_SET_LT:
1478 return "Set Latency Tolerance Value Command";
1479 case TRB_GET_BW:
1480 return "Get Port Bandwidth Command";
1481 case TRB_FORCE_HEADER:
1482 return "Force Header Command";
1483 case TRB_CMD_NOOP:
1484 return "No-Op Command";
1485 case TRB_TRANSFER:
1486 return "Transfer Event";
1487 case TRB_COMPLETION:
1488 return "Command Completion Event";
1489 case TRB_PORT_STATUS:
1490 return "Port Status Change Event";
1491 case TRB_BANDWIDTH_EVENT:
1492 return "Bandwidth Request Event";
1493 case TRB_DOORBELL:
1494 return "Doorbell Event";
1495 case TRB_HC_EVENT:
1496 return "Host Controller Event";
1497 case TRB_DEV_NOTE:
1498 return "Device Notification Event";
1499 case TRB_MFINDEX_WRAP:
1500 return "MFINDEX Wrap Event";
1501 case TRB_NEC_CMD_COMP:
1502 return "NEC Command Completion Event";
1503 case TRB_NEC_GET_FW:
1504 return "NET Get Firmware Revision Command";
1505 default:
1506 return "UNKNOWN";
1507 }
1508 }
1509
1510 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1511 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1512 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1513 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1514 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1515 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1516
1517 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1518 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1519
1520 /*
1521 * TRBS_PER_SEGMENT must be a multiple of 4,
1522 * since the command ring is 64-byte aligned.
1523 * It must also be greater than 16.
1524 */
1525 #define TRBS_PER_SEGMENT 256
1526 /* Allow two commands + a link TRB, along with any reserved command TRBs */
1527 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1528 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1529 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1530 /* TRB buffer pointers can't cross 64KB boundaries */
1531 #define TRB_MAX_BUFF_SHIFT 16
1532 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1533 /* How much data is left before the 64KB boundary? */
1534 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1535 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1536 #define MAX_SOFT_RETRY 3
1537 /*
1538 * Limits of consecutive isoc trbs that can Block Event Interrupt (BEI) if
1539 * XHCI_AVOID_BEI quirk is in use.
1540 */
1541 #define AVOID_BEI_INTERVAL_MIN 8
1542 #define AVOID_BEI_INTERVAL_MAX 32
1543
1544 struct xhci_segment {
1545 union xhci_trb *trbs;
1546 /* private to HCD */
1547 struct xhci_segment *next;
1548 dma_addr_t dma;
1549 /* Max packet sized bounce buffer for td-fragmant alignment */
1550 dma_addr_t bounce_dma;
1551 void *bounce_buf;
1552 unsigned int bounce_offs;
1553 unsigned int bounce_len;
1554 };
1555
1556 enum xhci_cancelled_td_status {
1557 TD_DIRTY = 0,
1558 TD_HALTED,
1559 TD_CLEARING_CACHE,
1560 TD_CLEARED,
1561 };
1562
1563 struct xhci_td {
1564 struct list_head td_list;
1565 struct list_head cancelled_td_list;
1566 int status;
1567 enum xhci_cancelled_td_status cancel_status;
1568 struct urb *urb;
1569 struct xhci_segment *start_seg;
1570 union xhci_trb *first_trb;
1571 union xhci_trb *last_trb;
1572 struct xhci_segment *last_trb_seg;
1573 struct xhci_segment *bounce_seg;
1574 /* actual_length of the URB has already been set */
1575 bool urb_length_set;
1576 bool error_mid_td;
1577 unsigned int num_trbs;
1578 };
1579
1580 /* xHCI command default timeout value */
1581 #define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ)
1582
1583 /* command descriptor */
1584 struct xhci_cd {
1585 struct xhci_command *command;
1586 union xhci_trb *cmd_trb;
1587 };
1588
1589 enum xhci_ring_type {
1590 TYPE_CTRL = 0,
1591 TYPE_ISOC,
1592 TYPE_BULK,
1593 TYPE_INTR,
1594 TYPE_STREAM,
1595 TYPE_COMMAND,
1596 TYPE_EVENT,
1597 };
1598
xhci_ring_type_string(enum xhci_ring_type type)1599 static inline const char *xhci_ring_type_string(enum xhci_ring_type type)
1600 {
1601 switch (type) {
1602 case TYPE_CTRL:
1603 return "CTRL";
1604 case TYPE_ISOC:
1605 return "ISOC";
1606 case TYPE_BULK:
1607 return "BULK";
1608 case TYPE_INTR:
1609 return "INTR";
1610 case TYPE_STREAM:
1611 return "STREAM";
1612 case TYPE_COMMAND:
1613 return "CMD";
1614 case TYPE_EVENT:
1615 return "EVENT";
1616 }
1617
1618 return "UNKNOWN";
1619 }
1620
1621 struct xhci_ring {
1622 struct xhci_segment *first_seg;
1623 struct xhci_segment *last_seg;
1624 union xhci_trb *enqueue;
1625 struct xhci_segment *enq_seg;
1626 union xhci_trb *dequeue;
1627 struct xhci_segment *deq_seg;
1628 struct list_head td_list;
1629 /*
1630 * Write the cycle state into the TRB cycle field to give ownership of
1631 * the TRB to the host controller (if we are the producer), or to check
1632 * if we own the TRB (if we are the consumer). See section 4.9.1.
1633 */
1634 u32 cycle_state;
1635 unsigned int stream_id;
1636 unsigned int num_segs;
1637 unsigned int num_trbs_free; /* used only by xhci DbC */
1638 unsigned int bounce_buf_len;
1639 enum xhci_ring_type type;
1640 bool last_td_was_short;
1641 struct radix_tree_root *trb_address_map;
1642 };
1643
1644 struct xhci_erst_entry {
1645 /* 64-bit event ring segment address */
1646 __le64 seg_addr;
1647 __le32 seg_size;
1648 /* Set to zero */
1649 __le32 rsvd;
1650 };
1651
1652 struct xhci_erst {
1653 struct xhci_erst_entry *entries;
1654 unsigned int num_entries;
1655 /* xhci->event_ring keeps track of segment dma addresses */
1656 dma_addr_t erst_dma_addr;
1657 /* Num entries the ERST can contain */
1658 unsigned int erst_size;
1659 };
1660
1661 struct xhci_scratchpad {
1662 u64 *sp_array;
1663 dma_addr_t sp_dma;
1664 void **sp_buffers;
1665 };
1666
1667 struct urb_priv {
1668 int num_tds;
1669 int num_tds_done;
1670 struct xhci_td td[];
1671 };
1672
1673 /*
1674 * Each segment table entry is 4*32bits long. 1K seems like an ok size:
1675 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1676 * meaning 64 ring segments.
1677 * Initial allocated size of the ERST, in number of entries */
1678 #define ERST_NUM_SEGS 1
1679 /* Poll every 60 seconds */
1680 #define POLL_TIMEOUT 60
1681 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1682 #define XHCI_STOP_EP_CMD_TIMEOUT 5
1683 /* XXX: Make these module parameters */
1684
1685 struct s3_save {
1686 u32 command;
1687 u32 dev_nt;
1688 u64 dcbaa_ptr;
1689 u32 config_reg;
1690 };
1691
1692 /* Use for lpm */
1693 struct dev_info {
1694 u32 dev_id;
1695 struct list_head list;
1696 };
1697
1698 struct xhci_bus_state {
1699 unsigned long bus_suspended;
1700 unsigned long next_statechange;
1701
1702 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1703 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1704 u32 port_c_suspend;
1705 u32 suspended_ports;
1706 u32 port_remote_wakeup;
1707 /* which ports have started to resume */
1708 unsigned long resuming_ports;
1709 };
1710
1711 struct xhci_interrupter {
1712 struct xhci_ring *event_ring;
1713 struct xhci_erst erst;
1714 struct xhci_intr_reg __iomem *ir_set;
1715 unsigned int intr_num;
1716 /* For interrupter registers save and restore over suspend/resume */
1717 u32 s3_irq_pending;
1718 u32 s3_irq_control;
1719 u32 s3_erst_size;
1720 u64 s3_erst_base;
1721 u64 s3_erst_dequeue;
1722 };
1723 /*
1724 * It can take up to 20 ms to transition from RExit to U0 on the
1725 * Intel Lynx Point LP xHCI host.
1726 */
1727 #define XHCI_MAX_REXIT_TIMEOUT_MS 20
1728 struct xhci_port_cap {
1729 u32 *psi; /* array of protocol speed ID entries */
1730 u8 psi_count;
1731 u8 psi_uid_count;
1732 u8 maj_rev;
1733 u8 min_rev;
1734 };
1735
1736 struct xhci_port {
1737 __le32 __iomem *addr;
1738 int hw_portnum;
1739 int hcd_portnum;
1740 struct xhci_hub *rhub;
1741 struct xhci_port_cap *port_cap;
1742 unsigned int lpm_incapable:1;
1743 unsigned long resume_timestamp;
1744 bool rexit_active;
1745 struct completion rexit_done;
1746 struct completion u3exit_done;
1747 };
1748
1749 struct xhci_hub {
1750 struct xhci_port **ports;
1751 unsigned int num_ports;
1752 struct usb_hcd *hcd;
1753 /* keep track of bus suspend info */
1754 struct xhci_bus_state bus_state;
1755 /* supported prococol extended capabiliy values */
1756 u8 maj_rev;
1757 u8 min_rev;
1758 };
1759
1760 /* There is one xhci_hcd structure per controller */
1761 struct xhci_hcd {
1762 struct usb_hcd *main_hcd;
1763 struct usb_hcd *shared_hcd;
1764 /* glue to PCI and HCD framework */
1765 struct xhci_cap_regs __iomem *cap_regs;
1766 struct xhci_op_regs __iomem *op_regs;
1767 struct xhci_run_regs __iomem *run_regs;
1768 struct xhci_doorbell_array __iomem *dba;
1769
1770 /* Cached register copies of read-only HC data */
1771 __u32 hcs_params1;
1772 __u32 hcs_params2;
1773 __u32 hcs_params3;
1774 __u32 hcc_params;
1775 __u32 hcc_params2;
1776
1777 spinlock_t lock;
1778
1779 /* packed release number */
1780 u8 sbrn;
1781 u16 hci_version;
1782 u8 max_slots;
1783 u16 max_interrupters;
1784 u8 max_ports;
1785 u8 isoc_threshold;
1786 /* imod_interval in ns (I * 250ns) */
1787 u32 imod_interval;
1788 u32 isoc_bei_interval;
1789 int event_ring_max;
1790 /* 4KB min, 128MB max */
1791 int page_size;
1792 /* Valid values are 12 to 20, inclusive */
1793 int page_shift;
1794 /* msi-x vectors */
1795 int msix_count;
1796 /* optional clocks */
1797 struct clk *clk;
1798 struct clk *reg_clk;
1799 /* optional reset controller */
1800 struct reset_control *reset;
1801 /* data structures */
1802 struct xhci_device_context_array *dcbaa;
1803 struct xhci_interrupter *interrupter;
1804 struct xhci_ring *cmd_ring;
1805 unsigned int cmd_ring_state;
1806 #define CMD_RING_STATE_RUNNING (1 << 0)
1807 #define CMD_RING_STATE_ABORTED (1 << 1)
1808 #define CMD_RING_STATE_STOPPED (1 << 2)
1809 struct list_head cmd_list;
1810 unsigned int cmd_ring_reserved_trbs;
1811 struct delayed_work cmd_timer;
1812 struct completion cmd_ring_stop_completion;
1813 struct xhci_command *current_cmd;
1814
1815 /* Scratchpad */
1816 struct xhci_scratchpad *scratchpad;
1817
1818 /* slot enabling and address device helpers */
1819 /* these are not thread safe so use mutex */
1820 struct mutex mutex;
1821 /* Internal mirror of the HW's dcbaa */
1822 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1823 /* For keeping track of bandwidth domains per roothub. */
1824 struct xhci_root_port_bw_info *rh_bw;
1825
1826 /* DMA pools */
1827 struct dma_pool *device_pool;
1828 struct dma_pool *segment_pool;
1829 struct dma_pool *small_streams_pool;
1830 struct dma_pool *medium_streams_pool;
1831
1832 /* Host controller watchdog timer structures */
1833 unsigned int xhc_state;
1834 unsigned long run_graceperiod;
1835 struct s3_save s3;
1836 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1837 *
1838 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1839 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1840 * that sees this status (other than the timer that set it) should stop touching
1841 * hardware immediately. Interrupt handlers should return immediately when
1842 * they see this status (any time they drop and re-acquire xhci->lock).
1843 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1844 * putting the TD on the canceled list, etc.
1845 *
1846 * There are no reports of xHCI host controllers that display this issue.
1847 */
1848 #define XHCI_STATE_DYING (1 << 0)
1849 #define XHCI_STATE_HALTED (1 << 1)
1850 #define XHCI_STATE_REMOVING (1 << 2)
1851 unsigned long long quirks;
1852 #define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
1853 #define XHCI_RESET_EP_QUIRK BIT_ULL(1) /* Deprecated */
1854 #define XHCI_NEC_HOST BIT_ULL(2)
1855 #define XHCI_AMD_PLL_FIX BIT_ULL(3)
1856 #define XHCI_SPURIOUS_SUCCESS BIT_ULL(4)
1857 /*
1858 * Certain Intel host controllers have a limit to the number of endpoint
1859 * contexts they can handle. Ideally, they would signal that they can't handle
1860 * anymore endpoint contexts by returning a Resource Error for the Configure
1861 * Endpoint command, but they don't. Instead they expect software to keep track
1862 * of the number of active endpoints for them, across configure endpoint
1863 * commands, reset device commands, disable slot commands, and address device
1864 * commands.
1865 */
1866 #define XHCI_EP_LIMIT_QUIRK BIT_ULL(5)
1867 #define XHCI_BROKEN_MSI BIT_ULL(6)
1868 #define XHCI_RESET_ON_RESUME BIT_ULL(7)
1869 #define XHCI_SW_BW_CHECKING BIT_ULL(8)
1870 #define XHCI_AMD_0x96_HOST BIT_ULL(9)
1871 #define XHCI_TRUST_TX_LENGTH BIT_ULL(10)
1872 #define XHCI_LPM_SUPPORT BIT_ULL(11)
1873 #define XHCI_INTEL_HOST BIT_ULL(12)
1874 #define XHCI_SPURIOUS_REBOOT BIT_ULL(13)
1875 #define XHCI_COMP_MODE_QUIRK BIT_ULL(14)
1876 #define XHCI_AVOID_BEI BIT_ULL(15)
1877 #define XHCI_PLAT BIT_ULL(16) /* Deprecated */
1878 #define XHCI_SLOW_SUSPEND BIT_ULL(17)
1879 #define XHCI_SPURIOUS_WAKEUP BIT_ULL(18)
1880 /* For controllers with a broken beyond repair streams implementation */
1881 #define XHCI_BROKEN_STREAMS BIT_ULL(19)
1882 #define XHCI_PME_STUCK_QUIRK BIT_ULL(20)
1883 #define XHCI_MTK_HOST BIT_ULL(21)
1884 #define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
1885 #define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
1886 #define XHCI_MISSING_CAS BIT_ULL(24)
1887 /* For controller with a broken Port Disable implementation */
1888 #define XHCI_BROKEN_PORT_PED BIT_ULL(25)
1889 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
1890 #define XHCI_U2_DISABLE_WAKE BIT_ULL(27)
1891 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
1892 #define XHCI_HW_LPM_DISABLE BIT_ULL(29)
1893 #define XHCI_SUSPEND_DELAY BIT_ULL(30)
1894 #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
1895 #define XHCI_ZERO_64B_REGS BIT_ULL(32)
1896 #define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33)
1897 #define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
1898 #define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
1899 #define XHCI_RENESAS_FW_QUIRK BIT_ULL(36)
1900 #define XHCI_SKIP_PHY_INIT BIT_ULL(37)
1901 #define XHCI_DISABLE_SPARSE BIT_ULL(38)
1902 #define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39)
1903 #define XHCI_NO_SOFT_RETRY BIT_ULL(40)
1904 #define XHCI_BROKEN_D3COLD_S2I BIT_ULL(41)
1905 #define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42)
1906 #define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43)
1907 #define XHCI_RESET_TO_DEFAULT BIT_ULL(44)
1908 #define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45)
1909 #define XHCI_ZHAOXIN_HOST BIT_ULL(46)
1910
1911 unsigned int num_active_eps;
1912 unsigned int limit_active_eps;
1913 struct xhci_port *hw_ports;
1914 struct xhci_hub usb2_rhub;
1915 struct xhci_hub usb3_rhub;
1916 /* support xHCI 1.0 spec USB2 hardware LPM */
1917 unsigned hw_lpm_support:1;
1918 /* Broken Suspend flag for SNPS Suspend resume issue */
1919 unsigned broken_suspend:1;
1920 /* Indicates that omitting hcd is supported if root hub has no ports */
1921 unsigned allow_single_roothub:1;
1922 /* cached usb2 extened protocol capabilites */
1923 u32 *ext_caps;
1924 unsigned int num_ext_caps;
1925 /* cached extended protocol port capabilities */
1926 struct xhci_port_cap *port_caps;
1927 unsigned int num_port_caps;
1928 /* Compliance Mode Recovery Data */
1929 struct timer_list comp_mode_recovery_timer;
1930 u32 port_status_u0;
1931 u16 test_mode;
1932 /* Compliance Mode Timer Triggered every 2 seconds */
1933 #define COMP_MODE_RCVRY_MSECS 2000
1934
1935 struct dentry *debugfs_root;
1936 struct dentry *debugfs_slots;
1937 struct list_head regset_list;
1938
1939 void *dbc;
1940 /* platform-specific data -- must come last */
1941 unsigned long priv[] __aligned(sizeof(s64));
1942 };
1943
1944 /* Platform specific overrides to generic XHCI hc_driver ops */
1945 struct xhci_driver_overrides {
1946 size_t extra_priv_size;
1947 int (*reset)(struct usb_hcd *hcd);
1948 int (*start)(struct usb_hcd *hcd);
1949 int (*add_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1950 struct usb_host_endpoint *ep);
1951 int (*drop_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1952 struct usb_host_endpoint *ep);
1953 int (*check_bandwidth)(struct usb_hcd *, struct usb_device *);
1954 void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);
1955 int (*update_hub_device)(struct usb_hcd *hcd, struct usb_device *hdev,
1956 struct usb_tt *tt, gfp_t mem_flags);
1957 int (*hub_control)(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1958 u16 wIndex, char *buf, u16 wLength);
1959 };
1960
1961 #define XHCI_CFC_DELAY 10
1962
1963 /* convert between an HCD pointer and the corresponding EHCI_HCD */
hcd_to_xhci(struct usb_hcd * hcd)1964 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1965 {
1966 struct usb_hcd *primary_hcd;
1967
1968 if (usb_hcd_is_primary_hcd(hcd))
1969 primary_hcd = hcd;
1970 else
1971 primary_hcd = hcd->primary_hcd;
1972
1973 return (struct xhci_hcd *) (primary_hcd->hcd_priv);
1974 }
1975
xhci_to_hcd(struct xhci_hcd * xhci)1976 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1977 {
1978 return xhci->main_hcd;
1979 }
1980
xhci_get_usb3_hcd(struct xhci_hcd * xhci)1981 static inline struct usb_hcd *xhci_get_usb3_hcd(struct xhci_hcd *xhci)
1982 {
1983 if (xhci->shared_hcd)
1984 return xhci->shared_hcd;
1985
1986 if (!xhci->usb2_rhub.num_ports)
1987 return xhci->main_hcd;
1988
1989 return NULL;
1990 }
1991
xhci_hcd_is_usb3(struct usb_hcd * hcd)1992 static inline bool xhci_hcd_is_usb3(struct usb_hcd *hcd)
1993 {
1994 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1995
1996 return hcd == xhci_get_usb3_hcd(xhci);
1997 }
1998
xhci_has_one_roothub(struct xhci_hcd * xhci)1999 static inline bool xhci_has_one_roothub(struct xhci_hcd *xhci)
2000 {
2001 return xhci->allow_single_roothub &&
2002 (!xhci->usb2_rhub.num_ports || !xhci->usb3_rhub.num_ports);
2003 }
2004
2005 #define xhci_dbg(xhci, fmt, args...) \
2006 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
2007 #define xhci_err(xhci, fmt, args...) \
2008 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
2009 #define xhci_warn(xhci, fmt, args...) \
2010 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
2011 #define xhci_warn_ratelimited(xhci, fmt, args...) \
2012 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
2013 #define xhci_info(xhci, fmt, args...) \
2014 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
2015
2016 /*
2017 * Registers should always be accessed with double word or quad word accesses.
2018 *
2019 * Some xHCI implementations may support 64-bit address pointers. Registers
2020 * with 64-bit address pointers should be written to with dword accesses by
2021 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
2022 * xHCI implementations that do not support 64-bit address pointers will ignore
2023 * the high dword, and write order is irrelevant.
2024 */
xhci_read_64(const struct xhci_hcd * xhci,__le64 __iomem * regs)2025 static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
2026 __le64 __iomem *regs)
2027 {
2028 return lo_hi_readq(regs);
2029 }
xhci_write_64(struct xhci_hcd * xhci,const u64 val,__le64 __iomem * regs)2030 static inline void xhci_write_64(struct xhci_hcd *xhci,
2031 const u64 val, __le64 __iomem *regs)
2032 {
2033 lo_hi_writeq(val, regs);
2034 }
2035
xhci_link_trb_quirk(struct xhci_hcd * xhci)2036 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
2037 {
2038 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
2039 }
2040
2041 /* xHCI debugging */
2042 char *xhci_get_slot_state(struct xhci_hcd *xhci,
2043 struct xhci_container_ctx *ctx);
2044 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
2045 const char *fmt, ...);
2046
2047 /* xHCI memory management */
2048 void xhci_mem_cleanup(struct xhci_hcd *xhci);
2049 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
2050 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
2051 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
2052 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
2053 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
2054 struct usb_device *udev);
2055 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
2056 unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
2057 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
2058 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2059 struct xhci_virt_device *virt_dev,
2060 int old_active_eps);
2061 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
2062 void xhci_update_bw_info(struct xhci_hcd *xhci,
2063 struct xhci_container_ctx *in_ctx,
2064 struct xhci_input_control_ctx *ctrl_ctx,
2065 struct xhci_virt_device *virt_dev);
2066 void xhci_endpoint_copy(struct xhci_hcd *xhci,
2067 struct xhci_container_ctx *in_ctx,
2068 struct xhci_container_ctx *out_ctx,
2069 unsigned int ep_index);
2070 void xhci_slot_copy(struct xhci_hcd *xhci,
2071 struct xhci_container_ctx *in_ctx,
2072 struct xhci_container_ctx *out_ctx);
2073 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
2074 struct usb_device *udev, struct usb_host_endpoint *ep,
2075 gfp_t mem_flags);
2076 struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
2077 unsigned int num_segs, unsigned int cycle_state,
2078 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags);
2079 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
2080 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
2081 unsigned int num_trbs, gfp_t flags);
2082 int xhci_alloc_erst(struct xhci_hcd *xhci,
2083 struct xhci_ring *evt_ring,
2084 struct xhci_erst *erst,
2085 gfp_t flags);
2086 void xhci_initialize_ring_info(struct xhci_ring *ring,
2087 unsigned int cycle_state);
2088 void xhci_free_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
2089 void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
2090 struct xhci_virt_device *virt_dev,
2091 unsigned int ep_index);
2092 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
2093 unsigned int num_stream_ctxs,
2094 unsigned int num_streams,
2095 unsigned int max_packet, gfp_t flags);
2096 void xhci_free_stream_info(struct xhci_hcd *xhci,
2097 struct xhci_stream_info *stream_info);
2098 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
2099 struct xhci_ep_ctx *ep_ctx,
2100 struct xhci_stream_info *stream_info);
2101 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
2102 struct xhci_virt_ep *ep);
2103 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
2104 struct xhci_virt_device *virt_dev, bool drop_control_ep);
2105 struct xhci_ring *xhci_dma_to_transfer_ring(
2106 struct xhci_virt_ep *ep,
2107 u64 address);
2108 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
2109 bool allocate_completion, gfp_t mem_flags);
2110 struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
2111 bool allocate_completion, gfp_t mem_flags);
2112 void xhci_urb_free_priv(struct urb_priv *urb_priv);
2113 void xhci_free_command(struct xhci_hcd *xhci,
2114 struct xhci_command *command);
2115 struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
2116 int type, gfp_t flags);
2117 void xhci_free_container_ctx(struct xhci_hcd *xhci,
2118 struct xhci_container_ctx *ctx);
2119
2120 /* xHCI host controller glue */
2121 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
2122 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us);
2123 void xhci_quiesce(struct xhci_hcd *xhci);
2124 int xhci_halt(struct xhci_hcd *xhci);
2125 int xhci_start(struct xhci_hcd *xhci);
2126 int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us);
2127 int xhci_run(struct usb_hcd *hcd);
2128 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
2129 void xhci_shutdown(struct usb_hcd *hcd);
2130 void xhci_stop(struct usb_hcd *hcd);
2131 void xhci_init_driver(struct hc_driver *drv,
2132 const struct xhci_driver_overrides *over);
2133 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
2134 struct usb_host_endpoint *ep);
2135 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
2136 struct usb_host_endpoint *ep);
2137 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
2138 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
2139 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
2140 struct usb_tt *tt, gfp_t mem_flags);
2141 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id);
2142 int xhci_ext_cap_init(struct xhci_hcd *xhci);
2143
2144 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
2145 int xhci_resume(struct xhci_hcd *xhci, pm_message_t msg);
2146
2147 irqreturn_t xhci_irq(struct usb_hcd *hcd);
2148 irqreturn_t xhci_msi_irq(int irq, void *hcd);
2149 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
2150 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
2151 struct xhci_virt_device *virt_dev,
2152 struct usb_device *hdev,
2153 struct usb_tt *tt, gfp_t mem_flags);
2154
2155 /* xHCI ring, segment, TRB, and TD functions */
2156 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
2157 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
2158 struct xhci_segment *start_seg, union xhci_trb *start_trb,
2159 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug);
2160 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
2161 void xhci_ring_cmd_db(struct xhci_hcd *xhci);
2162 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
2163 u32 trb_type, u32 slot_id);
2164 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2165 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
2166 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
2167 u32 field1, u32 field2, u32 field3, u32 field4);
2168 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
2169 int slot_id, unsigned int ep_index, int suspend);
2170 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2171 int slot_id, unsigned int ep_index);
2172 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2173 int slot_id, unsigned int ep_index);
2174 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2175 int slot_id, unsigned int ep_index);
2176 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
2177 struct urb *urb, int slot_id, unsigned int ep_index);
2178 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
2179 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
2180 bool command_must_succeed);
2181 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
2182 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
2183 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
2184 int slot_id, unsigned int ep_index,
2185 enum xhci_ep_reset_type reset_type);
2186 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2187 u32 slot_id);
2188 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int slot_id,
2189 unsigned int ep_index, unsigned int stream_id,
2190 struct xhci_td *td);
2191 void xhci_stop_endpoint_command_watchdog(struct timer_list *t);
2192 void xhci_handle_command_timeout(struct work_struct *work);
2193
2194 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
2195 unsigned int ep_index, unsigned int stream_id);
2196 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
2197 unsigned int slot_id,
2198 unsigned int ep_index);
2199 void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
2200 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring);
2201 unsigned int count_trbs(u64 addr, u64 len);
2202
2203 /* xHCI roothub code */
2204 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
2205 u32 link_state);
2206 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
2207 u32 port_bit);
2208 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
2209 char *buf, u16 wLength);
2210 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
2211 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
2212 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd);
2213
2214 void xhci_hc_died(struct xhci_hcd *xhci);
2215
2216 #ifdef CONFIG_PM
2217 int xhci_bus_suspend(struct usb_hcd *hcd);
2218 int xhci_bus_resume(struct usb_hcd *hcd);
2219 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd);
2220 #else
2221 #define xhci_bus_suspend NULL
2222 #define xhci_bus_resume NULL
2223 #define xhci_get_resuming_ports NULL
2224 #endif /* CONFIG_PM */
2225
2226 u32 xhci_port_state_to_neutral(u32 state);
2227 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
2228 u16 port);
2229 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
2230
2231 /* xHCI contexts */
2232 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
2233 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
2234 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
2235
2236 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
2237 unsigned int slot_id, unsigned int ep_index,
2238 unsigned int stream_id);
2239
xhci_urb_to_transfer_ring(struct xhci_hcd * xhci,struct urb * urb)2240 static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
2241 struct urb *urb)
2242 {
2243 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
2244 xhci_get_endpoint_index(&urb->ep->desc),
2245 urb->stream_id);
2246 }
2247
2248 /*
2249 * TODO: As per spec Isochronous IDT transmissions are supported. We bypass
2250 * them anyways as we where unable to find a device that matches the
2251 * constraints.
2252 */
xhci_urb_suitable_for_idt(struct urb * urb)2253 static inline bool xhci_urb_suitable_for_idt(struct urb *urb)
2254 {
2255 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) &&
2256 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE &&
2257 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE &&
2258 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) &&
2259 !urb->num_sgs)
2260 return true;
2261
2262 return false;
2263 }
2264
xhci_slot_state_string(u32 state)2265 static inline char *xhci_slot_state_string(u32 state)
2266 {
2267 switch (state) {
2268 case SLOT_STATE_ENABLED:
2269 return "enabled/disabled";
2270 case SLOT_STATE_DEFAULT:
2271 return "default";
2272 case SLOT_STATE_ADDRESSED:
2273 return "addressed";
2274 case SLOT_STATE_CONFIGURED:
2275 return "configured";
2276 default:
2277 return "reserved";
2278 }
2279 }
2280
xhci_decode_trb(char * str,size_t size,u32 field0,u32 field1,u32 field2,u32 field3)2281 static inline const char *xhci_decode_trb(char *str, size_t size,
2282 u32 field0, u32 field1, u32 field2, u32 field3)
2283 {
2284 int type = TRB_FIELD_TO_TYPE(field3);
2285
2286 switch (type) {
2287 case TRB_LINK:
2288 snprintf(str, size,
2289 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c",
2290 field1, field0, GET_INTR_TARGET(field2),
2291 xhci_trb_type_string(type),
2292 field3 & TRB_IOC ? 'I' : 'i',
2293 field3 & TRB_CHAIN ? 'C' : 'c',
2294 field3 & TRB_TC ? 'T' : 't',
2295 field3 & TRB_CYCLE ? 'C' : 'c');
2296 break;
2297 case TRB_TRANSFER:
2298 case TRB_COMPLETION:
2299 case TRB_PORT_STATUS:
2300 case TRB_BANDWIDTH_EVENT:
2301 case TRB_DOORBELL:
2302 case TRB_HC_EVENT:
2303 case TRB_DEV_NOTE:
2304 case TRB_MFINDEX_WRAP:
2305 snprintf(str, size,
2306 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c",
2307 field1, field0,
2308 xhci_trb_comp_code_string(GET_COMP_CODE(field2)),
2309 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3),
2310 /* Macro decrements 1, maybe it shouldn't?!? */
2311 TRB_TO_EP_INDEX(field3) + 1,
2312 xhci_trb_type_string(type),
2313 field3 & EVENT_DATA ? 'E' : 'e',
2314 field3 & TRB_CYCLE ? 'C' : 'c');
2315
2316 break;
2317 case TRB_SETUP:
2318 snprintf(str, size,
2319 "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c",
2320 field0 & 0xff,
2321 (field0 & 0xff00) >> 8,
2322 (field0 & 0xff000000) >> 24,
2323 (field0 & 0xff0000) >> 16,
2324 (field1 & 0xff00) >> 8,
2325 field1 & 0xff,
2326 (field1 & 0xff000000) >> 16 |
2327 (field1 & 0xff0000) >> 16,
2328 TRB_LEN(field2), GET_TD_SIZE(field2),
2329 GET_INTR_TARGET(field2),
2330 xhci_trb_type_string(type),
2331 field3 & TRB_IDT ? 'I' : 'i',
2332 field3 & TRB_IOC ? 'I' : 'i',
2333 field3 & TRB_CYCLE ? 'C' : 'c');
2334 break;
2335 case TRB_DATA:
2336 snprintf(str, size,
2337 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c",
2338 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2339 GET_INTR_TARGET(field2),
2340 xhci_trb_type_string(type),
2341 field3 & TRB_IDT ? 'I' : 'i',
2342 field3 & TRB_IOC ? 'I' : 'i',
2343 field3 & TRB_CHAIN ? 'C' : 'c',
2344 field3 & TRB_NO_SNOOP ? 'S' : 's',
2345 field3 & TRB_ISP ? 'I' : 'i',
2346 field3 & TRB_ENT ? 'E' : 'e',
2347 field3 & TRB_CYCLE ? 'C' : 'c');
2348 break;
2349 case TRB_STATUS:
2350 snprintf(str, size,
2351 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c",
2352 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2353 GET_INTR_TARGET(field2),
2354 xhci_trb_type_string(type),
2355 field3 & TRB_IOC ? 'I' : 'i',
2356 field3 & TRB_CHAIN ? 'C' : 'c',
2357 field3 & TRB_ENT ? 'E' : 'e',
2358 field3 & TRB_CYCLE ? 'C' : 'c');
2359 break;
2360 case TRB_NORMAL:
2361 case TRB_ISOC:
2362 case TRB_EVENT_DATA:
2363 case TRB_TR_NOOP:
2364 snprintf(str, size,
2365 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c",
2366 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2367 GET_INTR_TARGET(field2),
2368 xhci_trb_type_string(type),
2369 field3 & TRB_BEI ? 'B' : 'b',
2370 field3 & TRB_IDT ? 'I' : 'i',
2371 field3 & TRB_IOC ? 'I' : 'i',
2372 field3 & TRB_CHAIN ? 'C' : 'c',
2373 field3 & TRB_NO_SNOOP ? 'S' : 's',
2374 field3 & TRB_ISP ? 'I' : 'i',
2375 field3 & TRB_ENT ? 'E' : 'e',
2376 field3 & TRB_CYCLE ? 'C' : 'c');
2377 break;
2378
2379 case TRB_CMD_NOOP:
2380 case TRB_ENABLE_SLOT:
2381 snprintf(str, size,
2382 "%s: flags %c",
2383 xhci_trb_type_string(type),
2384 field3 & TRB_CYCLE ? 'C' : 'c');
2385 break;
2386 case TRB_DISABLE_SLOT:
2387 case TRB_NEG_BANDWIDTH:
2388 snprintf(str, size,
2389 "%s: slot %d flags %c",
2390 xhci_trb_type_string(type),
2391 TRB_TO_SLOT_ID(field3),
2392 field3 & TRB_CYCLE ? 'C' : 'c');
2393 break;
2394 case TRB_ADDR_DEV:
2395 snprintf(str, size,
2396 "%s: ctx %08x%08x slot %d flags %c:%c",
2397 xhci_trb_type_string(type),
2398 field1, field0,
2399 TRB_TO_SLOT_ID(field3),
2400 field3 & TRB_BSR ? 'B' : 'b',
2401 field3 & TRB_CYCLE ? 'C' : 'c');
2402 break;
2403 case TRB_CONFIG_EP:
2404 snprintf(str, size,
2405 "%s: ctx %08x%08x slot %d flags %c:%c",
2406 xhci_trb_type_string(type),
2407 field1, field0,
2408 TRB_TO_SLOT_ID(field3),
2409 field3 & TRB_DC ? 'D' : 'd',
2410 field3 & TRB_CYCLE ? 'C' : 'c');
2411 break;
2412 case TRB_EVAL_CONTEXT:
2413 snprintf(str, size,
2414 "%s: ctx %08x%08x slot %d flags %c",
2415 xhci_trb_type_string(type),
2416 field1, field0,
2417 TRB_TO_SLOT_ID(field3),
2418 field3 & TRB_CYCLE ? 'C' : 'c');
2419 break;
2420 case TRB_RESET_EP:
2421 snprintf(str, size,
2422 "%s: ctx %08x%08x slot %d ep %d flags %c:%c",
2423 xhci_trb_type_string(type),
2424 field1, field0,
2425 TRB_TO_SLOT_ID(field3),
2426 /* Macro decrements 1, maybe it shouldn't?!? */
2427 TRB_TO_EP_INDEX(field3) + 1,
2428 field3 & TRB_TSP ? 'T' : 't',
2429 field3 & TRB_CYCLE ? 'C' : 'c');
2430 break;
2431 case TRB_STOP_RING:
2432 snprintf(str, size,
2433 "%s: slot %d sp %d ep %d flags %c",
2434 xhci_trb_type_string(type),
2435 TRB_TO_SLOT_ID(field3),
2436 TRB_TO_SUSPEND_PORT(field3),
2437 /* Macro decrements 1, maybe it shouldn't?!? */
2438 TRB_TO_EP_INDEX(field3) + 1,
2439 field3 & TRB_CYCLE ? 'C' : 'c');
2440 break;
2441 case TRB_SET_DEQ:
2442 snprintf(str, size,
2443 "%s: deq %08x%08x stream %d slot %d ep %d flags %c",
2444 xhci_trb_type_string(type),
2445 field1, field0,
2446 TRB_TO_STREAM_ID(field2),
2447 TRB_TO_SLOT_ID(field3),
2448 /* Macro decrements 1, maybe it shouldn't?!? */
2449 TRB_TO_EP_INDEX(field3) + 1,
2450 field3 & TRB_CYCLE ? 'C' : 'c');
2451 break;
2452 case TRB_RESET_DEV:
2453 snprintf(str, size,
2454 "%s: slot %d flags %c",
2455 xhci_trb_type_string(type),
2456 TRB_TO_SLOT_ID(field3),
2457 field3 & TRB_CYCLE ? 'C' : 'c');
2458 break;
2459 case TRB_FORCE_EVENT:
2460 snprintf(str, size,
2461 "%s: event %08x%08x vf intr %d vf id %d flags %c",
2462 xhci_trb_type_string(type),
2463 field1, field0,
2464 TRB_TO_VF_INTR_TARGET(field2),
2465 TRB_TO_VF_ID(field3),
2466 field3 & TRB_CYCLE ? 'C' : 'c');
2467 break;
2468 case TRB_SET_LT:
2469 snprintf(str, size,
2470 "%s: belt %d flags %c",
2471 xhci_trb_type_string(type),
2472 TRB_TO_BELT(field3),
2473 field3 & TRB_CYCLE ? 'C' : 'c');
2474 break;
2475 case TRB_GET_BW:
2476 snprintf(str, size,
2477 "%s: ctx %08x%08x slot %d speed %d flags %c",
2478 xhci_trb_type_string(type),
2479 field1, field0,
2480 TRB_TO_SLOT_ID(field3),
2481 TRB_TO_DEV_SPEED(field3),
2482 field3 & TRB_CYCLE ? 'C' : 'c');
2483 break;
2484 case TRB_FORCE_HEADER:
2485 snprintf(str, size,
2486 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c",
2487 xhci_trb_type_string(type),
2488 field2, field1, field0 & 0xffffffe0,
2489 TRB_TO_PACKET_TYPE(field0),
2490 TRB_TO_ROOTHUB_PORT(field3),
2491 field3 & TRB_CYCLE ? 'C' : 'c');
2492 break;
2493 default:
2494 snprintf(str, size,
2495 "type '%s' -> raw %08x %08x %08x %08x",
2496 xhci_trb_type_string(type),
2497 field0, field1, field2, field3);
2498 }
2499
2500 return str;
2501 }
2502
xhci_decode_ctrl_ctx(char * str,unsigned long drop,unsigned long add)2503 static inline const char *xhci_decode_ctrl_ctx(char *str,
2504 unsigned long drop, unsigned long add)
2505 {
2506 unsigned int bit;
2507 int ret = 0;
2508
2509 str[0] = '\0';
2510
2511 if (drop) {
2512 ret = sprintf(str, "Drop:");
2513 for_each_set_bit(bit, &drop, 32)
2514 ret += sprintf(str + ret, " %d%s",
2515 bit / 2,
2516 bit % 2 ? "in":"out");
2517 ret += sprintf(str + ret, ", ");
2518 }
2519
2520 if (add) {
2521 ret += sprintf(str + ret, "Add:%s%s",
2522 (add & SLOT_FLAG) ? " slot":"",
2523 (add & EP0_FLAG) ? " ep0":"");
2524 add &= ~(SLOT_FLAG | EP0_FLAG);
2525 for_each_set_bit(bit, &add, 32)
2526 ret += sprintf(str + ret, " %d%s",
2527 bit / 2,
2528 bit % 2 ? "in":"out");
2529 }
2530 return str;
2531 }
2532
xhci_decode_slot_context(char * str,u32 info,u32 info2,u32 tt_info,u32 state)2533 static inline const char *xhci_decode_slot_context(char *str,
2534 u32 info, u32 info2, u32 tt_info, u32 state)
2535 {
2536 u32 speed;
2537 u32 hub;
2538 u32 mtt;
2539 int ret = 0;
2540
2541 speed = info & DEV_SPEED;
2542 hub = info & DEV_HUB;
2543 mtt = info & DEV_MTT;
2544
2545 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d",
2546 info & ROUTE_STRING_MASK,
2547 ({ char *s;
2548 switch (speed) {
2549 case SLOT_SPEED_FS:
2550 s = "full-speed";
2551 break;
2552 case SLOT_SPEED_LS:
2553 s = "low-speed";
2554 break;
2555 case SLOT_SPEED_HS:
2556 s = "high-speed";
2557 break;
2558 case SLOT_SPEED_SS:
2559 s = "super-speed";
2560 break;
2561 case SLOT_SPEED_SSP:
2562 s = "super-speed plus";
2563 break;
2564 default:
2565 s = "UNKNOWN speed";
2566 } s; }),
2567 mtt ? " multi-TT" : "",
2568 hub ? " Hub" : "",
2569 (info & LAST_CTX_MASK) >> 27,
2570 info2 & MAX_EXIT,
2571 DEVINFO_TO_ROOT_HUB_PORT(info2),
2572 DEVINFO_TO_MAX_PORTS(info2));
2573
2574 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s",
2575 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8,
2576 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info),
2577 state & DEV_ADDR_MASK,
2578 xhci_slot_state_string(GET_SLOT_STATE(state)));
2579
2580 return str;
2581 }
2582
2583
xhci_portsc_link_state_string(u32 portsc)2584 static inline const char *xhci_portsc_link_state_string(u32 portsc)
2585 {
2586 switch (portsc & PORT_PLS_MASK) {
2587 case XDEV_U0:
2588 return "U0";
2589 case XDEV_U1:
2590 return "U1";
2591 case XDEV_U2:
2592 return "U2";
2593 case XDEV_U3:
2594 return "U3";
2595 case XDEV_DISABLED:
2596 return "Disabled";
2597 case XDEV_RXDETECT:
2598 return "RxDetect";
2599 case XDEV_INACTIVE:
2600 return "Inactive";
2601 case XDEV_POLLING:
2602 return "Polling";
2603 case XDEV_RECOVERY:
2604 return "Recovery";
2605 case XDEV_HOT_RESET:
2606 return "Hot Reset";
2607 case XDEV_COMP_MODE:
2608 return "Compliance mode";
2609 case XDEV_TEST_MODE:
2610 return "Test mode";
2611 case XDEV_RESUME:
2612 return "Resume";
2613 default:
2614 break;
2615 }
2616 return "Unknown";
2617 }
2618
xhci_decode_portsc(char * str,u32 portsc)2619 static inline const char *xhci_decode_portsc(char *str, u32 portsc)
2620 {
2621 int ret;
2622
2623 ret = sprintf(str, "%s %s %s Link:%s PortSpeed:%d ",
2624 portsc & PORT_POWER ? "Powered" : "Powered-off",
2625 portsc & PORT_CONNECT ? "Connected" : "Not-connected",
2626 portsc & PORT_PE ? "Enabled" : "Disabled",
2627 xhci_portsc_link_state_string(portsc),
2628 DEV_PORT_SPEED(portsc));
2629
2630 if (portsc & PORT_OC)
2631 ret += sprintf(str + ret, "OverCurrent ");
2632 if (portsc & PORT_RESET)
2633 ret += sprintf(str + ret, "In-Reset ");
2634
2635 ret += sprintf(str + ret, "Change: ");
2636 if (portsc & PORT_CSC)
2637 ret += sprintf(str + ret, "CSC ");
2638 if (portsc & PORT_PEC)
2639 ret += sprintf(str + ret, "PEC ");
2640 if (portsc & PORT_WRC)
2641 ret += sprintf(str + ret, "WRC ");
2642 if (portsc & PORT_OCC)
2643 ret += sprintf(str + ret, "OCC ");
2644 if (portsc & PORT_RC)
2645 ret += sprintf(str + ret, "PRC ");
2646 if (portsc & PORT_PLC)
2647 ret += sprintf(str + ret, "PLC ");
2648 if (portsc & PORT_CEC)
2649 ret += sprintf(str + ret, "CEC ");
2650 if (portsc & PORT_CAS)
2651 ret += sprintf(str + ret, "CAS ");
2652
2653 ret += sprintf(str + ret, "Wake: ");
2654 if (portsc & PORT_WKCONN_E)
2655 ret += sprintf(str + ret, "WCE ");
2656 if (portsc & PORT_WKDISC_E)
2657 ret += sprintf(str + ret, "WDE ");
2658 if (portsc & PORT_WKOC_E)
2659 ret += sprintf(str + ret, "WOE ");
2660
2661 return str;
2662 }
2663
xhci_decode_usbsts(char * str,u32 usbsts)2664 static inline const char *xhci_decode_usbsts(char *str, u32 usbsts)
2665 {
2666 int ret = 0;
2667
2668 ret = sprintf(str, " 0x%08x", usbsts);
2669
2670 if (usbsts == ~(u32)0)
2671 return str;
2672
2673 if (usbsts & STS_HALT)
2674 ret += sprintf(str + ret, " HCHalted");
2675 if (usbsts & STS_FATAL)
2676 ret += sprintf(str + ret, " HSE");
2677 if (usbsts & STS_EINT)
2678 ret += sprintf(str + ret, " EINT");
2679 if (usbsts & STS_PORT)
2680 ret += sprintf(str + ret, " PCD");
2681 if (usbsts & STS_SAVE)
2682 ret += sprintf(str + ret, " SSS");
2683 if (usbsts & STS_RESTORE)
2684 ret += sprintf(str + ret, " RSS");
2685 if (usbsts & STS_SRE)
2686 ret += sprintf(str + ret, " SRE");
2687 if (usbsts & STS_CNR)
2688 ret += sprintf(str + ret, " CNR");
2689 if (usbsts & STS_HCE)
2690 ret += sprintf(str + ret, " HCE");
2691
2692 return str;
2693 }
2694
xhci_decode_doorbell(char * str,u32 slot,u32 doorbell)2695 static inline const char *xhci_decode_doorbell(char *str, u32 slot, u32 doorbell)
2696 {
2697 u8 ep;
2698 u16 stream;
2699 int ret;
2700
2701 ep = (doorbell & 0xff);
2702 stream = doorbell >> 16;
2703
2704 if (slot == 0) {
2705 sprintf(str, "Command Ring %d", doorbell);
2706 return str;
2707 }
2708 ret = sprintf(str, "Slot %d ", slot);
2709 if (ep > 0 && ep < 32)
2710 ret = sprintf(str + ret, "ep%d%s",
2711 ep / 2,
2712 ep % 2 ? "in" : "out");
2713 else if (ep == 0 || ep < 248)
2714 ret = sprintf(str + ret, "Reserved %d", ep);
2715 else
2716 ret = sprintf(str + ret, "Vendor Defined %d", ep);
2717 if (stream)
2718 ret = sprintf(str + ret, " Stream %d", stream);
2719
2720 return str;
2721 }
2722
xhci_ep_state_string(u8 state)2723 static inline const char *xhci_ep_state_string(u8 state)
2724 {
2725 switch (state) {
2726 case EP_STATE_DISABLED:
2727 return "disabled";
2728 case EP_STATE_RUNNING:
2729 return "running";
2730 case EP_STATE_HALTED:
2731 return "halted";
2732 case EP_STATE_STOPPED:
2733 return "stopped";
2734 case EP_STATE_ERROR:
2735 return "error";
2736 default:
2737 return "INVALID";
2738 }
2739 }
2740
xhci_ep_type_string(u8 type)2741 static inline const char *xhci_ep_type_string(u8 type)
2742 {
2743 switch (type) {
2744 case ISOC_OUT_EP:
2745 return "Isoc OUT";
2746 case BULK_OUT_EP:
2747 return "Bulk OUT";
2748 case INT_OUT_EP:
2749 return "Int OUT";
2750 case CTRL_EP:
2751 return "Ctrl";
2752 case ISOC_IN_EP:
2753 return "Isoc IN";
2754 case BULK_IN_EP:
2755 return "Bulk IN";
2756 case INT_IN_EP:
2757 return "Int IN";
2758 default:
2759 return "INVALID";
2760 }
2761 }
2762
xhci_decode_ep_context(char * str,u32 info,u32 info2,u64 deq,u32 tx_info)2763 static inline const char *xhci_decode_ep_context(char *str, u32 info,
2764 u32 info2, u64 deq, u32 tx_info)
2765 {
2766 int ret;
2767
2768 u32 esit;
2769 u16 maxp;
2770 u16 avg;
2771
2772 u8 max_pstr;
2773 u8 ep_state;
2774 u8 interval;
2775 u8 ep_type;
2776 u8 burst;
2777 u8 cerr;
2778 u8 mult;
2779
2780 bool lsa;
2781 bool hid;
2782
2783 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 |
2784 CTX_TO_MAX_ESIT_PAYLOAD(tx_info);
2785
2786 ep_state = info & EP_STATE_MASK;
2787 max_pstr = CTX_TO_EP_MAXPSTREAMS(info);
2788 interval = CTX_TO_EP_INTERVAL(info);
2789 mult = CTX_TO_EP_MULT(info) + 1;
2790 lsa = !!(info & EP_HAS_LSA);
2791
2792 cerr = (info2 & (3 << 1)) >> 1;
2793 ep_type = CTX_TO_EP_TYPE(info2);
2794 hid = !!(info2 & (1 << 7));
2795 burst = CTX_TO_MAX_BURST(info2);
2796 maxp = MAX_PACKET_DECODED(info2);
2797
2798 avg = EP_AVG_TRB_LENGTH(tx_info);
2799
2800 ret = sprintf(str, "State %s mult %d max P. Streams %d %s",
2801 xhci_ep_state_string(ep_state), mult,
2802 max_pstr, lsa ? "LSA " : "");
2803
2804 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ",
2805 (1 << interval) * 125, esit, cerr);
2806
2807 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ",
2808 xhci_ep_type_string(ep_type), hid ? "HID" : "",
2809 burst, maxp, deq);
2810
2811 ret += sprintf(str + ret, "avg trb len %d", avg);
2812
2813 return str;
2814 }
2815
2816 #endif /* __LINUX_XHCI_HCD_H */
2817