1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * xHCI host controller driver
4  *
5  * Copyright (C) 2008 Intel Corp.
6  *
7  * Author: Sarah Sharp
8  * Some code borrowed from the Linux EHCI driver.
9  */
10 
11 /* HC should halt within 16 ms, but use 32 ms as some hosts take longer */
12 #define XHCI_MAX_HALT_USEC	(32 * 1000)
13 /* HC not running - set to 1 when run/stop bit is cleared. */
14 #define XHCI_STS_HALT		(1<<0)
15 
16 /* HCCPARAMS offset from PCI base address */
17 #define XHCI_HCC_PARAMS_OFFSET	0x10
18 /* HCCPARAMS contains the first extended capability pointer */
19 #define XHCI_HCC_EXT_CAPS(p)	(((p)>>16)&0xffff)
20 
21 /* Command and Status registers offset from the Operational Registers address */
22 #define XHCI_CMD_OFFSET		0x00
23 #define XHCI_STS_OFFSET		0x04
24 
25 #define XHCI_MAX_EXT_CAPS		50
26 
27 /* Capability Register */
28 /* bits 7:0 - how long is the Capabilities register */
29 #define XHCI_HC_LENGTH(p)	(((p)>>00)&0x00ff)
30 
31 /* Extended capability register fields */
32 #define XHCI_EXT_CAPS_ID(p)	(((p)>>0)&0xff)
33 #define XHCI_EXT_CAPS_NEXT(p)	(((p)>>8)&0xff)
34 #define	XHCI_EXT_CAPS_VAL(p)	((p)>>16)
35 /* Extended capability IDs - ID 0 reserved */
36 #define XHCI_EXT_CAPS_LEGACY	1
37 #define XHCI_EXT_CAPS_PROTOCOL	2
38 #define XHCI_EXT_CAPS_PM	3
39 #define XHCI_EXT_CAPS_VIRT	4
40 #define XHCI_EXT_CAPS_ROUTE	5
41 /* IDs 6-9 reserved */
42 #define XHCI_EXT_CAPS_DEBUG	10
43 /* Vendor caps */
44 #define XHCI_EXT_CAPS_VENDOR_INTEL	192
45 /* USB Legacy Support Capability - section 7.1.1 */
46 #define XHCI_HC_BIOS_OWNED	(1 << 16)
47 #define XHCI_HC_OS_OWNED	(1 << 24)
48 
49 /* USB Legacy Support Capability - section 7.1.1 */
50 /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
51 #define XHCI_LEGACY_SUPPORT_OFFSET	(0x00)
52 
53 /* USB Legacy Support Control and Status Register  - section 7.1.2 */
54 /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
55 #define XHCI_LEGACY_CONTROL_OFFSET	(0x04)
56 /* bits 1:3, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */
57 #define	XHCI_LEGACY_DISABLE_SMI		((0x7 << 1) + (0xff << 5) + (0x7 << 17))
58 #define XHCI_LEGACY_SMI_EVENTS		(0x7 << 29)
59 
60 /* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */
61 #define XHCI_L1C               (1 << 16)
62 
63 /* USB 2.0 xHCI 1.0 hardware LMP capability - section 7.2.2.1.3.2 */
64 #define XHCI_HLC               (1 << 19)
65 #define XHCI_BLC               (1 << 20)
66 
67 /* command register values to disable interrupts and halt the HC */
68 /* start/stop HC execution - do not write unless HC is halted*/
69 #define XHCI_CMD_RUN		(1 << 0)
70 /* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */
71 #define XHCI_CMD_EIE		(1 << 2)
72 /* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */
73 #define XHCI_CMD_HSEIE		(1 << 3)
74 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
75 #define XHCI_CMD_EWE		(1 << 10)
76 
77 #define XHCI_IRQS		(XHCI_CMD_EIE | XHCI_CMD_HSEIE | XHCI_CMD_EWE)
78 
79 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
80 #define XHCI_STS_CNR		(1 << 11)
81 
82 #include <linux/io.h>
83 
84 /**
85  * Find the offset of the extended capabilities with capability ID id.
86  *
87  * @base	PCI MMIO registers base address.
88  * @start	address at which to start looking, (0 or HCC_PARAMS to start at
89  *		beginning of list)
90  * @id		Extended capability ID to search for, or 0 for the next
91  *		capability
92  *
93  * Returns the offset of the next matching extended capability structure.
94  * Some capabilities can occur several times, e.g., the XHCI_EXT_CAPS_PROTOCOL,
95  * and this provides a way to find them all.
96  */
97 
xhci_find_next_ext_cap(void __iomem * base,u32 start,int id)98 static inline int xhci_find_next_ext_cap(void __iomem *base, u32 start, int id)
99 {
100 	u32 val;
101 	u32 next;
102 	u32 offset;
103 
104 	offset = start;
105 	if (!start || start == XHCI_HCC_PARAMS_OFFSET) {
106 		val = readl(base + XHCI_HCC_PARAMS_OFFSET);
107 		if (val == ~0)
108 			return 0;
109 		offset = XHCI_HCC_EXT_CAPS(val) << 2;
110 		if (!offset)
111 			return 0;
112 	}
113 	do {
114 		val = readl(base + offset);
115 		if (val == ~0)
116 			return 0;
117 		if (offset != start && (id == 0 || XHCI_EXT_CAPS_ID(val) == id))
118 			return offset;
119 
120 		next = XHCI_EXT_CAPS_NEXT(val);
121 		offset += next << 2;
122 	} while (next);
123 
124 	return 0;
125 }
126