1 #include "vgatypes.h"
2
3 #include <linux/version.h>
4 #include <linux/types.h>
5 #include <linux/delay.h> /* udelay */
6 #include "XGIfb.h"
7
8 #include "vb_def.h"
9 #include "vb_struct.h"
10 #include "vb_util.h"
11 #include "vb_setmode.h"
12 #include "vb_init.h"
13 #include "vb_ext.h"
14
15
16 #include <asm/io.h>
17
18 static unsigned char XGINew_ChannelAB, XGINew_DataBusWidth;
19
20 static unsigned short XGINew_DDRDRAM_TYPE340[4][5] = {
21 { 2, 13, 9, 64, 0x45},
22 { 2, 12, 9, 32, 0x35},
23 { 2, 12, 8, 16, 0x31},
24 { 2, 11, 8, 8, 0x21} };
25
26 static unsigned short XGINew_DDRDRAM_TYPE20[12][5] = {
27 { 2, 14, 11, 128, 0x5D},
28 { 2, 14, 10, 64, 0x59},
29 { 2, 13, 11, 64, 0x4D},
30 { 2, 14, 9, 32, 0x55},
31 { 2, 13, 10, 32, 0x49},
32 { 2, 12, 11, 32, 0x3D},
33 { 2, 14, 8, 16, 0x51},
34 { 2, 13, 9, 16, 0x45},
35 { 2, 12, 10, 16, 0x39},
36 { 2, 13, 8, 8, 0x41},
37 { 2, 12, 9, 8, 0x35},
38 { 2, 12, 8, 4, 0x31} };
39
40 static int XGINew_RAMType;
41
XGINew_GetXG20DRAMType(struct xgi_hw_device_info * HwDeviceExtension,struct vb_device_info * pVBInfo)42 static unsigned char XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
43 struct vb_device_info *pVBInfo)
44 {
45 unsigned char data, temp;
46
47 if (HwDeviceExtension->jChipType < XG20) {
48 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
49 data = *pVBInfo->pSoftSetting & 0x07;
50 return data;
51 } else {
52 data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
53
54 if (data == 0)
55 data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) & 0x02) >> 1;
56
57 return data;
58 }
59 } else if (HwDeviceExtension->jChipType == XG27) {
60 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
61 data = *pVBInfo->pSoftSetting & 0x07;
62 return data;
63 }
64 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
65
66 if ((temp & 0x88) == 0x80) /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
67 data = 0; /* DDR */
68 else
69 data = 1; /* DDRII */
70 return data;
71 } else if (HwDeviceExtension->jChipType == XG21) {
72 xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02); /* Independent GPIO control */
73 udelay(800);
74 xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
75 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48); /* GPIOF 0:DVI 1:DVO */
76 /* HOTPLUG_SUPPORT */
77 /* for current XG20 & XG21, GPIOH is floating, driver will fix DDR temporarily */
78 if (temp & 0x01) /* DVI read GPIOH */
79 data = 1; /* DDRII */
80 else
81 data = 0; /* DDR */
82 /* ~HOTPLUG_SUPPORT */
83 xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02);
84 return data;
85 } else {
86 data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01;
87
88 if (data == 1)
89 data++;
90
91 return data;
92 }
93 }
94
XGINew_DDR1x_MRS_340(unsigned long P3c4,struct vb_device_info * pVBInfo)95 static void XGINew_DDR1x_MRS_340(unsigned long P3c4, struct vb_device_info *pVBInfo)
96 {
97 xgifb_reg_set(P3c4, 0x18, 0x01);
98 xgifb_reg_set(P3c4, 0x19, 0x20);
99 xgifb_reg_set(P3c4, 0x16, 0x00);
100 xgifb_reg_set(P3c4, 0x16, 0x80);
101
102 if (*pVBInfo->pXGINew_DRAMTypeDefinition != 0x0C) { /* Samsung F Die */
103 mdelay(3);
104 xgifb_reg_set(P3c4, 0x18, 0x00);
105 xgifb_reg_set(P3c4, 0x19, 0x20);
106 xgifb_reg_set(P3c4, 0x16, 0x00);
107 xgifb_reg_set(P3c4, 0x16, 0x80);
108 }
109
110 udelay(60);
111 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
112 xgifb_reg_set(P3c4, 0x19, 0x01);
113 xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[0]);
114 xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[1]);
115 mdelay(1);
116 xgifb_reg_set(P3c4, 0x1B, 0x03);
117 udelay(500);
118 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
119 xgifb_reg_set(P3c4, 0x19, 0x00);
120 xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[2]);
121 xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[3]);
122 xgifb_reg_set(P3c4, 0x1B, 0x00);
123 }
124
XGINew_SetMemoryClock(struct xgi_hw_device_info * HwDeviceExtension,struct vb_device_info * pVBInfo)125 static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension,
126 struct vb_device_info *pVBInfo)
127 {
128
129 xgifb_reg_set(pVBInfo->P3c4, 0x28, pVBInfo->MCLKData[XGINew_RAMType].SR28);
130 xgifb_reg_set(pVBInfo->P3c4, 0x29, pVBInfo->MCLKData[XGINew_RAMType].SR29);
131 xgifb_reg_set(pVBInfo->P3c4, 0x2A, pVBInfo->MCLKData[XGINew_RAMType].SR2A);
132
133 xgifb_reg_set(pVBInfo->P3c4, 0x2E, pVBInfo->ECLKData[XGINew_RAMType].SR2E);
134 xgifb_reg_set(pVBInfo->P3c4, 0x2F, pVBInfo->ECLKData[XGINew_RAMType].SR2F);
135 xgifb_reg_set(pVBInfo->P3c4, 0x30, pVBInfo->ECLKData[XGINew_RAMType].SR30);
136
137 /* [Vicent] 2004/07/07, When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
138 /* [Hsuan] 2004/08/20, Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz, Set SR32 D[1:0] = 10b */
139 if (HwDeviceExtension->jChipType == XG42) {
140 if ((pVBInfo->MCLKData[XGINew_RAMType].SR28 == 0x1C)
141 && (pVBInfo->MCLKData[XGINew_RAMType].SR29 == 0x01)
142 && (((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x1C)
143 && (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01))
144 || ((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x22)
145 && (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01))))
146 xgifb_reg_set(pVBInfo->P3c4, 0x32, ((unsigned char) xgifb_reg_get(pVBInfo->P3c4, 0x32) & 0xFC) | 0x02);
147 }
148 }
149
XGINew_DDRII_Bootup_XG27(struct xgi_hw_device_info * HwDeviceExtension,unsigned long P3c4,struct vb_device_info * pVBInfo)150 static void XGINew_DDRII_Bootup_XG27(
151 struct xgi_hw_device_info *HwDeviceExtension,
152 unsigned long P3c4, struct vb_device_info *pVBInfo)
153 {
154 unsigned long P3d4 = P3c4 + 0x10;
155 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
156 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
157
158 /* Set Double Frequency */
159 /* xgifb_reg_set(P3d4, 0x97, 0x11); *//* CR97 */
160 xgifb_reg_set(P3d4, 0x97, *pVBInfo->pXGINew_CR97); /* CR97 */
161
162 udelay(200);
163
164 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
165 xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */
166 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
167 udelay(15);
168 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
169 udelay(15);
170
171 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
172 xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */
173 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
174 udelay(15);
175 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
176 udelay(15);
177
178 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
179 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
180 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
181 udelay(30);
182 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
183 udelay(15);
184
185 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
186 xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */
187 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
188 udelay(30);
189 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
190 xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */
191 /* udelay(15); */
192
193 xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */
194 udelay(60);
195 xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */
196
197 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
198 xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */
199 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
200
201 udelay(30);
202 xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */
203 udelay(15);
204
205 xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
206 xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */
207 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
208 udelay(30);
209 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
210 udelay(15);
211
212 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
213 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
214 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
215 udelay(30);
216 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
217 udelay(15);
218
219 xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B refresh control 000:close; 010:open */
220 udelay(200);
221
222 }
223
XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info * HwDeviceExtension,unsigned long P3c4,struct vb_device_info * pVBInfo)224 static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
225 unsigned long P3c4, struct vb_device_info *pVBInfo)
226 {
227 unsigned long P3d4 = P3c4 + 0x10;
228
229 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
230 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
231
232 xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
233
234 udelay(200);
235 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */
236 xgifb_reg_set(P3c4, 0x19, 0x80);
237 xgifb_reg_set(P3c4, 0x16, 0x05);
238 xgifb_reg_set(P3c4, 0x16, 0x85);
239
240 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */
241 xgifb_reg_set(P3c4, 0x19, 0xC0);
242 xgifb_reg_set(P3c4, 0x16, 0x05);
243 xgifb_reg_set(P3c4, 0x16, 0x85);
244
245 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */
246 xgifb_reg_set(P3c4, 0x19, 0x40);
247 xgifb_reg_set(P3c4, 0x16, 0x05);
248 xgifb_reg_set(P3c4, 0x16, 0x85);
249
250 /* xgifb_reg_set(P3c4, 0x18, 0x52); */ /* MRS1 */
251 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
252 xgifb_reg_set(P3c4, 0x19, 0x02);
253 xgifb_reg_set(P3c4, 0x16, 0x05);
254 xgifb_reg_set(P3c4, 0x16, 0x85);
255
256 udelay(15);
257 xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */
258 udelay(30);
259 xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */
260 udelay(100);
261
262 /* xgifb_reg_set(P3c4 ,0x18, 0x52); */ /* MRS2 */
263 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
264 xgifb_reg_set(P3c4, 0x19, 0x00);
265 xgifb_reg_set(P3c4, 0x16, 0x05);
266 xgifb_reg_set(P3c4, 0x16, 0x85);
267
268 udelay(200);
269 }
270
XGINew_DDR1x_MRS_XG20(unsigned long P3c4,struct vb_device_info * pVBInfo)271 static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, struct vb_device_info *pVBInfo)
272 {
273
274 xgifb_reg_set(P3c4, 0x18, 0x01);
275 xgifb_reg_set(P3c4, 0x19, 0x40);
276 xgifb_reg_set(P3c4, 0x16, 0x00);
277 xgifb_reg_set(P3c4, 0x16, 0x80);
278 udelay(60);
279
280 xgifb_reg_set(P3c4, 0x18, 0x00);
281 xgifb_reg_set(P3c4, 0x19, 0x40);
282 xgifb_reg_set(P3c4, 0x16, 0x00);
283 xgifb_reg_set(P3c4, 0x16, 0x80);
284 udelay(60);
285 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
286 /* xgifb_reg_set(P3c4, 0x18, 0x31); */
287 xgifb_reg_set(P3c4, 0x19, 0x01);
288 xgifb_reg_set(P3c4, 0x16, 0x03);
289 xgifb_reg_set(P3c4, 0x16, 0x83);
290 mdelay(1);
291 xgifb_reg_set(P3c4, 0x1B, 0x03);
292 udelay(500);
293 /* xgifb_reg_set(P3c4, 0x18, 0x31); */
294 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
295 xgifb_reg_set(P3c4, 0x19, 0x00);
296 xgifb_reg_set(P3c4, 0x16, 0x03);
297 xgifb_reg_set(P3c4, 0x16, 0x83);
298 xgifb_reg_set(P3c4, 0x1B, 0x00);
299 }
300
XGINew_DDR1x_DefaultRegister(struct xgi_hw_device_info * HwDeviceExtension,unsigned long Port,struct vb_device_info * pVBInfo)301 static void XGINew_DDR1x_DefaultRegister(
302 struct xgi_hw_device_info *HwDeviceExtension,
303 unsigned long Port, struct vb_device_info *pVBInfo)
304 {
305 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
306
307 if (HwDeviceExtension->jChipType >= XG20) {
308 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
309 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
310 xgifb_reg_set(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
311 xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */
312
313 xgifb_reg_set(P3d4, 0x98, 0x01);
314 xgifb_reg_set(P3d4, 0x9A, 0x02);
315
316 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
317 } else {
318 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
319
320 switch (HwDeviceExtension->jChipType) {
321 case XG41:
322 case XG42:
323 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
324 xgifb_reg_set(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
325 xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */
326 break;
327 default:
328 xgifb_reg_set(P3d4, 0x82, 0x88);
329 xgifb_reg_set(P3d4, 0x86, 0x00);
330 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
331 xgifb_reg_set(P3d4, 0x86, 0x88);
332 xgifb_reg_get(P3d4, 0x86);
333 xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]);
334 xgifb_reg_set(P3d4, 0x82, 0x77);
335 xgifb_reg_set(P3d4, 0x85, 0x00);
336 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
337 xgifb_reg_set(P3d4, 0x85, 0x88);
338 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
339 xgifb_reg_set(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
340 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
341 break;
342 }
343
344 xgifb_reg_set(P3d4, 0x97, 0x00);
345 xgifb_reg_set(P3d4, 0x98, 0x01);
346 xgifb_reg_set(P3d4, 0x9A, 0x02);
347 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
348 }
349 }
350
XGINew_DDR2_DefaultRegister(struct xgi_hw_device_info * HwDeviceExtension,unsigned long Port,struct vb_device_info * pVBInfo)351 static void XGINew_DDR2_DefaultRegister(
352 struct xgi_hw_device_info *HwDeviceExtension,
353 unsigned long Port, struct vb_device_info *pVBInfo)
354 {
355 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
356
357 /* keep following setting sequence, each setting in the same reg insert idle */
358 xgifb_reg_set(P3d4, 0x82, 0x77);
359 xgifb_reg_set(P3d4, 0x86, 0x00);
360 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
361 xgifb_reg_set(P3d4, 0x86, 0x88);
362 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
363 xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */
364 xgifb_reg_set(P3d4, 0x82, 0x77);
365 xgifb_reg_set(P3d4, 0x85, 0x00);
366 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
367 xgifb_reg_set(P3d4, 0x85, 0x88);
368 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
369 xgifb_reg_set(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
370 if (HwDeviceExtension->jChipType == XG27)
371 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
372 else
373 xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
374
375 xgifb_reg_set(P3d4, 0x98, 0x01);
376 xgifb_reg_set(P3d4, 0x9A, 0x02);
377 if (HwDeviceExtension->jChipType == XG27)
378 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
379 else
380 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
381 }
382
XGINew_SetDRAMDefaultRegister340(struct xgi_hw_device_info * HwDeviceExtension,unsigned long Port,struct vb_device_info * pVBInfo)383 static void XGINew_SetDRAMDefaultRegister340(
384 struct xgi_hw_device_info *HwDeviceExtension,
385 unsigned long Port, struct vb_device_info *pVBInfo)
386 {
387 unsigned char temp, temp1, temp2, temp3, i, j, k;
388
389 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
390
391 xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][XGINew_RAMType]);
392 xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][XGINew_RAMType]);
393 xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][XGINew_RAMType]);
394 xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][XGINew_RAMType]);
395
396 temp2 = 0;
397 for (i = 0; i < 4; i++) {
398 temp = pVBInfo->CR6B[XGINew_RAMType][i]; /* CR6B DQS fine tune delay */
399 for (j = 0; j < 4; j++) {
400 temp1 = ((temp >> (2 * j)) & 0x03) << 2;
401 temp2 |= temp1;
402 xgifb_reg_set(P3d4, 0x6B, temp2);
403 xgifb_reg_get(P3d4, 0x6B); /* Insert read command for delay */
404 temp2 &= 0xF0;
405 temp2 += 0x10;
406 }
407 }
408
409 temp2 = 0;
410 for (i = 0; i < 4; i++) {
411 temp = pVBInfo->CR6E[XGINew_RAMType][i]; /* CR6E DQM fine tune delay */
412 for (j = 0; j < 4; j++) {
413 temp1 = ((temp >> (2 * j)) & 0x03) << 2;
414 temp2 |= temp1;
415 xgifb_reg_set(P3d4, 0x6E, temp2);
416 xgifb_reg_get(P3d4, 0x6E); /* Insert read command for delay */
417 temp2 &= 0xF0;
418 temp2 += 0x10;
419 }
420 }
421
422 temp3 = 0;
423 for (k = 0; k < 4; k++) {
424 xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3); /* CR6E_D[1:0] select channel */
425 temp2 = 0;
426 for (i = 0; i < 8; i++) {
427 temp = pVBInfo->CR6F[XGINew_RAMType][8 * k + i]; /* CR6F DQ fine tune delay */
428 for (j = 0; j < 4; j++) {
429 temp1 = (temp >> (2 * j)) & 0x03;
430 temp2 |= temp1;
431 xgifb_reg_set(P3d4, 0x6F, temp2);
432 xgifb_reg_get(P3d4, 0x6F); /* Insert read command for delay */
433 temp2 &= 0xF8;
434 temp2 += 0x08;
435 }
436 }
437 temp3 += 0x01;
438 }
439
440 xgifb_reg_set(P3d4, 0x80, pVBInfo->CR40[9][XGINew_RAMType]); /* CR80 */
441 xgifb_reg_set(P3d4, 0x81, pVBInfo->CR40[10][XGINew_RAMType]); /* CR81 */
442
443 temp2 = 0x80;
444 temp = pVBInfo->CR89[XGINew_RAMType][0]; /* CR89 terminator type select */
445 for (j = 0; j < 4; j++) {
446 temp1 = (temp >> (2 * j)) & 0x03;
447 temp2 |= temp1;
448 xgifb_reg_set(P3d4, 0x89, temp2);
449 xgifb_reg_get(P3d4, 0x89); /* Insert read command for delay */
450 temp2 &= 0xF0;
451 temp2 += 0x10;
452 }
453
454 temp = pVBInfo->CR89[XGINew_RAMType][1];
455 temp1 = temp & 0x03;
456 temp2 |= temp1;
457 xgifb_reg_set(P3d4, 0x89, temp2);
458
459 temp = pVBInfo->CR40[3][XGINew_RAMType];
460 temp1 = temp & 0x0F;
461 temp2 = (temp >> 4) & 0x07;
462 temp3 = temp & 0x80;
463 xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
464 xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
465 xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
466 xgifb_reg_set(P3d4, 0x41, pVBInfo->CR40[0][XGINew_RAMType]); /* CR41 */
467
468 if (HwDeviceExtension->jChipType == XG27)
469 xgifb_reg_set(P3d4, 0x8F, *pVBInfo->pCR8F); /* CR8F */
470
471 for (j = 0; j <= 6; j++)
472 xgifb_reg_set(P3d4, (0x90 + j),
473 pVBInfo->CR40[14 + j][XGINew_RAMType]); /* CR90 - CR96 */
474
475 for (j = 0; j <= 2; j++)
476 xgifb_reg_set(P3d4, (0xC3 + j),
477 pVBInfo->CR40[21 + j][XGINew_RAMType]); /* CRC3 - CRC5 */
478
479 for (j = 0; j < 2; j++)
480 xgifb_reg_set(P3d4, (0x8A + j),
481 pVBInfo->CR40[1 + j][XGINew_RAMType]); /* CR8A - CR8B */
482
483 if ((HwDeviceExtension->jChipType == XG41) || (HwDeviceExtension->jChipType == XG42))
484 xgifb_reg_set(P3d4, 0x8C, 0x87);
485
486 xgifb_reg_set(P3d4, 0x59, pVBInfo->CR40[4][XGINew_RAMType]); /* CR59 */
487
488 xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
489 xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
490 xgifb_reg_set(P3d4, 0xCF, *pVBInfo->pCRCF); /* CRCF */
491 if (XGINew_RAMType) {
492 /* xgifb_reg_set(P3c4, 0x17, 0xC0); */ /* SR17 DDRII */
493 xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
494 if (HwDeviceExtension->jChipType == XG27)
495 xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */
496
497 } else {
498 xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */
499 }
500 xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */
501
502 temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
503 if (temp == 0) {
504 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
505 } else {
506 xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
507 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
508 }
509 xgifb_reg_set(P3c4, 0x1B, pVBInfo->SR15[3][XGINew_RAMType]); /* SR1B */
510 }
511
XGINew_SetDRAMSizingType(int index,unsigned short DRAMTYPE_TABLE[][5],struct vb_device_info * pVBInfo)512 static void XGINew_SetDRAMSizingType(int index,
513 unsigned short DRAMTYPE_TABLE[][5],
514 struct vb_device_info *pVBInfo)
515 {
516 unsigned short data;
517
518 data = DRAMTYPE_TABLE[index][4];
519 xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, data);
520 udelay(15);
521 /* should delay 50 ns */
522 }
523
XGINew_SetDRAMSizeReg(int index,unsigned short DRAMTYPE_TABLE[][5],struct vb_device_info * pVBInfo)524 static unsigned short XGINew_SetDRAMSizeReg(int index,
525 unsigned short DRAMTYPE_TABLE[][5],
526 struct vb_device_info *pVBInfo)
527 {
528 unsigned short data = 0, memsize = 0;
529 int RankSize;
530 unsigned char ChannelNo;
531
532 RankSize = DRAMTYPE_TABLE[index][3] * XGINew_DataBusWidth / 32;
533 data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
534 data &= 0x80;
535
536 if (data == 0x80)
537 RankSize *= 2;
538
539 data = 0;
540
541 if (XGINew_ChannelAB == 3)
542 ChannelNo = 4;
543 else
544 ChannelNo = XGINew_ChannelAB;
545
546 if (ChannelNo * RankSize <= 256) {
547 while ((RankSize >>= 1) > 0)
548 data += 0x10;
549
550 memsize = data >> 4;
551
552 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
553 xgifb_reg_set(pVBInfo->P3c4, 0x14, (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) | (data & 0xF0));
554
555 /* data |= XGINew_ChannelAB << 2; */
556 /* data |= (XGINew_DataBusWidth / 64) << 1; */
557 /* xgifb_reg_set(pVBInfo->P3c4, 0x14, data); */
558
559 /* should delay */
560 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
561 }
562 return memsize;
563 }
564
XGINew_SetDRAMSize20Reg(int index,unsigned short DRAMTYPE_TABLE[][5],struct vb_device_info * pVBInfo)565 static unsigned short XGINew_SetDRAMSize20Reg(int index,
566 unsigned short DRAMTYPE_TABLE[][5],
567 struct vb_device_info *pVBInfo)
568 {
569 unsigned short data = 0, memsize = 0;
570 int RankSize;
571 unsigned char ChannelNo;
572
573 RankSize = DRAMTYPE_TABLE[index][3] * XGINew_DataBusWidth / 8;
574 data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
575 data &= 0x80;
576
577 if (data == 0x80)
578 RankSize *= 2;
579
580 data = 0;
581
582 if (XGINew_ChannelAB == 3)
583 ChannelNo = 4;
584 else
585 ChannelNo = XGINew_ChannelAB;
586
587 if (ChannelNo * RankSize <= 256) {
588 while ((RankSize >>= 1) > 0)
589 data += 0x10;
590
591 memsize = data >> 4;
592
593 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
594 xgifb_reg_set(pVBInfo->P3c4, 0x14, (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) | (data & 0xF0));
595 udelay(15);
596
597 /* data |= XGINew_ChannelAB << 2; */
598 /* data |= (XGINew_DataBusWidth / 64) << 1; */
599 /* xgifb_reg_set(pVBInfo->P3c4, 0x14, data); */
600
601 /* should delay */
602 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
603 }
604 return memsize;
605 }
606
XGINew_ReadWriteRest(unsigned short StopAddr,unsigned short StartAddr,struct vb_device_info * pVBInfo)607 static int XGINew_ReadWriteRest(unsigned short StopAddr,
608 unsigned short StartAddr, struct vb_device_info *pVBInfo)
609 {
610 int i;
611 unsigned long Position = 0;
612
613 *((unsigned long *) (pVBInfo->FBAddr + Position)) = Position;
614
615 for (i = StartAddr; i <= StopAddr; i++) {
616 Position = 1 << i;
617 *((unsigned long *) (pVBInfo->FBAddr + Position)) = Position;
618 }
619
620 udelay(500); /* [Vicent] 2004/04/16. Fix #1759 Memory Size error in Multi-Adapter. */
621
622 Position = 0;
623
624 if ((*(unsigned long *) (pVBInfo->FBAddr + Position)) != Position)
625 return 0;
626
627 for (i = StartAddr; i <= StopAddr; i++) {
628 Position = 1 << i;
629 if ((*(unsigned long *) (pVBInfo->FBAddr + Position)) != Position)
630 return 0;
631 }
632 return 1;
633 }
634
XGINew_CheckFrequence(struct vb_device_info * pVBInfo)635 static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
636 {
637 unsigned char data;
638
639 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
640
641 if ((data & 0x10) == 0) {
642 data = xgifb_reg_get(pVBInfo->P3c4, 0x39);
643 data = (data & 0x02) >> 1;
644 return data;
645 } else {
646 return data & 0x01;
647 }
648 }
649
XGINew_CheckChannel(struct xgi_hw_device_info * HwDeviceExtension,struct vb_device_info * pVBInfo)650 static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
651 struct vb_device_info *pVBInfo)
652 {
653 unsigned char data;
654
655 switch (HwDeviceExtension->jChipType) {
656 case XG20:
657 case XG21:
658 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
659 data = data & 0x01;
660 XGINew_ChannelAB = 1; /* XG20 "JUST" one channel */
661
662 if (data == 0) { /* Single_32_16 */
663
664 if ((HwDeviceExtension->ulVideoMemorySize - 1)
665 > 0x1000000) {
666
667 XGINew_DataBusWidth = 32; /* 32 bits */
668 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1); /* 22bit + 2 rank + 32bit */
669 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
670 udelay(15);
671
672 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
673 return;
674
675 if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x800000) {
676 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x31); /* 22bit + 1 rank + 32bit */
677 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
678 udelay(15);
679
680 if (XGINew_ReadWriteRest(23, 23, pVBInfo) == 1)
681 return;
682 }
683 }
684
685 if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x800000) {
686 XGINew_DataBusWidth = 16; /* 16 bits */
687 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1); /* 22bit + 2 rank + 16bit */
688 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
689 udelay(15);
690
691 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
692 return;
693 else
694 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x31);
695 udelay(15);
696 }
697
698 } else { /* Dual_16_8 */
699 if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x800000) {
700
701 XGINew_DataBusWidth = 16; /* 16 bits */
702 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1); /* (0x31:12x8x2) 22bit + 2 rank */
703 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41); /* 0x41:16Mx16 bit*/
704 udelay(15);
705
706 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
707 return;
708
709 if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x400000) {
710 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x31); /* (0x31:12x8x2) 22bit + 1 rank */
711 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x31); /* 0x31:8Mx16 bit*/
712 udelay(15);
713
714 if (XGINew_ReadWriteRest(22, 22, pVBInfo) == 1)
715 return;
716 }
717 }
718
719 if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x400000) {
720 XGINew_DataBusWidth = 8; /* 8 bits */
721 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1); /* (0x31:12x8x2) 22bit + 2 rank */
722 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30); /* 0x30:8Mx8 bit*/
723 udelay(15);
724
725 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
726 return;
727 else
728 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x31); /* (0x31:12x8x2) 22bit + 1 rank */
729 udelay(15);
730 }
731 }
732 break;
733
734 case XG27:
735 XGINew_DataBusWidth = 16; /* 16 bits */
736 XGINew_ChannelAB = 1; /* Single channel */
737 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
738 break;
739 case XG41:
740 if (XGINew_CheckFrequence(pVBInfo) == 1) {
741 XGINew_DataBusWidth = 32; /* 32 bits */
742 XGINew_ChannelAB = 3; /* Quad Channel */
743 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
744 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
745
746 if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
747 return;
748
749 XGINew_ChannelAB = 2; /* Dual channels */
750 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
751
752 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
753 return;
754
755 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x49);
756
757 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
758 return;
759
760 XGINew_ChannelAB = 3;
761 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
762 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
763
764 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
765 return;
766
767 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
768
769 if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)
770 return;
771 else
772 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x39);
773 } else { /* DDR */
774 XGINew_DataBusWidth = 64; /* 64 bits */
775 XGINew_ChannelAB = 2; /* Dual channels */
776 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
777 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
778
779 if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1)
780 return;
781
782 XGINew_ChannelAB = 1; /* Single channels */
783 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
784
785 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
786 return;
787
788 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x53);
789
790 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
791 return;
792
793 XGINew_ChannelAB = 2; /* Dual channels */
794 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
795 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
796
797 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
798 return;
799
800 XGINew_ChannelAB = 1; /* Single channels */
801 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
802
803 if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)
804 return;
805 else
806 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x43);
807 }
808
809 break;
810
811 case XG42:
812 /*
813 XG42 SR14 D[3] Reserve
814 D[2] = 1, Dual Channel
815 = 0, Single Channel
816
817 It's Different from Other XG40 Series.
818 */
819 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
820 XGINew_DataBusWidth = 32; /* 32 bits */
821 XGINew_ChannelAB = 2; /* 2 Channel */
822 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
823 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
824
825 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
826 return;
827
828 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
829 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34);
830 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
831 return;
832
833 XGINew_ChannelAB = 1; /* Single Channel */
834 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
835 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
836
837 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
838 return;
839 else {
840 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
841 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
842 }
843 } else { /* DDR */
844 XGINew_DataBusWidth = 64; /* 64 bits */
845 XGINew_ChannelAB = 1; /* 1 channels */
846 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
847 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
848
849 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
850 return;
851 else {
852 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
853 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
854 }
855 }
856
857 break;
858
859 default: /* XG40 */
860
861 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
862 XGINew_DataBusWidth = 32; /* 32 bits */
863 XGINew_ChannelAB = 3;
864 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
865 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
866
867 if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
868 return;
869
870 XGINew_ChannelAB = 2; /* 2 channels */
871 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
872
873 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
874 return;
875
876 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
877 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
878
879 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
880 XGINew_ChannelAB = 3; /* 4 channels */
881 } else {
882 XGINew_ChannelAB = 2; /* 2 channels */
883 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
884 }
885 } else { /* DDR */
886 XGINew_DataBusWidth = 64; /* 64 bits */
887 XGINew_ChannelAB = 2; /* 2 channels */
888 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
889 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
890
891 if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1) {
892 return;
893 } else {
894 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
895 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
896 }
897 }
898 break;
899 }
900 }
901
XGINew_DDRSizing340(struct xgi_hw_device_info * HwDeviceExtension,struct vb_device_info * pVBInfo)902 static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
903 struct vb_device_info *pVBInfo)
904 {
905 int i;
906 unsigned short memsize, addr;
907
908 xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
909 xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
910 XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
911
912 if (HwDeviceExtension->jChipType >= XG20) {
913 for (i = 0; i < 12; i++) {
914 XGINew_SetDRAMSizingType(i, XGINew_DDRDRAM_TYPE20, pVBInfo);
915 memsize = XGINew_SetDRAMSize20Reg(i, XGINew_DDRDRAM_TYPE20, pVBInfo);
916 if (memsize == 0)
917 continue;
918
919 addr = memsize + (XGINew_ChannelAB - 2) + 20;
920 if ((HwDeviceExtension->ulVideoMemorySize - 1) < (unsigned long) (1 << addr))
921 continue;
922
923 if (XGINew_ReadWriteRest(addr, 5, pVBInfo) == 1)
924 return 1;
925 }
926 } else {
927 for (i = 0; i < 4; i++) {
928 XGINew_SetDRAMSizingType(i, XGINew_DDRDRAM_TYPE340, pVBInfo);
929 memsize = XGINew_SetDRAMSizeReg(i, XGINew_DDRDRAM_TYPE340, pVBInfo);
930
931 if (memsize == 0)
932 continue;
933
934 addr = memsize + (XGINew_ChannelAB - 2) + 20;
935 if ((HwDeviceExtension->ulVideoMemorySize - 1) < (unsigned long) (1 << addr))
936 continue;
937
938 if (XGINew_ReadWriteRest(addr, 9, pVBInfo) == 1)
939 return 1;
940 }
941 }
942 return 0;
943 }
944
XGINew_SetDRAMSize_340(struct xgi_hw_device_info * HwDeviceExtension,struct vb_device_info * pVBInfo)945 static void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *HwDeviceExtension,
946 struct vb_device_info *pVBInfo)
947 {
948 unsigned short data;
949
950 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
951 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
952
953 XGISetModeNew(HwDeviceExtension, 0x2e);
954
955 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
956 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF)); /* disable read cache */
957 XGI_DisplayOff(HwDeviceExtension, pVBInfo);
958
959 /* data = xgifb_reg_get(pVBInfo->P3c4, 0x1); */
960 /* data |= 0x20 ; */
961 /* xgifb_reg_set(pVBInfo->P3c4, 0x01, data); *//* Turn OFF Display */
962 XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
963 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
964 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20)); /* enable read cache */
965 }
966
ReadVBIOSTablData(unsigned char ChipType,struct vb_device_info * pVBInfo)967 static void ReadVBIOSTablData(unsigned char ChipType, struct vb_device_info *pVBInfo)
968 {
969 volatile unsigned char *pVideoMemory = (unsigned char *) pVBInfo->ROMAddr;
970 unsigned long i;
971 unsigned char j, k;
972 /* Volari customize data area end */
973
974 if (ChipType == XG21) {
975 pVBInfo->IF_DEF_LVDS = 0;
976 if (pVideoMemory[0x65] & 0x1) {
977 pVBInfo->IF_DEF_LVDS = 1;
978 i = pVideoMemory[0x316] | (pVideoMemory[0x317] << 8);
979 j = pVideoMemory[i - 1];
980 if (j != 0xff) {
981 k = 0;
982 do {
983 pVBInfo->XG21_LVDSCapList[k].LVDS_Capability
984 = pVideoMemory[i] | (pVideoMemory[i + 1] << 8);
985 pVBInfo->XG21_LVDSCapList[k].LVDSHT
986 = pVideoMemory[i + 2] | (pVideoMemory[i + 3] << 8);
987 pVBInfo->XG21_LVDSCapList[k].LVDSVT
988 = pVideoMemory[i + 4] | (pVideoMemory[i + 5] << 8);
989 pVBInfo->XG21_LVDSCapList[k].LVDSHDE
990 = pVideoMemory[i + 6] | (pVideoMemory[i + 7] << 8);
991 pVBInfo->XG21_LVDSCapList[k].LVDSVDE
992 = pVideoMemory[i + 8] | (pVideoMemory[i + 9] << 8);
993 pVBInfo->XG21_LVDSCapList[k].LVDSHFP
994 = pVideoMemory[i + 10] | (pVideoMemory[i + 11] << 8);
995 pVBInfo->XG21_LVDSCapList[k].LVDSVFP
996 = pVideoMemory[i + 12] | (pVideoMemory[i + 13] << 8);
997 pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC
998 = pVideoMemory[i + 14] | (pVideoMemory[i + 15] << 8);
999 pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC
1000 = pVideoMemory[i + 16] | (pVideoMemory[i + 17] << 8);
1001 pVBInfo->XG21_LVDSCapList[k].VCLKData1
1002 = pVideoMemory[i + 18];
1003 pVBInfo->XG21_LVDSCapList[k].VCLKData2
1004 = pVideoMemory[i + 19];
1005 pVBInfo->XG21_LVDSCapList[k].PSC_S1
1006 = pVideoMemory[i + 20];
1007 pVBInfo->XG21_LVDSCapList[k].PSC_S2
1008 = pVideoMemory[i + 21];
1009 pVBInfo->XG21_LVDSCapList[k].PSC_S3
1010 = pVideoMemory[i + 22];
1011 pVBInfo->XG21_LVDSCapList[k].PSC_S4
1012 = pVideoMemory[i + 23];
1013 pVBInfo->XG21_LVDSCapList[k].PSC_S5
1014 = pVideoMemory[i + 24];
1015 i += 25;
1016 j--;
1017 k++;
1018 } while ((j > 0) && (k < (sizeof(XGI21_LCDCapList) / sizeof(struct XGI21_LVDSCapStruct))));
1019 } else {
1020 pVBInfo->XG21_LVDSCapList[0].LVDS_Capability
1021 = pVideoMemory[i] | (pVideoMemory[i + 1] << 8);
1022 pVBInfo->XG21_LVDSCapList[0].LVDSHT
1023 = pVideoMemory[i + 2] | (pVideoMemory[i + 3] << 8);
1024 pVBInfo->XG21_LVDSCapList[0].LVDSVT
1025 = pVideoMemory[i + 4] | (pVideoMemory[i + 5] << 8);
1026 pVBInfo->XG21_LVDSCapList[0].LVDSHDE
1027 = pVideoMemory[i + 6] | (pVideoMemory[i + 7] << 8);
1028 pVBInfo->XG21_LVDSCapList[0].LVDSVDE
1029 = pVideoMemory[i + 8] | (pVideoMemory[i + 9] << 8);
1030 pVBInfo->XG21_LVDSCapList[0].LVDSHFP
1031 = pVideoMemory[i + 10] | (pVideoMemory[i + 11] << 8);
1032 pVBInfo->XG21_LVDSCapList[0].LVDSVFP
1033 = pVideoMemory[i + 12] | (pVideoMemory[i + 13] << 8);
1034 pVBInfo->XG21_LVDSCapList[0].LVDSHSYNC
1035 = pVideoMemory[i + 14] | (pVideoMemory[i + 15] << 8);
1036 pVBInfo->XG21_LVDSCapList[0].LVDSVSYNC
1037 = pVideoMemory[i + 16] | (pVideoMemory[i + 17] << 8);
1038 pVBInfo->XG21_LVDSCapList[0].VCLKData1
1039 = pVideoMemory[i + 18];
1040 pVBInfo->XG21_LVDSCapList[0].VCLKData2
1041 = pVideoMemory[i + 19];
1042 pVBInfo->XG21_LVDSCapList[0].PSC_S1
1043 = pVideoMemory[i + 20];
1044 pVBInfo->XG21_LVDSCapList[0].PSC_S2
1045 = pVideoMemory[i + 21];
1046 pVBInfo->XG21_LVDSCapList[0].PSC_S3
1047 = pVideoMemory[i + 22];
1048 pVBInfo->XG21_LVDSCapList[0].PSC_S4
1049 = pVideoMemory[i + 23];
1050 pVBInfo->XG21_LVDSCapList[0].PSC_S5
1051 = pVideoMemory[i + 24];
1052 }
1053 }
1054 }
1055 }
1056
XGINew_ChkSenseStatus(struct xgi_hw_device_info * HwDeviceExtension,struct vb_device_info * pVBInfo)1057 static void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension,
1058 struct vb_device_info *pVBInfo)
1059 {
1060 unsigned short tempbx = 0, temp, tempcx, CR3CData;
1061
1062 temp = xgifb_reg_get(pVBInfo->P3d4, 0x32);
1063
1064 if (temp & Monitor1Sense)
1065 tempbx |= ActiveCRT1;
1066 if (temp & LCDSense)
1067 tempbx |= ActiveLCD;
1068 if (temp & Monitor2Sense)
1069 tempbx |= ActiveCRT2;
1070 if (temp & TVSense) {
1071 tempbx |= ActiveTV;
1072 if (temp & AVIDEOSense)
1073 tempbx |= (ActiveAVideo << 8);
1074 if (temp & SVIDEOSense)
1075 tempbx |= (ActiveSVideo << 8);
1076 if (temp & SCARTSense)
1077 tempbx |= (ActiveSCART << 8);
1078 if (temp & HiTVSense)
1079 tempbx |= (ActiveHiTV << 8);
1080 if (temp & YPbPrSense)
1081 tempbx |= (ActiveYPbPr << 8);
1082 }
1083
1084 tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
1085 tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8);
1086
1087 if (tempbx & tempcx) {
1088 CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
1089 if (!(CR3CData & DisplayDeviceFromCMOS)) {
1090 tempcx = 0x1FF0;
1091 if (*pVBInfo->pSoftSetting & ModeSoftSetting)
1092 tempbx = 0x1FF0;
1093 }
1094 } else {
1095 tempcx = 0x1FF0;
1096 if (*pVBInfo->pSoftSetting & ModeSoftSetting)
1097 tempbx = 0x1FF0;
1098 }
1099
1100 tempbx &= tempcx;
1101 xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
1102 xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
1103 }
1104
XGINew_SetModeScratch(struct xgi_hw_device_info * HwDeviceExtension,struct vb_device_info * pVBInfo)1105 static void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension,
1106 struct vb_device_info *pVBInfo)
1107 {
1108 unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
1109
1110 temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
1111 temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8;
1112 temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
1113
1114 if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
1115 if (temp & ActiveCRT2)
1116 tempcl = SetCRT2ToRAMDAC;
1117 }
1118
1119 if (temp & ActiveLCD) {
1120 tempcl |= SetCRT2ToLCD;
1121 if (temp & DriverMode) {
1122 if (temp & ActiveTV) {
1123 tempch = SetToLCDA | EnableDualEdge;
1124 temp ^= SetCRT2ToLCD;
1125
1126 if ((temp >> 8) & ActiveAVideo)
1127 tempcl |= SetCRT2ToAVIDEO;
1128 if ((temp >> 8) & ActiveSVideo)
1129 tempcl |= SetCRT2ToSVIDEO;
1130 if ((temp >> 8) & ActiveSCART)
1131 tempcl |= SetCRT2ToSCART;
1132
1133 if (pVBInfo->IF_DEF_HiVision == 1) {
1134 if ((temp >> 8) & ActiveHiTV)
1135 tempcl |= SetCRT2ToHiVisionTV;
1136 }
1137
1138 if (pVBInfo->IF_DEF_YPbPr == 1) {
1139 if ((temp >> 8) & ActiveYPbPr)
1140 tempch |= SetYPbPr;
1141 }
1142 }
1143 }
1144 } else {
1145 if ((temp >> 8) & ActiveAVideo)
1146 tempcl |= SetCRT2ToAVIDEO;
1147 if ((temp >> 8) & ActiveSVideo)
1148 tempcl |= SetCRT2ToSVIDEO;
1149 if ((temp >> 8) & ActiveSCART)
1150 tempcl |= SetCRT2ToSCART;
1151
1152 if (pVBInfo->IF_DEF_HiVision == 1) {
1153 if ((temp >> 8) & ActiveHiTV)
1154 tempcl |= SetCRT2ToHiVisionTV;
1155 }
1156
1157 if (pVBInfo->IF_DEF_YPbPr == 1) {
1158 if ((temp >> 8) & ActiveYPbPr)
1159 tempch |= SetYPbPr;
1160 }
1161 }
1162
1163 tempcl |= SetSimuScanMode;
1164 if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) || (temp & ActiveTV)
1165 || (temp & ActiveCRT2)))
1166 tempcl ^= (SetSimuScanMode | SwitchToCRT2);
1167 if ((temp & ActiveLCD) && (temp & ActiveTV))
1168 tempcl ^= (SetSimuScanMode | SwitchToCRT2);
1169 xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl);
1170
1171 CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
1172 CR31Data &= ~(SetNotSimuMode >> 8);
1173 if (!(temp & ActiveCRT1))
1174 CR31Data |= (SetNotSimuMode >> 8);
1175 CR31Data &= ~(DisableCRT2Display >> 8);
1176 if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1177 CR31Data |= (DisableCRT2Display >> 8);
1178 xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data);
1179
1180 CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1181 CR38Data &= ~SetYPbPr;
1182 CR38Data |= tempch;
1183 xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data);
1184
1185 }
1186
XGINew_GetXG21Sense(struct xgi_hw_device_info * HwDeviceExtension,struct vb_device_info * pVBInfo)1187 static void XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension,
1188 struct vb_device_info *pVBInfo)
1189 {
1190 unsigned char Temp;
1191 volatile unsigned char *pVideoMemory =
1192 (unsigned char *) pVBInfo->ROMAddr;
1193
1194 pVBInfo->IF_DEF_LVDS = 0;
1195
1196 #if 1
1197 if ((pVideoMemory[0x65] & 0x01)) { /* For XG21 LVDS */
1198 pVBInfo->IF_DEF_LVDS = 1;
1199 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1200 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0); /* LVDS on chip */
1201 } else {
1202 #endif
1203 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03); /* Enable GPIOA/B read */
1204 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
1205 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
1206 XGINew_SenseLCD(HwDeviceExtension, pVBInfo);
1207 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1208 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20); /* Enable read GPIOF */
1209 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04;
1210 if (!Temp)
1211 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0x80); /* TMDS on chip */
1212 else
1213 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0); /* Only DVO on chip */
1214 xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20); /* Disable read GPIOF */
1215 }
1216 #if 1
1217 }
1218 #endif
1219 }
1220
XGINew_GetXG27Sense(struct xgi_hw_device_info * HwDeviceExtension,struct vb_device_info * pVBInfo)1221 static void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension,
1222 struct vb_device_info *pVBInfo)
1223 {
1224 unsigned char Temp, bCR4A;
1225
1226 pVBInfo->IF_DEF_LVDS = 0;
1227 bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1228 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07); /* Enable GPIOA/B/C read */
1229 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
1230 xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
1231
1232 if (Temp <= 0x02) {
1233 pVBInfo->IF_DEF_LVDS = 1;
1234 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0); /* LVDS setting */
1235 xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
1236 } else {
1237 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0); /* TMDS/DVO setting */
1238 }
1239 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1240
1241 }
1242
GetXG21FPBits(struct vb_device_info * pVBInfo)1243 static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1244 {
1245 unsigned char CR38, CR4A, temp;
1246
1247 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1248 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10); /* enable GPIOE read */
1249 CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1250 temp = 0;
1251 if ((CR38 & 0xE0) > 0x80) {
1252 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1253 temp &= 0x08;
1254 temp >>= 3;
1255 }
1256
1257 xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1258
1259 return temp;
1260 }
1261
GetXG27FPBits(struct vb_device_info * pVBInfo)1262 static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1263 {
1264 unsigned char CR4A, temp;
1265
1266 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1267 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03); /* enable GPIOA/B/C read */
1268 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1269 if (temp <= 2)
1270 temp &= 0x03;
1271 else
1272 temp = ((temp & 0x04) >> 1) || ((~temp) & 0x01);
1273
1274 xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1275
1276 return temp;
1277 }
1278
XGIInitNew(struct xgi_hw_device_info * HwDeviceExtension)1279 unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
1280 {
1281 struct vb_device_info VBINF;
1282 struct vb_device_info *pVBInfo = &VBINF;
1283 unsigned char i, temp = 0, temp1;
1284 /* VBIOSVersion[5]; */
1285 volatile unsigned char *pVideoMemory;
1286
1287 /* unsigned long j, k; */
1288
1289 unsigned long Temp;
1290
1291 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
1292
1293 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1294
1295 pVBInfo->BaseAddr = (unsigned long) HwDeviceExtension->pjIOAddress;
1296
1297 pVideoMemory = (unsigned char *) pVBInfo->ROMAddr;
1298
1299 /* Newdebugcode(0x99); */
1300
1301
1302 /* if (pVBInfo->ROMAddr == 0) */
1303 /* return(0); */
1304
1305 if (pVBInfo->FBAddr == NULL) {
1306 printk("\n pVBInfo->FBAddr == 0 ");
1307 return 0;
1308 }
1309 printk("1");
1310 if (pVBInfo->BaseAddr == 0) {
1311 printk("\npVBInfo->BaseAddr == 0 ");
1312 return 0;
1313 }
1314 printk("2");
1315
1316 outb(0x67, (pVBInfo->BaseAddr + 0x12)); /* 3c2 <- 67 ,ynlai */
1317
1318 pVBInfo->ISXPDOS = 0;
1319 printk("3");
1320
1321 printk("4");
1322
1323 /* VBIOSVersion[4] = 0x0; */
1324
1325 /* 09/07/99 modify by domao */
1326
1327 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14;
1328 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24;
1329 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10;
1330 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e;
1331 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12;
1332 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a;
1333 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16;
1334 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17;
1335 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18;
1336 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19;
1337 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A;
1338 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00;
1339 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04;
1340 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10;
1341 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12;
1342 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14;
1343 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2;
1344 printk("5");
1345
1346 if (HwDeviceExtension->jChipType < XG20) /* kuku 2004/06/25 */
1347 XGI_GetVBType(pVBInfo); /* Run XGI_GetVBType before InitTo330Pointer */
1348
1349 InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1350
1351 /* ReadVBIOSData */
1352 ReadVBIOSTablData(HwDeviceExtension->jChipType, pVBInfo);
1353
1354 /* 1.Openkey */
1355 xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86);
1356 printk("6");
1357
1358 /* GetXG21Sense (GPIO) */
1359 if (HwDeviceExtension->jChipType == XG21)
1360 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo);
1361
1362 if (HwDeviceExtension->jChipType == XG27)
1363 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo);
1364
1365 printk("7");
1366
1367 /* 2.Reset Extended register */
1368
1369 for (i = 0x06; i < 0x20; i++)
1370 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1371
1372 for (i = 0x21; i <= 0x27; i++)
1373 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1374
1375 /* for(i = 0x06; i <= 0x27; i++) */
1376 /* xgifb_reg_set(pVBInfo->P3c4, i, 0); */
1377
1378 printk("8");
1379
1380 for (i = 0x31; i <= 0x3B; i++)
1381 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1382 printk("9");
1383
1384 if (HwDeviceExtension->jChipType == XG42) /* [Hsuan] 2004/08/20 Auto over driver for XG42 */
1385 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
1386
1387 /* for (i = 0x30; i <= 0x3F; i++) */
1388 /* xgifb_reg_set(pVBInfo->P3d4, i, 0); */
1389
1390 for (i = 0x79; i <= 0x7C; i++)
1391 xgifb_reg_set(pVBInfo->P3d4, i, 0); /* shampoo 0208 */
1392
1393 printk("10");
1394
1395 if (HwDeviceExtension->jChipType >= XG20)
1396 xgifb_reg_set(pVBInfo->P3d4, 0x97, *pVBInfo->pXGINew_CR97);
1397
1398 /* 3.SetMemoryClock
1399
1400 XGINew_RAMType = (int)XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1401 */
1402
1403 printk("11");
1404
1405 /* 4.SetDefExt1Regs begin */
1406 xgifb_reg_set(pVBInfo->P3c4, 0x07, *pVBInfo->pSR07);
1407 if (HwDeviceExtension->jChipType == XG27) {
1408 xgifb_reg_set(pVBInfo->P3c4, 0x40, *pVBInfo->pSR40);
1409 xgifb_reg_set(pVBInfo->P3c4, 0x41, *pVBInfo->pSR41);
1410 }
1411 xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
1412 xgifb_reg_set(pVBInfo->P3c4, 0x1F, *pVBInfo->pSR1F);
1413 /* xgifb_reg_set(pVBInfo->P3c4, 0x20, 0x20); */
1414 xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0); /* alan, 2001/6/26 Frame buffer can read/write SR20 */
1415 xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70); /* Hsuan, 2006/01/01 H/W request for slow corner chip */
1416 if (HwDeviceExtension->jChipType == XG27) /* Alan 12/07/2006 */
1417 xgifb_reg_set(pVBInfo->P3c4, 0x36, *pVBInfo->pSR36);
1418
1419 /* SR11 = 0x0F; */
1420 /* xgifb_reg_set(pVBInfo->P3c4, 0x11, SR11); */
1421
1422 printk("12");
1423
1424 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1425 /* Set AGP Rate */
1426 /*
1427 temp1 = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
1428 temp1 &= 0x02;
1429 if (temp1 == 0x02) {
1430 outl(0x80000000, 0xcf8);
1431 ChipsetID = inl(0x0cfc);
1432 outl(0x8000002C, 0xcf8);
1433 VendorID = inl(0x0cfc);
1434 VendorID &= 0x0000FFFF;
1435 outl(0x8001002C, 0xcf8);
1436 GraphicVendorID = inl(0x0cfc);
1437 GraphicVendorID &= 0x0000FFFF;
1438
1439 if (ChipsetID == 0x7301039)
1440 xgifb_reg_set(pVBInfo->P3d4, 0x5F, 0x09);
1441
1442 ChipsetID &= 0x0000FFFF;
1443
1444 if ((ChipsetID == 0x700E) || (ChipsetID == 0x1022) || (ChipsetID == 0x1106) || (ChipsetID == 0x10DE)) {
1445 if (ChipsetID == 0x1106) {
1446 if ((VendorID == 0x1019) && (GraphicVendorID == 0x1019))
1447 xgifb_reg_set(pVBInfo->P3d4, 0x5F, 0x0D);
1448 else
1449 xgifb_reg_set(pVBInfo->P3d4, 0x5F, 0x0B);
1450 } else {
1451 xgifb_reg_set(pVBInfo->P3d4, 0x5F, 0x0B);
1452 }
1453 }
1454 }
1455 */
1456
1457 printk("13");
1458
1459 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1460 for (i = 0x47; i <= 0x4C; i++)
1461 xgifb_reg_set(pVBInfo->P3d4, i, pVBInfo->AGPReg[i - 0x47]);
1462
1463 for (i = 0x70; i <= 0x71; i++)
1464 xgifb_reg_set(pVBInfo->P3d4, i, pVBInfo->AGPReg[6 + i - 0x70]);
1465
1466 for (i = 0x74; i <= 0x77; i++)
1467 xgifb_reg_set(pVBInfo->P3d4, i, pVBInfo->AGPReg[8 + i - 0x74]);
1468 /* Set AGP customize registers (in SetDefAGPRegs) End */
1469 /* [Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */
1470 /* outl(0x80000000, 0xcf8); */
1471 /* ChipsetID = inl(0x0cfc); */
1472 /* if (ChipsetID == 0x25308086) */
1473 /* xgifb_reg_set(pVBInfo->P3d4, 0x77, 0xF0); */
1474
1475 HwDeviceExtension->pQueryVGAConfigSpace(HwDeviceExtension, 0x50, 0, &Temp); /* Get */
1476 Temp >>= 20;
1477 Temp &= 0xF;
1478
1479 if (Temp == 1)
1480 xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
1481 printk("14");
1482 } /* != XG20 */
1483
1484 /* Set PCI */
1485 xgifb_reg_set(pVBInfo->P3c4, 0x23, *pVBInfo->pSR23);
1486 xgifb_reg_set(pVBInfo->P3c4, 0x24, *pVBInfo->pSR24);
1487 xgifb_reg_set(pVBInfo->P3c4, 0x25, pVBInfo->SR25[0]);
1488 printk("15");
1489
1490 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1491 /* Set VB */
1492 XGI_UnLockCRT2(HwDeviceExtension, pVBInfo);
1493 xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00); /* alan, disable VideoCapture */
1494 xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
1495 temp1 = (unsigned char) xgifb_reg_get(pVBInfo->P3d4, 0x7B); /* chk if BCLK>=100MHz */
1496 temp = (unsigned char) ((temp1 >> 4) & 0x0F);
1497
1498 xgifb_reg_set(pVBInfo->Part1Port, 0x02, (*pVBInfo->pCRT2Data_1_2));
1499
1500 printk("16");
1501
1502 xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
1503 } /* != XG20 */
1504
1505 xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
1506
1507 if ((HwDeviceExtension->jChipType == XG42)
1508 && XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) { /* Not DDR */
1509 xgifb_reg_set(pVBInfo->P3c4, 0x31, (*pVBInfo->pSR31 & 0x3F) | 0x40);
1510 xgifb_reg_set(pVBInfo->P3c4, 0x32, (*pVBInfo->pSR32 & 0xFC) | 0x01);
1511 } else {
1512 xgifb_reg_set(pVBInfo->P3c4, 0x31, *pVBInfo->pSR31);
1513 xgifb_reg_set(pVBInfo->P3c4, 0x32, *pVBInfo->pSR32);
1514 }
1515 xgifb_reg_set(pVBInfo->P3c4, 0x33, *pVBInfo->pSR33);
1516 printk("17");
1517
1518 /*
1519 SetPowerConsume (HwDeviceExtension, pVBInfo->P3c4); */
1520
1521 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1522 if (XGI_BridgeIsOn(pVBInfo) == 1) {
1523 if (pVBInfo->IF_DEF_LVDS == 0) {
1524 xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
1525 xgifb_reg_set(pVBInfo->Part4Port, 0x0D, *pVBInfo->pCRT2Data_4_D);
1526 xgifb_reg_set(pVBInfo->Part4Port, 0x0E, *pVBInfo->pCRT2Data_4_E);
1527 xgifb_reg_set(pVBInfo->Part4Port, 0x10, *pVBInfo->pCRT2Data_4_10);
1528 xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
1529 }
1530
1531 XGI_LockCRT2(HwDeviceExtension, pVBInfo);
1532 }
1533 } /* != XG20 */
1534 printk("18");
1535
1536 printk("181");
1537
1538 printk("182");
1539
1540 XGI_SenseCRT1(pVBInfo);
1541
1542 printk("183");
1543 /* XGINew_DetectMonitor(HwDeviceExtension); */
1544 pVBInfo->IF_DEF_CH7007 = 0;
1545 if ((HwDeviceExtension->jChipType == XG21) && (pVBInfo->IF_DEF_CH7007)) {
1546 printk("184");
1547 XGI_GetSenseStatus(HwDeviceExtension, pVBInfo); /* sense CRT2 */
1548 printk("185");
1549
1550 }
1551 if (HwDeviceExtension->jChipType == XG21) {
1552 printk("186");
1553
1554 xgifb_reg_and_or(pVBInfo->P3d4, 0x32, ~Monitor1Sense, Monitor1Sense); /* Z9 default has CRT */
1555 temp = GetXG21FPBits(pVBInfo);
1556 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
1557 printk("187");
1558
1559 }
1560 if (HwDeviceExtension->jChipType == XG27) {
1561 xgifb_reg_and_or(pVBInfo->P3d4, 0x32, ~Monitor1Sense, Monitor1Sense); /* Z9 default has CRT */
1562 temp = GetXG27FPBits(pVBInfo);
1563 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
1564 }
1565 printk("19");
1566
1567 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1568
1569 XGINew_SetDRAMDefaultRegister340(HwDeviceExtension, pVBInfo->P3d4, pVBInfo);
1570
1571 printk("20");
1572 XGINew_SetDRAMSize_340(HwDeviceExtension, pVBInfo);
1573 printk("21");
1574
1575 printk("22");
1576
1577 /* SetDefExt2Regs begin */
1578 /*
1579 AGP = 1;
1580 temp = (unsigned char) xgifb_reg_get(pVBInfo->P3c4, 0x3A);
1581 temp &= 0x30;
1582 if (temp == 0x30)
1583 AGP = 0;
1584
1585 if (AGP == 0)
1586 *pVBInfo->pSR21 &= 0xEF;
1587
1588 xgifb_reg_set(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
1589 if (AGP == 1)
1590 *pVBInfo->pSR22 &= 0x20;
1591 xgifb_reg_set(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22);
1592 */
1593 /* base = 0x80000000; */
1594 /* OutPortLong(0xcf8, base); */
1595 /* Temp = (InPortLong(0xcfc) & 0xFFFF); */
1596 /* if (Temp == 0x1039) { */
1597 xgifb_reg_set(pVBInfo->P3c4, 0x22, (unsigned char) ((*pVBInfo->pSR22) & 0xFE));
1598 /* } else { */
1599 /* xgifb_reg_set(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22); */
1600 /* } */
1601
1602 xgifb_reg_set(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
1603
1604 printk("23");
1605
1606 XGINew_ChkSenseStatus(HwDeviceExtension, pVBInfo);
1607 XGINew_SetModeScratch(HwDeviceExtension, pVBInfo);
1608
1609 printk("24");
1610
1611 xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87);
1612 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x31);
1613 printk("25");
1614
1615 return 1;
1616 } /* end of init */
1617