1 #ifndef _ASM_X86_PROCESSOR_FLAGS_H
2 #define _ASM_X86_PROCESSOR_FLAGS_H
3 /* Various flags defined: can be included from assembler. */
4 
5 /*
6  * EFLAGS bits
7  */
8 #define X86_EFLAGS_CF	0x00000001 /* Carry Flag */
9 #define X86_EFLAGS_BIT1	0x00000002 /* Bit 1 - always on */
10 #define X86_EFLAGS_PF	0x00000004 /* Parity Flag */
11 #define X86_EFLAGS_AF	0x00000010 /* Auxiliary carry Flag */
12 #define X86_EFLAGS_ZF	0x00000040 /* Zero Flag */
13 #define X86_EFLAGS_SF	0x00000080 /* Sign Flag */
14 #define X86_EFLAGS_TF	0x00000100 /* Trap Flag */
15 #define X86_EFLAGS_IF	0x00000200 /* Interrupt Flag */
16 #define X86_EFLAGS_DF	0x00000400 /* Direction Flag */
17 #define X86_EFLAGS_OF	0x00000800 /* Overflow Flag */
18 #define X86_EFLAGS_IOPL	0x00003000 /* IOPL mask */
19 #define X86_EFLAGS_NT	0x00004000 /* Nested Task */
20 #define X86_EFLAGS_RF	0x00010000 /* Resume Flag */
21 #define X86_EFLAGS_VM	0x00020000 /* Virtual Mode */
22 #define X86_EFLAGS_AC	0x00040000 /* Alignment Check */
23 #define X86_EFLAGS_VIF	0x00080000 /* Virtual Interrupt Flag */
24 #define X86_EFLAGS_VIP	0x00100000 /* Virtual Interrupt Pending */
25 #define X86_EFLAGS_ID	0x00200000 /* CPUID detection flag */
26 
27 /*
28  * Basic CPU control in CR0
29  */
30 #define X86_CR0_PE	0x00000001 /* Protection Enable */
31 #define X86_CR0_MP	0x00000002 /* Monitor Coprocessor */
32 #define X86_CR0_EM	0x00000004 /* Emulation */
33 #define X86_CR0_TS	0x00000008 /* Task Switched */
34 #define X86_CR0_ET	0x00000010 /* Extension Type */
35 #define X86_CR0_NE	0x00000020 /* Numeric Error */
36 #define X86_CR0_WP	0x00010000 /* Write Protect */
37 #define X86_CR0_AM	0x00040000 /* Alignment Mask */
38 #define X86_CR0_NW	0x20000000 /* Not Write-through */
39 #define X86_CR0_CD	0x40000000 /* Cache Disable */
40 #define X86_CR0_PG	0x80000000 /* Paging */
41 
42 /*
43  * Paging options in CR3
44  */
45 #define X86_CR3_PWT	0x00000008 /* Page Write Through */
46 #define X86_CR3_PCD	0x00000010 /* Page Cache Disable */
47 
48 /*
49  * Intel CPU features in CR4
50  */
51 #define X86_CR4_VME	0x00000001 /* enable vm86 extensions */
52 #define X86_CR4_PVI	0x00000002 /* virtual interrupts flag enable */
53 #define X86_CR4_TSD	0x00000004 /* disable time stamp at ipl 3 */
54 #define X86_CR4_DE	0x00000008 /* enable debugging extensions */
55 #define X86_CR4_PSE	0x00000010 /* enable page size extensions */
56 #define X86_CR4_PAE	0x00000020 /* enable physical address extensions */
57 #define X86_CR4_MCE	0x00000040 /* Machine check enable */
58 #define X86_CR4_PGE	0x00000080 /* enable global pages */
59 #define X86_CR4_PCE	0x00000100 /* enable performance counters at ipl 3 */
60 #define X86_CR4_OSFXSR	0x00000200 /* enable fast FPU save and restore */
61 #define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
62 #define X86_CR4_VMXE	0x00002000 /* enable VMX virtualization */
63 #define X86_CR4_RDWRGSFS 0x00010000 /* enable RDWRGSFS support */
64 #define X86_CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */
65 #define X86_CR4_SMEP	0x00100000 /* enable SMEP support */
66 
67 /*
68  * x86-64 Task Priority Register, CR8
69  */
70 #define X86_CR8_TPR	0x0000000F /* task priority register */
71 
72 /*
73  * AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h>
74  */
75 
76 /*
77  *      NSC/Cyrix CPU configuration register indexes
78  */
79 #define CX86_PCR0	0x20
80 #define CX86_GCR	0xb8
81 #define CX86_CCR0	0xc0
82 #define CX86_CCR1	0xc1
83 #define CX86_CCR2	0xc2
84 #define CX86_CCR3	0xc3
85 #define CX86_CCR4	0xe8
86 #define CX86_CCR5	0xe9
87 #define CX86_CCR6	0xea
88 #define CX86_CCR7	0xeb
89 #define CX86_PCR1	0xf0
90 #define CX86_DIR0	0xfe
91 #define CX86_DIR1	0xff
92 #define CX86_ARR_BASE	0xc4
93 #define CX86_RCR_BASE	0xdc
94 
95 #ifdef __KERNEL__
96 #ifdef CONFIG_VM86
97 #define X86_VM_MASK	X86_EFLAGS_VM
98 #else
99 #define X86_VM_MASK	0 /* No VM86 support */
100 #endif
101 #endif
102 
103 #endif /* _ASM_X86_PROCESSOR_FLAGS_H */
104