1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2012 Avionic Design GmbH
4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 */
6
7 #ifndef TEGRA_DC_H
8 #define TEGRA_DC_H 1
9
10 #include <linux/host1x.h>
11
12 #include <drm/drm_crtc.h>
13
14 #include "drm.h"
15
16 struct tegra_output;
17
18 #define TEGRA_DC_LEGACY_PLANES_NUM 7
19
20 struct tegra_dc_state {
21 struct drm_crtc_state base;
22
23 struct clk *clk;
24 unsigned long pclk;
25 unsigned int div;
26
27 u32 planes;
28 };
29
to_dc_state(struct drm_crtc_state * state)30 static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state)
31 {
32 if (state)
33 return container_of(state, struct tegra_dc_state, base);
34
35 return NULL;
36 }
37
38 struct tegra_dc_stats {
39 unsigned long frames;
40 unsigned long vblank;
41 unsigned long underflow;
42 unsigned long overflow;
43
44 unsigned long frames_total;
45 unsigned long vblank_total;
46 unsigned long underflow_total;
47 unsigned long overflow_total;
48 };
49
50 struct tegra_windowgroup_soc {
51 unsigned int index;
52 unsigned int dc;
53 const unsigned int *windows;
54 unsigned int num_windows;
55 };
56
57 struct tegra_dc_soc_info {
58 bool supports_background_color;
59 bool supports_interlacing;
60 bool supports_cursor;
61 bool supports_block_linear;
62 bool supports_sector_layout;
63 bool has_legacy_blending;
64 unsigned int pitch_align;
65 bool has_powergate;
66 bool coupled_pm;
67 bool has_nvdisplay;
68 const struct tegra_windowgroup_soc *wgrps;
69 unsigned int num_wgrps;
70 const u32 *primary_formats;
71 unsigned int num_primary_formats;
72 const u32 *overlay_formats;
73 unsigned int num_overlay_formats;
74 const u64 *modifiers;
75 bool has_win_a_without_filters;
76 bool has_win_b_vfilter_mem_client;
77 bool has_win_c_without_vert_filter;
78 bool plane_tiled_memory_bandwidth_x2;
79 bool has_pll_d2_out0;
80 };
81
82 struct tegra_dc {
83 struct host1x_client client;
84 struct host1x_syncpt *syncpt;
85 struct device *dev;
86
87 struct drm_crtc base;
88 unsigned int powergate;
89 int pipe;
90
91 struct clk *clk;
92 struct reset_control *rst;
93 void __iomem *regs;
94 int irq;
95
96 struct tegra_output *rgb;
97
98 struct tegra_dc_stats stats;
99 struct list_head list;
100
101 struct drm_info_list *debugfs_files;
102
103 const struct tegra_dc_soc_info *soc;
104
105 bool has_opp_table;
106 };
107
108 static inline struct tegra_dc *
host1x_client_to_dc(struct host1x_client * client)109 host1x_client_to_dc(struct host1x_client *client)
110 {
111 return container_of(client, struct tegra_dc, client);
112 }
113
to_tegra_dc(struct drm_crtc * crtc)114 static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc)
115 {
116 return crtc ? container_of(crtc, struct tegra_dc, base) : NULL;
117 }
118
tegra_dc_writel(struct tegra_dc * dc,u32 value,unsigned int offset)119 static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value,
120 unsigned int offset)
121 {
122 trace_dc_writel(dc->dev, offset, value);
123 writel(value, dc->regs + (offset << 2));
124 }
125
tegra_dc_readl(struct tegra_dc * dc,unsigned int offset)126 static inline u32 tegra_dc_readl(struct tegra_dc *dc, unsigned int offset)
127 {
128 u32 value = readl(dc->regs + (offset << 2));
129
130 trace_dc_readl(dc->dev, offset, value);
131
132 return value;
133 }
134
135 struct tegra_dc_window {
136 struct {
137 unsigned int x;
138 unsigned int y;
139 unsigned int w;
140 unsigned int h;
141 } src;
142 struct {
143 unsigned int x;
144 unsigned int y;
145 unsigned int w;
146 unsigned int h;
147 } dst;
148 unsigned int bits_per_pixel;
149 unsigned int stride[2];
150 unsigned long base[3];
151 unsigned int zpos;
152 bool reflect_x;
153 bool reflect_y;
154
155 struct tegra_bo_tiling tiling;
156 u32 format;
157 u32 swap;
158 };
159
160 /* from dc.c */
161 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev);
162 void tegra_dc_commit(struct tegra_dc *dc);
163 int tegra_dc_state_setup_clock(struct tegra_dc *dc,
164 struct drm_crtc_state *crtc_state,
165 struct clk *clk, unsigned long pclk,
166 unsigned int div);
167 void tegra_crtc_atomic_post_commit(struct drm_crtc *crtc,
168 struct drm_atomic_state *state);
169
170 /* from rgb.c */
171 int tegra_dc_rgb_probe(struct tegra_dc *dc);
172 int tegra_dc_rgb_remove(struct tegra_dc *dc);
173 int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc);
174 int tegra_dc_rgb_exit(struct tegra_dc *dc);
175
176 #define DC_CMD_GENERAL_INCR_SYNCPT 0x000
177 #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001
178 #define SYNCPT_CNTRL_NO_STALL (1 << 8)
179 #define SYNCPT_CNTRL_SOFT_RESET (1 << 0)
180 #define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002
181 #define DC_CMD_WIN_A_INCR_SYNCPT 0x008
182 #define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009
183 #define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a
184 #define DC_CMD_WIN_B_INCR_SYNCPT 0x010
185 #define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011
186 #define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012
187 #define DC_CMD_WIN_C_INCR_SYNCPT 0x018
188 #define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL 0x019
189 #define DC_CMD_WIN_C_INCR_SYNCPT_ERROR 0x01a
190 #define DC_CMD_CONT_SYNCPT_VSYNC 0x028
191 #define SYNCPT_VSYNC_ENABLE (1 << 8)
192 #define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031
193 #define DC_CMD_DISPLAY_COMMAND 0x032
194 #define DISP_CTRL_MODE_STOP (0 << 5)
195 #define DISP_CTRL_MODE_C_DISPLAY (1 << 5)
196 #define DISP_CTRL_MODE_NC_DISPLAY (2 << 5)
197 #define DISP_CTRL_MODE_MASK (3 << 5)
198 #define DC_CMD_SIGNAL_RAISE 0x033
199 #define DC_CMD_DISPLAY_POWER_CONTROL 0x036
200 #define PW0_ENABLE (1 << 0)
201 #define PW1_ENABLE (1 << 2)
202 #define PW2_ENABLE (1 << 4)
203 #define PW3_ENABLE (1 << 6)
204 #define PW4_ENABLE (1 << 8)
205 #define PM0_ENABLE (1 << 16)
206 #define PM1_ENABLE (1 << 18)
207
208 #define DC_CMD_INT_STATUS 0x037
209 #define DC_CMD_INT_MASK 0x038
210 #define DC_CMD_INT_ENABLE 0x039
211 #define DC_CMD_INT_TYPE 0x03a
212 #define DC_CMD_INT_POLARITY 0x03b
213 #define CTXSW_INT (1 << 0)
214 #define FRAME_END_INT (1 << 1)
215 #define VBLANK_INT (1 << 2)
216 #define V_PULSE3_INT (1 << 4)
217 #define V_PULSE2_INT (1 << 5)
218 #define REGION_CRC_INT (1 << 6)
219 #define REG_TMOUT_INT (1 << 7)
220 #define WIN_A_UF_INT (1 << 8)
221 #define WIN_B_UF_INT (1 << 9)
222 #define WIN_C_UF_INT (1 << 10)
223 #define MSF_INT (1 << 12)
224 #define WIN_A_OF_INT (1 << 14)
225 #define WIN_B_OF_INT (1 << 15)
226 #define WIN_C_OF_INT (1 << 16)
227 #define HEAD_UF_INT (1 << 23)
228 #define SD3_BUCKET_WALK_DONE_INT (1 << 24)
229 #define DSC_OBUF_UF_INT (1 << 26)
230 #define DSC_RBUF_UF_INT (1 << 27)
231 #define DSC_BBUF_UF_INT (1 << 28)
232 #define DSC_TO_UF_INT (1 << 29)
233
234 #define DC_CMD_SIGNAL_RAISE1 0x03c
235 #define DC_CMD_SIGNAL_RAISE2 0x03d
236 #define DC_CMD_SIGNAL_RAISE3 0x03e
237
238 #define DC_CMD_STATE_ACCESS 0x040
239 #define READ_MUX (1 << 0)
240 #define WRITE_MUX (1 << 2)
241
242 #define DC_CMD_STATE_CONTROL 0x041
243 #define GENERAL_ACT_REQ (1 << 0)
244 #define WIN_A_ACT_REQ (1 << 1)
245 #define WIN_B_ACT_REQ (1 << 2)
246 #define WIN_C_ACT_REQ (1 << 3)
247 #define CURSOR_ACT_REQ (1 << 7)
248 #define GENERAL_UPDATE (1 << 8)
249 #define WIN_A_UPDATE (1 << 9)
250 #define WIN_B_UPDATE (1 << 10)
251 #define WIN_C_UPDATE (1 << 11)
252 #define CURSOR_UPDATE (1 << 15)
253 #define COMMON_ACTREQ (1 << 16)
254 #define COMMON_UPDATE (1 << 17)
255 #define NC_HOST_TRIG (1 << 24)
256
257 #define DC_CMD_DISPLAY_WINDOW_HEADER 0x042
258 #define WINDOW_A_SELECT (1 << 4)
259 #define WINDOW_B_SELECT (1 << 5)
260 #define WINDOW_C_SELECT (1 << 6)
261
262 #define DC_CMD_REG_ACT_CONTROL 0x043
263
264 #define DC_COM_CRC_CONTROL 0x300
265 #define DC_COM_CRC_CONTROL_ALWAYS (1 << 3)
266 #define DC_COM_CRC_CONTROL_FULL_FRAME (0 << 2)
267 #define DC_COM_CRC_CONTROL_ACTIVE_DATA (1 << 2)
268 #define DC_COM_CRC_CONTROL_WAIT (1 << 1)
269 #define DC_COM_CRC_CONTROL_ENABLE (1 << 0)
270 #define DC_COM_CRC_CHECKSUM 0x301
271 #define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x))
272 #define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x))
273 #define LVS_OUTPUT_POLARITY_LOW (1 << 28)
274 #define LHS_OUTPUT_POLARITY_LOW (1 << 30)
275 #define DC_COM_PIN_OUTPUT_DATA(x) (0x30a + (x))
276 #define DC_COM_PIN_INPUT_ENABLE(x) (0x30e + (x))
277 #define DC_COM_PIN_INPUT_DATA(x) (0x312 + (x))
278 #define DC_COM_PIN_OUTPUT_SELECT(x) (0x314 + (x))
279
280 #define DC_COM_PIN_MISC_CONTROL 0x31b
281 #define DC_COM_PIN_PM0_CONTROL 0x31c
282 #define DC_COM_PIN_PM0_DUTY_CYCLE 0x31d
283 #define DC_COM_PIN_PM1_CONTROL 0x31e
284 #define DC_COM_PIN_PM1_DUTY_CYCLE 0x31f
285
286 #define DC_COM_SPI_CONTROL 0x320
287 #define DC_COM_SPI_START_BYTE 0x321
288 #define DC_COM_HSPI_WRITE_DATA_AB 0x322
289 #define DC_COM_HSPI_WRITE_DATA_CD 0x323
290 #define DC_COM_HSPI_CS_DC 0x324
291 #define DC_COM_SCRATCH_REGISTER_A 0x325
292 #define DC_COM_SCRATCH_REGISTER_B 0x326
293 #define DC_COM_GPIO_CTRL 0x327
294 #define DC_COM_GPIO_DEBOUNCE_COUNTER 0x328
295 #define DC_COM_CRC_CHECKSUM_LATCHED 0x329
296
297 #define DC_COM_RG_UNDERFLOW 0x365
298 #define UNDERFLOW_MODE_RED (1 << 8)
299 #define UNDERFLOW_REPORT_ENABLE (1 << 0)
300
301 #define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400
302 #define H_PULSE0_ENABLE (1 << 8)
303 #define H_PULSE1_ENABLE (1 << 10)
304 #define H_PULSE2_ENABLE (1 << 12)
305
306 #define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401
307
308 #define DC_DISP_DISP_WIN_OPTIONS 0x402
309 #define HDMI_ENABLE (1 << 30)
310 #define DSI_ENABLE (1 << 29)
311 #define SOR1_TIMING_CYA (1 << 27)
312 #define CURSOR_ENABLE (1 << 16)
313
314 #define SOR_ENABLE(x) (1 << (25 + (((x) > 1) ? ((x) + 1) : (x))))
315
316 #define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403
317 #define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24)
318 #define WINDOW_A_THRESHOLD(x) (((x) & 0x7f) << 16)
319 #define WINDOW_B_THRESHOLD(x) (((x) & 0x7f) << 8)
320 #define WINDOW_C_THRESHOLD(x) (((x) & 0xff) << 0)
321
322 #define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404
323 #define CURSOR_DELAY(x) (((x) & 0x3f) << 24)
324 #define WINDOW_A_DELAY(x) (((x) & 0x3f) << 16)
325 #define WINDOW_B_DELAY(x) (((x) & 0x3f) << 8)
326 #define WINDOW_C_DELAY(x) (((x) & 0x3f) << 0)
327
328 #define DC_DISP_DISP_TIMING_OPTIONS 0x405
329 #define VSYNC_H_POSITION(x) ((x) & 0xfff)
330
331 #define DC_DISP_REF_TO_SYNC 0x406
332 #define DC_DISP_SYNC_WIDTH 0x407
333 #define DC_DISP_BACK_PORCH 0x408
334 #define DC_DISP_ACTIVE 0x409
335 #define DC_DISP_FRONT_PORCH 0x40a
336 #define DC_DISP_H_PULSE0_CONTROL 0x40b
337 #define DC_DISP_H_PULSE0_POSITION_A 0x40c
338 #define DC_DISP_H_PULSE0_POSITION_B 0x40d
339 #define DC_DISP_H_PULSE0_POSITION_C 0x40e
340 #define DC_DISP_H_PULSE0_POSITION_D 0x40f
341 #define DC_DISP_H_PULSE1_CONTROL 0x410
342 #define DC_DISP_H_PULSE1_POSITION_A 0x411
343 #define DC_DISP_H_PULSE1_POSITION_B 0x412
344 #define DC_DISP_H_PULSE1_POSITION_C 0x413
345 #define DC_DISP_H_PULSE1_POSITION_D 0x414
346 #define DC_DISP_H_PULSE2_CONTROL 0x415
347 #define DC_DISP_H_PULSE2_POSITION_A 0x416
348 #define DC_DISP_H_PULSE2_POSITION_B 0x417
349 #define DC_DISP_H_PULSE2_POSITION_C 0x418
350 #define DC_DISP_H_PULSE2_POSITION_D 0x419
351 #define DC_DISP_V_PULSE0_CONTROL 0x41a
352 #define DC_DISP_V_PULSE0_POSITION_A 0x41b
353 #define DC_DISP_V_PULSE0_POSITION_B 0x41c
354 #define DC_DISP_V_PULSE0_POSITION_C 0x41d
355 #define DC_DISP_V_PULSE1_CONTROL 0x41e
356 #define DC_DISP_V_PULSE1_POSITION_A 0x41f
357 #define DC_DISP_V_PULSE1_POSITION_B 0x420
358 #define DC_DISP_V_PULSE1_POSITION_C 0x421
359 #define DC_DISP_V_PULSE2_CONTROL 0x422
360 #define DC_DISP_V_PULSE2_POSITION_A 0x423
361 #define DC_DISP_V_PULSE3_CONTROL 0x424
362 #define DC_DISP_V_PULSE3_POSITION_A 0x425
363 #define DC_DISP_M0_CONTROL 0x426
364 #define DC_DISP_M1_CONTROL 0x427
365 #define DC_DISP_DI_CONTROL 0x428
366 #define DC_DISP_PP_CONTROL 0x429
367 #define DC_DISP_PP_SELECT_A 0x42a
368 #define DC_DISP_PP_SELECT_B 0x42b
369 #define DC_DISP_PP_SELECT_C 0x42c
370 #define DC_DISP_PP_SELECT_D 0x42d
371
372 #define PULSE_MODE_NORMAL (0 << 3)
373 #define PULSE_MODE_ONE_CLOCK (1 << 3)
374 #define PULSE_POLARITY_HIGH (0 << 4)
375 #define PULSE_POLARITY_LOW (1 << 4)
376 #define PULSE_QUAL_ALWAYS (0 << 6)
377 #define PULSE_QUAL_VACTIVE (2 << 6)
378 #define PULSE_QUAL_VACTIVE1 (3 << 6)
379 #define PULSE_LAST_START_A (0 << 8)
380 #define PULSE_LAST_END_A (1 << 8)
381 #define PULSE_LAST_START_B (2 << 8)
382 #define PULSE_LAST_END_B (3 << 8)
383 #define PULSE_LAST_START_C (4 << 8)
384 #define PULSE_LAST_END_C (5 << 8)
385 #define PULSE_LAST_START_D (6 << 8)
386 #define PULSE_LAST_END_D (7 << 8)
387
388 #define PULSE_START(x) (((x) & 0xfff) << 0)
389 #define PULSE_END(x) (((x) & 0xfff) << 16)
390
391 #define DC_DISP_DISP_CLOCK_CONTROL 0x42e
392 #define PIXEL_CLK_DIVIDER_PCD1 (0 << 8)
393 #define PIXEL_CLK_DIVIDER_PCD1H (1 << 8)
394 #define PIXEL_CLK_DIVIDER_PCD2 (2 << 8)
395 #define PIXEL_CLK_DIVIDER_PCD3 (3 << 8)
396 #define PIXEL_CLK_DIVIDER_PCD4 (4 << 8)
397 #define PIXEL_CLK_DIVIDER_PCD6 (5 << 8)
398 #define PIXEL_CLK_DIVIDER_PCD8 (6 << 8)
399 #define PIXEL_CLK_DIVIDER_PCD9 (7 << 8)
400 #define PIXEL_CLK_DIVIDER_PCD12 (8 << 8)
401 #define PIXEL_CLK_DIVIDER_PCD16 (9 << 8)
402 #define PIXEL_CLK_DIVIDER_PCD18 (10 << 8)
403 #define PIXEL_CLK_DIVIDER_PCD24 (11 << 8)
404 #define PIXEL_CLK_DIVIDER_PCD13 (12 << 8)
405 #define SHIFT_CLK_DIVIDER(x) ((x) & 0xff)
406
407 #define DC_DISP_DISP_INTERFACE_CONTROL 0x42f
408 #define DISP_DATA_FORMAT_DF1P1C (0 << 0)
409 #define DISP_DATA_FORMAT_DF1P2C24B (1 << 0)
410 #define DISP_DATA_FORMAT_DF1P2C18B (2 << 0)
411 #define DISP_DATA_FORMAT_DF1P2C16B (3 << 0)
412 #define DISP_DATA_FORMAT_DF2S (4 << 0)
413 #define DISP_DATA_FORMAT_DF3S (5 << 0)
414 #define DISP_DATA_FORMAT_DFSPI (6 << 0)
415 #define DISP_DATA_FORMAT_DF1P3C24B (7 << 0)
416 #define DISP_DATA_FORMAT_DF1P3C18B (8 << 0)
417 #define DISP_ALIGNMENT_MSB (0 << 8)
418 #define DISP_ALIGNMENT_LSB (1 << 8)
419 #define DISP_ORDER_RED_BLUE (0 << 9)
420 #define DISP_ORDER_BLUE_RED (1 << 9)
421
422 #define DC_DISP_DISP_COLOR_CONTROL 0x430
423 #define BASE_COLOR_SIZE666 ( 0 << 0)
424 #define BASE_COLOR_SIZE111 ( 1 << 0)
425 #define BASE_COLOR_SIZE222 ( 2 << 0)
426 #define BASE_COLOR_SIZE333 ( 3 << 0)
427 #define BASE_COLOR_SIZE444 ( 4 << 0)
428 #define BASE_COLOR_SIZE555 ( 5 << 0)
429 #define BASE_COLOR_SIZE565 ( 6 << 0)
430 #define BASE_COLOR_SIZE332 ( 7 << 0)
431 #define BASE_COLOR_SIZE888 ( 8 << 0)
432 #define BASE_COLOR_SIZE101010 (10 << 0)
433 #define BASE_COLOR_SIZE121212 (12 << 0)
434 #define DITHER_CONTROL_MASK (3 << 8)
435 #define DITHER_CONTROL_DISABLE (0 << 8)
436 #define DITHER_CONTROL_ORDERED (2 << 8)
437 #define DITHER_CONTROL_ERRDIFF (3 << 8)
438 #define BASE_COLOR_SIZE_MASK (0xf << 0)
439 #define BASE_COLOR_SIZE_666 ( 0 << 0)
440 #define BASE_COLOR_SIZE_111 ( 1 << 0)
441 #define BASE_COLOR_SIZE_222 ( 2 << 0)
442 #define BASE_COLOR_SIZE_333 ( 3 << 0)
443 #define BASE_COLOR_SIZE_444 ( 4 << 0)
444 #define BASE_COLOR_SIZE_555 ( 5 << 0)
445 #define BASE_COLOR_SIZE_565 ( 6 << 0)
446 #define BASE_COLOR_SIZE_332 ( 7 << 0)
447 #define BASE_COLOR_SIZE_888 ( 8 << 0)
448 #define BASE_COLOR_SIZE_101010 ( 10 << 0)
449 #define BASE_COLOR_SIZE_121212 ( 12 << 0)
450
451 #define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
452 #define SC1_H_QUALIFIER_NONE (1 << 16)
453 #define SC0_H_QUALIFIER_NONE (1 << 0)
454
455 #define DC_DISP_DATA_ENABLE_OPTIONS 0x432
456 #define DE_SELECT_ACTIVE_BLANK (0 << 0)
457 #define DE_SELECT_ACTIVE (1 << 0)
458 #define DE_SELECT_ACTIVE_IS (2 << 0)
459 #define DE_CONTROL_ONECLK (0 << 2)
460 #define DE_CONTROL_NORMAL (1 << 2)
461 #define DE_CONTROL_EARLY_EXT (2 << 2)
462 #define DE_CONTROL_EARLY (3 << 2)
463 #define DE_CONTROL_ACTIVE_BLANK (4 << 2)
464
465 #define DC_DISP_SERIAL_INTERFACE_OPTIONS 0x433
466 #define DC_DISP_LCD_SPI_OPTIONS 0x434
467 #define DC_DISP_BORDER_COLOR 0x435
468 #define DC_DISP_COLOR_KEY0_LOWER 0x436
469 #define DC_DISP_COLOR_KEY0_UPPER 0x437
470 #define DC_DISP_COLOR_KEY1_LOWER 0x438
471 #define DC_DISP_COLOR_KEY1_UPPER 0x439
472
473 #define DC_DISP_CURSOR_FOREGROUND 0x43c
474 #define DC_DISP_CURSOR_BACKGROUND 0x43d
475
476 #define DC_DISP_CURSOR_START_ADDR 0x43e
477 #define CURSOR_CLIP_DISPLAY (0 << 28)
478 #define CURSOR_CLIP_WIN_A (1 << 28)
479 #define CURSOR_CLIP_WIN_B (2 << 28)
480 #define CURSOR_CLIP_WIN_C (3 << 28)
481 #define CURSOR_SIZE_32x32 (0 << 24)
482 #define CURSOR_SIZE_64x64 (1 << 24)
483 #define CURSOR_SIZE_128x128 (2 << 24)
484 #define CURSOR_SIZE_256x256 (3 << 24)
485 #define DC_DISP_CURSOR_START_ADDR_NS 0x43f
486
487 #define DC_DISP_CURSOR_POSITION 0x440
488 #define DC_DISP_CURSOR_POSITION_NS 0x441
489
490 #define DC_DISP_INIT_SEQ_CONTROL 0x442
491 #define DC_DISP_SPI_INIT_SEQ_DATA_A 0x443
492 #define DC_DISP_SPI_INIT_SEQ_DATA_B 0x444
493 #define DC_DISP_SPI_INIT_SEQ_DATA_C 0x445
494 #define DC_DISP_SPI_INIT_SEQ_DATA_D 0x446
495
496 #define DC_DISP_DC_MCCIF_FIFOCTRL 0x480
497 #define DC_DISP_MCCIF_DISPLAY0A_HYST 0x481
498 #define DC_DISP_MCCIF_DISPLAY0B_HYST 0x482
499 #define DC_DISP_MCCIF_DISPLAY1A_HYST 0x483
500 #define DC_DISP_MCCIF_DISPLAY1B_HYST 0x484
501
502 #define DC_DISP_DAC_CRT_CTRL 0x4c0
503 #define DC_DISP_DISP_MISC_CONTROL 0x4c1
504 #define DC_DISP_SD_CONTROL 0x4c2
505 #define DC_DISP_SD_CSC_COEFF 0x4c3
506 #define DC_DISP_SD_LUT(x) (0x4c4 + (x))
507 #define DC_DISP_SD_FLICKER_CONTROL 0x4cd
508 #define DC_DISP_DC_PIXEL_COUNT 0x4ce
509 #define DC_DISP_SD_HISTOGRAM(x) (0x4cf + (x))
510 #define DC_DISP_SD_BL_PARAMETERS 0x4d7
511 #define DC_DISP_SD_BL_TF(x) (0x4d8 + (x))
512 #define DC_DISP_SD_BL_CONTROL 0x4dc
513 #define DC_DISP_SD_HW_K_VALUES 0x4dd
514 #define DC_DISP_SD_MAN_K_VALUES 0x4de
515
516 #define DC_DISP_BLEND_BACKGROUND_COLOR 0x4e4
517 #define BACKGROUND_COLOR_ALPHA(x) (((x) & 0xff) << 24)
518 #define BACKGROUND_COLOR_BLUE(x) (((x) & 0xff) << 16)
519 #define BACKGROUND_COLOR_GREEN(x) (((x) & 0xff) << 8)
520 #define BACKGROUND_COLOR_RED(x) (((x) & 0xff) << 0)
521
522 #define DC_DISP_INTERLACE_CONTROL 0x4e5
523 #define INTERLACE_STATUS (1 << 2)
524 #define INTERLACE_START (1 << 1)
525 #define INTERLACE_ENABLE (1 << 0)
526
527 #define DC_DISP_CURSOR_START_ADDR_HI 0x4ec
528 #define DC_DISP_BLEND_CURSOR_CONTROL 0x4f1
529 #define CURSOR_COMPOSITION_MODE_BLEND (0 << 25)
530 #define CURSOR_COMPOSITION_MODE_XOR (1 << 25)
531 #define CURSOR_MODE_LEGACY (0 << 24)
532 #define CURSOR_MODE_NORMAL (1 << 24)
533 #define CURSOR_DST_BLEND_ZERO (0 << 16)
534 #define CURSOR_DST_BLEND_K1 (1 << 16)
535 #define CURSOR_DST_BLEND_NEG_K1_TIMES_SRC (2 << 16)
536 #define CURSOR_DST_BLEND_MASK (3 << 16)
537 #define CURSOR_SRC_BLEND_K1 (0 << 8)
538 #define CURSOR_SRC_BLEND_K1_TIMES_SRC (1 << 8)
539 #define CURSOR_SRC_BLEND_MASK (3 << 8)
540 #define CURSOR_ALPHA 0xff
541
542 #define DC_WIN_CORE_ACT_CONTROL 0x50e
543 #define VCOUNTER (0 << 0)
544 #define HCOUNTER (1 << 0)
545
546 #define DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA 0x543
547 #define LATENCY_CTL_MODE_ENABLE (1 << 2)
548
549 #define DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB 0x544
550 #define WATERMARK_MASK 0x1fffffff
551
552 #define DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER 0x560
553 #define PIPE_METER_INT(x) (((x) & 0xff) << 8)
554 #define PIPE_METER_FRAC(x) (((x) & 0xff) << 0)
555
556 #define DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG 0x561
557 #define MEMPOOL_ENTRIES(x) (((x) & 0xffff) << 0)
558
559 #define DC_WIN_CORE_IHUB_WGRP_FETCH_METER 0x562
560 #define SLOTS(x) (((x) & 0xff) << 0)
561
562 #define DC_WIN_CORE_IHUB_LINEBUF_CONFIG 0x563
563 #define MODE_TWO_LINES (0 << 14)
564 #define MODE_FOUR_LINES (1 << 14)
565
566 #define DC_WIN_CORE_IHUB_THREAD_GROUP 0x568
567 #define THREAD_NUM_MASK (0x1f << 1)
568 #define THREAD_NUM(x) (((x) & 0x1f) << 1)
569 #define THREAD_GROUP_ENABLE (1 << 0)
570
571 #define DC_WIN_H_FILTER_P(p) (0x601 + (p))
572 #define DC_WIN_V_FILTER_P(p) (0x619 + (p))
573
574 #define DC_WIN_CSC_YOF 0x611
575 #define DC_WIN_CSC_KYRGB 0x612
576 #define DC_WIN_CSC_KUR 0x613
577 #define DC_WIN_CSC_KVR 0x614
578 #define DC_WIN_CSC_KUG 0x615
579 #define DC_WIN_CSC_KVG 0x616
580 #define DC_WIN_CSC_KUB 0x617
581 #define DC_WIN_CSC_KVB 0x618
582
583 #define DC_WIN_WIN_OPTIONS 0x700
584 #define H_DIRECTION (1 << 0)
585 #define V_DIRECTION (1 << 2)
586 #define COLOR_EXPAND (1 << 6)
587 #define H_FILTER (1 << 8)
588 #define V_FILTER (1 << 10)
589 #define CSC_ENABLE (1 << 18)
590 #define WIN_ENABLE (1 << 30)
591
592 #define DC_WIN_BYTE_SWAP 0x701
593 #define BYTE_SWAP_NOSWAP (0 << 0)
594 #define BYTE_SWAP_SWAP2 (1 << 0)
595 #define BYTE_SWAP_SWAP4 (2 << 0)
596 #define BYTE_SWAP_SWAP4HW (3 << 0)
597
598 #define DC_WIN_BUFFER_CONTROL 0x702
599 #define BUFFER_CONTROL_HOST (0 << 0)
600 #define BUFFER_CONTROL_VI (1 << 0)
601 #define BUFFER_CONTROL_EPP (2 << 0)
602 #define BUFFER_CONTROL_MPEGE (3 << 0)
603 #define BUFFER_CONTROL_SB2D (4 << 0)
604
605 #define DC_WIN_COLOR_DEPTH 0x703
606 #define WIN_COLOR_DEPTH_P1 0
607 #define WIN_COLOR_DEPTH_P2 1
608 #define WIN_COLOR_DEPTH_P4 2
609 #define WIN_COLOR_DEPTH_P8 3
610 #define WIN_COLOR_DEPTH_B4G4R4A4 4
611 #define WIN_COLOR_DEPTH_B5G5R5A1 5
612 #define WIN_COLOR_DEPTH_B5G6R5 6
613 #define WIN_COLOR_DEPTH_A1B5G5R5 7
614 #define WIN_COLOR_DEPTH_B8G8R8A8 12
615 #define WIN_COLOR_DEPTH_R8G8B8A8 13
616 #define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 14
617 #define WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 15
618 #define WIN_COLOR_DEPTH_YCbCr422 16
619 #define WIN_COLOR_DEPTH_YUV422 17
620 #define WIN_COLOR_DEPTH_YCbCr420P 18
621 #define WIN_COLOR_DEPTH_YUV420P 19
622 #define WIN_COLOR_DEPTH_YCbCr422P 20
623 #define WIN_COLOR_DEPTH_YUV422P 21
624 #define WIN_COLOR_DEPTH_YCbCr422R 22
625 #define WIN_COLOR_DEPTH_YUV422R 23
626 #define WIN_COLOR_DEPTH_YCbCr422RA 24
627 #define WIN_COLOR_DEPTH_YUV422RA 25
628 #define WIN_COLOR_DEPTH_R4G4B4A4 27
629 #define WIN_COLOR_DEPTH_R5G5B5A 28
630 #define WIN_COLOR_DEPTH_AR5G5B5 29
631 #define WIN_COLOR_DEPTH_B5G5R5X1 30
632 #define WIN_COLOR_DEPTH_X1B5G5R5 31
633 #define WIN_COLOR_DEPTH_R5G5B5X1 32
634 #define WIN_COLOR_DEPTH_X1R5G5B5 33
635 #define WIN_COLOR_DEPTH_R5G6B5 34
636 #define WIN_COLOR_DEPTH_A8R8G8B8 35
637 #define WIN_COLOR_DEPTH_A8B8G8R8 36
638 #define WIN_COLOR_DEPTH_B8G8R8X8 37
639 #define WIN_COLOR_DEPTH_R8G8B8X8 38
640 #define WIN_COLOR_DEPTH_YCbCr444P 41
641 #define WIN_COLOR_DEPTH_YCrCb420SP 42
642 #define WIN_COLOR_DEPTH_YCbCr420SP 43
643 #define WIN_COLOR_DEPTH_YCrCb422SP 44
644 #define WIN_COLOR_DEPTH_YCbCr422SP 45
645 #define WIN_COLOR_DEPTH_YCrCb444SP 48
646 #define WIN_COLOR_DEPTH_YCbCr444SP 49
647 #define WIN_COLOR_DEPTH_X8B8G8R8 65
648 #define WIN_COLOR_DEPTH_X8R8G8B8 66
649
650 #define DC_WIN_POSITION 0x704
651 #define H_POSITION(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */
652 #define V_POSITION(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */
653
654 #define DC_WIN_SIZE 0x705
655 #define H_SIZE(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */
656 #define V_SIZE(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */
657
658 #define DC_WIN_PRESCALED_SIZE 0x706
659 #define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0)
660 #define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */
661
662 #define DC_WIN_H_INITIAL_DDA 0x707
663 #define DC_WIN_V_INITIAL_DDA 0x708
664 #define DC_WIN_DDA_INC 0x709
665 #define H_DDA_INC(x) (((x) & 0xffff) << 0)
666 #define V_DDA_INC(x) (((x) & 0xffff) << 16)
667
668 #define DC_WIN_LINE_STRIDE 0x70a
669 #define DC_WIN_BUF_STRIDE 0x70b
670 #define DC_WIN_UV_BUF_STRIDE 0x70c
671 #define DC_WIN_BUFFER_ADDR_MODE 0x70d
672 #define DC_WIN_BUFFER_ADDR_MODE_LINEAR (0 << 0)
673 #define DC_WIN_BUFFER_ADDR_MODE_TILE (1 << 0)
674 #define DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV (0 << 16)
675 #define DC_WIN_BUFFER_ADDR_MODE_TILE_UV (1 << 16)
676
677 #define DC_WIN_DV_CONTROL 0x70e
678
679 #define DC_WIN_BLEND_NOKEY 0x70f
680 #define BLEND_WEIGHT1(x) (((x) & 0xff) << 16)
681 #define BLEND_WEIGHT0(x) (((x) & 0xff) << 8)
682
683 #define DC_WIN_BLEND_1WIN 0x710
684 #define BLEND_CONTROL_FIX (0 << 2)
685 #define BLEND_CONTROL_ALPHA (1 << 2)
686 #define BLEND_COLOR_KEY_NONE (0 << 0)
687 #define BLEND_COLOR_KEY_0 (1 << 0)
688 #define BLEND_COLOR_KEY_1 (2 << 0)
689 #define BLEND_COLOR_KEY_BOTH (3 << 0)
690
691 #define DC_WIN_BLEND_2WIN_X 0x711
692 #define BLEND_CONTROL_DEPENDENT (2 << 2)
693
694 #define DC_WIN_BLEND_2WIN_Y 0x712
695 #define DC_WIN_BLEND_3WIN_XY 0x713
696
697 #define DC_WIN_HP_FETCH_CONTROL 0x714
698
699 #define DC_WINBUF_START_ADDR 0x800
700 #define DC_WINBUF_START_ADDR_NS 0x801
701 #define DC_WINBUF_START_ADDR_U 0x802
702 #define DC_WINBUF_START_ADDR_U_NS 0x803
703 #define DC_WINBUF_START_ADDR_V 0x804
704 #define DC_WINBUF_START_ADDR_V_NS 0x805
705
706 #define DC_WINBUF_ADDR_H_OFFSET 0x806
707 #define DC_WINBUF_ADDR_H_OFFSET_NS 0x807
708 #define DC_WINBUF_ADDR_V_OFFSET 0x808
709 #define DC_WINBUF_ADDR_V_OFFSET_NS 0x809
710
711 #define DC_WINBUF_UFLOW_STATUS 0x80a
712 #define DC_WINBUF_SURFACE_KIND 0x80b
713 #define DC_WINBUF_SURFACE_KIND_PITCH (0 << 0)
714 #define DC_WINBUF_SURFACE_KIND_TILED (1 << 0)
715 #define DC_WINBUF_SURFACE_KIND_BLOCK (2 << 0)
716 #define DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(x) (((x) & 0x7) << 4)
717
718 #define DC_WINBUF_START_ADDR_HI 0x80d
719
720 #define DC_WINBUF_START_ADDR_HI_U 0x80f
721 #define DC_WINBUF_START_ADDR_HI_V 0x811
722
723 #define DC_WINBUF_CDE_CONTROL 0x82f
724 #define ENABLE_SURFACE (1 << 0)
725
726 #define DC_WINBUF_AD_UFLOW_STATUS 0xbca
727 #define DC_WINBUF_BD_UFLOW_STATUS 0xdca
728 #define DC_WINBUF_CD_UFLOW_STATUS 0xfca
729
730 /* Tegra186 and later */
731 #define DC_DISP_CORE_SOR_SET_CONTROL(x) (0x403 + (x))
732 #define PROTOCOL_MASK (0xf << 8)
733 #define PROTOCOL_SINGLE_TMDS_A (0x1 << 8)
734
735 #define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR 0x442
736 #define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR 0x446
737
738 #define DC_WINC_PRECOMP_WGRP_PIPE_CAPA 0x500
739 #define DC_WINC_PRECOMP_WGRP_PIPE_CAPB 0x501
740 #define DC_WINC_PRECOMP_WGRP_PIPE_CAPC 0x502
741 #define MAX_PIXELS_5TAP444(x) ((x) & 0xffff)
742 #define DC_WINC_PRECOMP_WGRP_PIPE_CAPD 0x503
743 #define DC_WINC_PRECOMP_WGRP_PIPE_CAPE 0x504
744 #define MAX_PIXELS_2TAP444(x) ((x) & 0xffff)
745 #define DC_WINC_PRECOMP_WGRP_PIPE_CAPF 0x505
746
747 #define DC_WIN_CORE_WINDOWGROUP_SET_CONTROL 0x702
748 #define OWNER_MASK (0xf << 0)
749 #define OWNER(x) (((x) & 0xf) << 0)
750
751 #define DC_WIN_CROPPED_SIZE 0x706
752
753 #define DC_WIN_SET_INPUT_SCALER_H_START_PHASE 0x707
754 #define DC_WIN_SET_INPUT_SCALER_V_START_PHASE 0x708
755
756 #define DC_WIN_PLANAR_STORAGE 0x709
757 #define PITCH(x) (((x) >> 6) & 0x1fff)
758
759 #define DC_WIN_PLANAR_STORAGE_UV 0x70a
760 #define PITCH_U(x) ((((x) >> 6) & 0x1fff) << 0)
761 #define PITCH_V(x) ((((x) >> 6) & 0x1fff) << 16)
762
763 #define DC_WIN_SET_INPUT_SCALER_HPHASE_INCR 0x70b
764 #define DC_WIN_SET_INPUT_SCALER_VPHASE_INCR 0x70c
765
766 #define DC_WIN_SET_PARAMS 0x70d
767 #define CLAMP_BEFORE_BLEND (1 << 15)
768 #define DEGAMMA_NONE (0 << 13)
769 #define DEGAMMA_SRGB (1 << 13)
770 #define DEGAMMA_YUV8_10 (2 << 13)
771 #define DEGAMMA_YUV12 (3 << 13)
772 #define INPUT_RANGE_BYPASS (0 << 10)
773 #define INPUT_RANGE_LIMITED (1 << 10)
774 #define INPUT_RANGE_FULL (2 << 10)
775 #define COLOR_SPACE_RGB (0 << 8)
776 #define COLOR_SPACE_YUV_601 (1 << 8)
777 #define COLOR_SPACE_YUV_709 (2 << 8)
778 #define COLOR_SPACE_YUV_2020 (3 << 8)
779
780 #define DC_WIN_WINDOWGROUP_SET_CONTROL_INPUT_SCALER 0x70e
781 #define HORIZONTAL_TAPS_2 (1 << 3)
782 #define HORIZONTAL_TAPS_5 (4 << 3)
783 #define VERTICAL_TAPS_2 (1 << 0)
784 #define VERTICAL_TAPS_5 (4 << 0)
785
786 #define DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_COEFF 0x70f
787 #define COEFF_INDEX(x) (((x) & 0xff) << 15)
788 #define COEFF_DATA(x) (((x) & 0x3ff) << 0)
789
790 #define DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE 0x711
791 #define INPUT_SCALER_USE422 (1 << 2)
792 #define INPUT_SCALER_VBYPASS (1 << 1)
793 #define INPUT_SCALER_HBYPASS (1 << 0)
794
795 #define DC_WIN_BLEND_LAYER_CONTROL 0x716
796 #define COLOR_KEY_NONE (0 << 25)
797 #define COLOR_KEY_SRC (1 << 25)
798 #define COLOR_KEY_DST (2 << 25)
799 #define BLEND_BYPASS (1 << 24)
800 #define K2(x) (((x) & 0xff) << 16)
801 #define K1(x) (((x) & 0xff) << 8)
802 #define WINDOW_LAYER_DEPTH(x) (((x) & 0xff) << 0)
803
804 #define DC_WIN_BLEND_MATCH_SELECT 0x717
805 #define BLEND_FACTOR_DST_ALPHA_ZERO (0 << 12)
806 #define BLEND_FACTOR_DST_ALPHA_ONE (1 << 12)
807 #define BLEND_FACTOR_DST_ALPHA_NEG_K1_TIMES_SRC (2 << 12)
808 #define BLEND_FACTOR_DST_ALPHA_K2 (3 << 12)
809 #define BLEND_FACTOR_SRC_ALPHA_ZERO (0 << 8)
810 #define BLEND_FACTOR_SRC_ALPHA_K1 (1 << 8)
811 #define BLEND_FACTOR_SRC_ALPHA_K2 (2 << 8)
812 #define BLEND_FACTOR_SRC_ALPHA_NEG_K1_TIMES_DST (3 << 8)
813 #define BLEND_FACTOR_DST_COLOR_ZERO (0 << 4)
814 #define BLEND_FACTOR_DST_COLOR_ONE (1 << 4)
815 #define BLEND_FACTOR_DST_COLOR_K1 (2 << 4)
816 #define BLEND_FACTOR_DST_COLOR_K2 (3 << 4)
817 #define BLEND_FACTOR_DST_COLOR_K1_TIMES_DST (4 << 4)
818 #define BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_DST (5 << 4)
819 #define BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC (6 << 4)
820 #define BLEND_FACTOR_DST_COLOR_NEG_K1 (7 << 4)
821 #define BLEND_FACTOR_SRC_COLOR_ZERO (0 << 0)
822 #define BLEND_FACTOR_SRC_COLOR_ONE (1 << 0)
823 #define BLEND_FACTOR_SRC_COLOR_K1 (2 << 0)
824 #define BLEND_FACTOR_SRC_COLOR_K1_TIMES_DST (3 << 0)
825 #define BLEND_FACTOR_SRC_COLOR_NEG_K1_TIMES_DST (4 << 0)
826 #define BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC (5 << 0)
827
828 #define DC_WIN_BLEND_NOMATCH_SELECT 0x718
829
830 #define DC_WIN_PRECOMP_WGRP_PARAMS 0x724
831 #define SWAP_UV (1 << 0)
832
833 #define DC_WIN_WINDOW_SET_CONTROL 0x730
834 #define CONTROL_CSC_ENABLE (1 << 5)
835
836 #define DC_WINBUF_CROPPED_POINT 0x806
837 #define OFFSET_Y(x) (((x) & 0xffff) << 16)
838 #define OFFSET_X(x) (((x) & 0xffff) << 0)
839
840 #endif /* TEGRA_DC_H */
841