1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* include/video/samsung_fimd.h
3  *
4  * Copyright 2008 Openmoko, Inc.
5  * Copyright 2008 Simtec Electronics
6  *      http://armlinux.simtec.co.uk/
7  *      Ben Dooks <ben@simtec.co.uk>
8  *
9  * S3C Platform - new-style fimd and framebuffer register definitions
10  *
11  * This is the register set for the fimd and new style framebuffer interface
12  * found from the S3C2443 onwards into the S3C2416, S3C2450, the
13  * S3C64XX series such as the S3C6400 and S3C6410, and Exynos series.
14 */
15 
16 /* VIDCON0 */
17 
18 #define VIDCON0					0x00
19 #define VIDCON0_DSI_EN				(1 << 30)
20 #define VIDCON0_INTERLACE			(1 << 29)
21 #define VIDCON0_VIDOUT_MASK			(0x7 << 26)
22 #define VIDCON0_VIDOUT_SHIFT			26
23 #define VIDCON0_VIDOUT_RGB			(0x0 << 26)
24 #define VIDCON0_VIDOUT_TV			(0x1 << 26)
25 #define VIDCON0_VIDOUT_I80_LDI0			(0x2 << 26)
26 #define VIDCON0_VIDOUT_I80_LDI1			(0x3 << 26)
27 #define VIDCON0_VIDOUT_WB_RGB			(0x4 << 26)
28 #define VIDCON0_VIDOUT_WB_I80_LDI0		(0x6 << 26)
29 #define VIDCON0_VIDOUT_WB_I80_LDI1		(0x7 << 26)
30 
31 #define VIDCON0_L1_DATA_MASK			(0x7 << 23)
32 #define VIDCON0_L1_DATA_SHIFT			23
33 #define VIDCON0_L1_DATA_16BPP			(0x0 << 23)
34 #define VIDCON0_L1_DATA_18BPP16			(0x1 << 23)
35 #define VIDCON0_L1_DATA_18BPP9			(0x2 << 23)
36 #define VIDCON0_L1_DATA_24BPP			(0x3 << 23)
37 #define VIDCON0_L1_DATA_18BPP			(0x4 << 23)
38 #define VIDCON0_L1_DATA_16BPP8			(0x5 << 23)
39 
40 #define VIDCON0_L0_DATA_MASK			(0x7 << 20)
41 #define VIDCON0_L0_DATA_SHIFT			20
42 #define VIDCON0_L0_DATA_16BPP			(0x0 << 20)
43 #define VIDCON0_L0_DATA_18BPP16			(0x1 << 20)
44 #define VIDCON0_L0_DATA_18BPP9			(0x2 << 20)
45 #define VIDCON0_L0_DATA_24BPP			(0x3 << 20)
46 #define VIDCON0_L0_DATA_18BPP			(0x4 << 20)
47 #define VIDCON0_L0_DATA_16BPP8			(0x5 << 20)
48 
49 #define VIDCON0_PNRMODE_MASK			(0x3 << 17)
50 #define VIDCON0_PNRMODE_SHIFT			17
51 #define VIDCON0_PNRMODE_RGB			(0x0 << 17)
52 #define VIDCON0_PNRMODE_BGR			(0x1 << 17)
53 #define VIDCON0_PNRMODE_SERIAL_RGB		(0x2 << 17)
54 #define VIDCON0_PNRMODE_SERIAL_BGR		(0x3 << 17)
55 
56 #define VIDCON0_CLKVALUP			(1 << 16)
57 #define VIDCON0_CLKVAL_F_MASK			(0xff << 6)
58 #define VIDCON0_CLKVAL_F_SHIFT			6
59 #define VIDCON0_CLKVAL_F_LIMIT			0xff
60 #define VIDCON0_CLKVAL_F(_x)			((_x) << 6)
61 #define VIDCON0_VLCKFREE			(1 << 5)
62 #define VIDCON0_CLKDIR				(1 << 4)
63 
64 #define VIDCON0_CLKSEL_MASK			(0x3 << 2)
65 #define VIDCON0_CLKSEL_SHIFT			2
66 #define VIDCON0_CLKSEL_HCLK			(0x0 << 2)
67 #define VIDCON0_CLKSEL_LCD			(0x1 << 2)
68 #define VIDCON0_CLKSEL_27M			(0x3 << 2)
69 
70 #define VIDCON0_ENVID				(1 << 1)
71 #define VIDCON0_ENVID_F				(1 << 0)
72 
73 #define VIDCON1					0x04
74 #define VIDCON1_LINECNT_MASK			(0x7ff << 16)
75 #define VIDCON1_LINECNT_SHIFT			16
76 #define VIDCON1_LINECNT_GET(_v)			(((_v) >> 16) & 0x7ff)
77 #define VIDCON1_FSTATUS_EVEN			(1 << 15)
78 #define VIDCON1_VSTATUS_MASK			(0x3 << 13)
79 #define VIDCON1_VSTATUS_SHIFT			13
80 #define VIDCON1_VSTATUS_VSYNC			(0x0 << 13)
81 #define VIDCON1_VSTATUS_BACKPORCH		(0x1 << 13)
82 #define VIDCON1_VSTATUS_ACTIVE			(0x2 << 13)
83 #define VIDCON1_VSTATUS_FRONTPORCH		(0x3 << 13)
84 #define VIDCON1_VCLK_MASK			(0x3 << 9)
85 #define VIDCON1_VCLK_HOLD			(0x0 << 9)
86 #define VIDCON1_VCLK_RUN			(0x1 << 9)
87 
88 #define VIDCON1_INV_VCLK			(1 << 7)
89 #define VIDCON1_INV_HSYNC			(1 << 6)
90 #define VIDCON1_INV_VSYNC			(1 << 5)
91 #define VIDCON1_INV_VDEN			(1 << 4)
92 
93 /* VIDCON2 */
94 
95 #define VIDCON2					0x08
96 #define VIDCON2_EN601				(1 << 23)
97 #define VIDCON2_TVFMTSEL_SW			(1 << 14)
98 
99 #define VIDCON2_TVFMTSEL1_MASK			(0x3 << 12)
100 #define VIDCON2_TVFMTSEL1_SHIFT			12
101 #define VIDCON2_TVFMTSEL1_RGB			(0x0 << 12)
102 #define VIDCON2_TVFMTSEL1_YUV422		(0x1 << 12)
103 #define VIDCON2_TVFMTSEL1_YUV444		(0x2 << 12)
104 
105 #define VIDCON2_ORGYCbCr			(1 << 8)
106 #define VIDCON2_YUVORDCrCb			(1 << 7)
107 
108 /* PRTCON (S3C6410)
109  * Might not be present in the S3C6410 documentation,
110  * but tests prove it's there almost for sure; shouldn't hurt in any case.
111  */
112 #define PRTCON					0x0c
113 #define PRTCON_PROTECT				(1 << 11)
114 
115 /* VIDTCON0 */
116 
117 #define VIDTCON0				0x10
118 #define VIDTCON0_VBPDE_MASK			(0xff << 24)
119 #define VIDTCON0_VBPDE_SHIFT			24
120 #define VIDTCON0_VBPDE_LIMIT			0xff
121 #define VIDTCON0_VBPDE(_x)			((_x) << 24)
122 
123 #define VIDTCON0_VBPD_MASK			(0xff << 16)
124 #define VIDTCON0_VBPD_SHIFT			16
125 #define VIDTCON0_VBPD_LIMIT			0xff
126 #define VIDTCON0_VBPD(_x)			((_x) << 16)
127 
128 #define VIDTCON0_VFPD_MASK			(0xff << 8)
129 #define VIDTCON0_VFPD_SHIFT			8
130 #define VIDTCON0_VFPD_LIMIT			0xff
131 #define VIDTCON0_VFPD(_x)			((_x) << 8)
132 
133 #define VIDTCON0_VSPW_MASK			(0xff << 0)
134 #define VIDTCON0_VSPW_SHIFT			0
135 #define VIDTCON0_VSPW_LIMIT			0xff
136 #define VIDTCON0_VSPW(_x)			((_x) << 0)
137 
138 /* VIDTCON1 */
139 
140 #define VIDTCON1				0x14
141 #define VIDTCON1_VFPDE_MASK			(0xff << 24)
142 #define VIDTCON1_VFPDE_SHIFT			24
143 #define VIDTCON1_VFPDE_LIMIT			0xff
144 #define VIDTCON1_VFPDE(_x)			((_x) << 24)
145 
146 #define VIDTCON1_HBPD_MASK			(0xff << 16)
147 #define VIDTCON1_HBPD_SHIFT			16
148 #define VIDTCON1_HBPD_LIMIT			0xff
149 #define VIDTCON1_HBPD(_x)			((_x) << 16)
150 
151 #define VIDTCON1_HFPD_MASK			(0xff << 8)
152 #define VIDTCON1_HFPD_SHIFT			8
153 #define VIDTCON1_HFPD_LIMIT			0xff
154 #define VIDTCON1_HFPD(_x)			((_x) << 8)
155 
156 #define VIDTCON1_HSPW_MASK			(0xff << 0)
157 #define VIDTCON1_HSPW_SHIFT			0
158 #define VIDTCON1_HSPW_LIMIT			0xff
159 #define VIDTCON1_HSPW(_x)			((_x) << 0)
160 
161 #define VIDTCON2				0x18
162 #define VIDTCON2_LINEVAL_E(_x)			((((_x) & 0x800) >> 11) << 23)
163 #define VIDTCON2_LINEVAL_MASK			(0x7ff << 11)
164 #define VIDTCON2_LINEVAL_SHIFT			11
165 #define VIDTCON2_LINEVAL_LIMIT			0x7ff
166 #define VIDTCON2_LINEVAL(_x)			(((_x) & 0x7ff) << 11)
167 
168 #define VIDTCON2_HOZVAL_E(_x)			((((_x) & 0x800) >> 11) << 22)
169 #define VIDTCON2_HOZVAL_MASK			(0x7ff << 0)
170 #define VIDTCON2_HOZVAL_SHIFT			0
171 #define VIDTCON2_HOZVAL_LIMIT			0x7ff
172 #define VIDTCON2_HOZVAL(_x)			(((_x) & 0x7ff) << 0)
173 
174 /* WINCONx */
175 
176 #define WINCON(_win)				(0x20 + ((_win) * 4))
177 #define WINCONx_CSCCON_EQ601			(0x0 << 28)
178 #define WINCONx_CSCCON_EQ709			(0x1 << 28)
179 #define WINCONx_CSCWIDTH_MASK			(0x3 << 26)
180 #define WINCONx_CSCWIDTH_SHIFT			26
181 #define WINCONx_CSCWIDTH_WIDE			(0x0 << 26)
182 #define WINCONx_CSCWIDTH_NARROW			(0x3 << 26)
183 #define WINCONx_ENLOCAL				(1 << 22)
184 #define WINCONx_BUFSTATUS			(1 << 21)
185 #define WINCONx_BUFSEL				(1 << 20)
186 #define WINCONx_BUFAUTOEN			(1 << 19)
187 #define WINCONx_BITSWP				(1 << 18)
188 #define WINCONx_BYTSWP				(1 << 17)
189 #define WINCONx_HAWSWP				(1 << 16)
190 #define WINCONx_WSWP				(1 << 15)
191 #define WINCONx_YCbCr				(1 << 13)
192 #define WINCONx_BURSTLEN_MASK			(0x3 << 9)
193 #define WINCONx_BURSTLEN_SHIFT			9
194 #define WINCONx_BURSTLEN_16WORD			(0x0 << 9)
195 #define WINCONx_BURSTLEN_8WORD			(0x1 << 9)
196 #define WINCONx_BURSTLEN_4WORD			(0x2 << 9)
197 #define WINCONx_ENWIN				(1 << 0)
198 #define WINCONx_BLEND_MODE_MASK			(0xc2)
199 
200 #define WINCON0_BPPMODE_MASK			(0xf << 2)
201 #define WINCON0_BPPMODE_SHIFT			2
202 #define WINCON0_BPPMODE_1BPP			(0x0 << 2)
203 #define WINCON0_BPPMODE_2BPP			(0x1 << 2)
204 #define WINCON0_BPPMODE_4BPP			(0x2 << 2)
205 #define WINCON0_BPPMODE_8BPP_PALETTE		(0x3 << 2)
206 #define WINCON0_BPPMODE_16BPP_565		(0x5 << 2)
207 #define WINCON0_BPPMODE_16BPP_1555		(0x7 << 2)
208 #define WINCON0_BPPMODE_18BPP_666		(0x8 << 2)
209 #define WINCON0_BPPMODE_24BPP_888		(0xb << 2)
210 
211 #define WINCON1_LOCALSEL_CAMIF			(1 << 23)
212 #define WINCON1_ALPHA_MUL			(1 << 7)
213 #define WINCON1_BLD_PIX				(1 << 6)
214 #define WINCON1_BPPMODE_MASK			(0xf << 2)
215 #define WINCON1_BPPMODE_SHIFT			2
216 #define WINCON1_BPPMODE_1BPP			(0x0 << 2)
217 #define WINCON1_BPPMODE_2BPP			(0x1 << 2)
218 #define WINCON1_BPPMODE_4BPP			(0x2 << 2)
219 #define WINCON1_BPPMODE_8BPP_PALETTE		(0x3 << 2)
220 #define WINCON1_BPPMODE_8BPP_1232		(0x4 << 2)
221 #define WINCON1_BPPMODE_16BPP_565		(0x5 << 2)
222 #define WINCON1_BPPMODE_16BPP_A1555		(0x6 << 2)
223 #define WINCON1_BPPMODE_16BPP_I1555		(0x7 << 2)
224 #define WINCON1_BPPMODE_18BPP_666		(0x8 << 2)
225 #define WINCON1_BPPMODE_18BPP_A1665		(0x9 << 2)
226 #define WINCON1_BPPMODE_19BPP_A1666		(0xa << 2)
227 #define WINCON1_BPPMODE_24BPP_888		(0xb << 2)
228 #define WINCON1_BPPMODE_24BPP_A1887		(0xc << 2)
229 #define WINCON1_BPPMODE_25BPP_A1888		(0xd << 2)
230 #define WINCON1_BPPMODE_28BPP_A4888		(0xd << 2)
231 #define WINCON1_ALPHA_SEL			(1 << 1)
232 
233 /* S5PV210 */
234 #define SHADOWCON				0x34
235 #define SHADOWCON_WINx_PROTECT(_win)		(1 << (10 + (_win)))
236 /* DMA channels (all windows) */
237 #define SHADOWCON_CHx_ENABLE(_win)		(1 << (_win))
238 /* Local input channels (windows 0-2) */
239 #define SHADOWCON_CHx_LOCAL_ENABLE(_win)	(1 << (5 + (_win)))
240 
241 /* VIDOSDx */
242 
243 #define VIDOSD_BASE				0x40
244 #define VIDOSDxA_TOPLEFT_X_E(_x)		((((_x) & 0x800) >> 11) << 23)
245 #define VIDOSDxA_TOPLEFT_X_MASK			(0x7ff << 11)
246 #define VIDOSDxA_TOPLEFT_X_SHIFT		11
247 #define VIDOSDxA_TOPLEFT_X_LIMIT		0x7ff
248 #define VIDOSDxA_TOPLEFT_X(_x)			(((_x) & 0x7ff) << 11)
249 
250 #define VIDOSDxA_TOPLEFT_Y_E(_x)		((((_x) & 0x800) >> 11) << 22)
251 #define VIDOSDxA_TOPLEFT_Y_MASK			(0x7ff << 0)
252 #define VIDOSDxA_TOPLEFT_Y_SHIFT		0
253 #define VIDOSDxA_TOPLEFT_Y_LIMIT		0x7ff
254 #define VIDOSDxA_TOPLEFT_Y(_x)			(((_x) & 0x7ff) << 0)
255 
256 #define VIDOSDxB_BOTRIGHT_X_E(_x)		((((_x) & 0x800) >> 11) << 23)
257 #define VIDOSDxB_BOTRIGHT_X_MASK		(0x7ff << 11)
258 #define VIDOSDxB_BOTRIGHT_X_SHIFT		11
259 #define VIDOSDxB_BOTRIGHT_X_LIMIT		0x7ff
260 #define VIDOSDxB_BOTRIGHT_X(_x)			(((_x) & 0x7ff) << 11)
261 
262 #define VIDOSDxB_BOTRIGHT_Y_E(_x)		((((_x) & 0x800) >> 11) << 22)
263 #define VIDOSDxB_BOTRIGHT_Y_MASK		(0x7ff << 0)
264 #define VIDOSDxB_BOTRIGHT_Y_SHIFT		0
265 #define VIDOSDxB_BOTRIGHT_Y_LIMIT		0x7ff
266 #define VIDOSDxB_BOTRIGHT_Y(_x)			(((_x) & 0x7ff) << 0)
267 
268 /* For VIDOSD[1..4]C */
269 #define VIDISD14C_ALPHA0_R(_x)			((_x) << 20)
270 #define VIDISD14C_ALPHA0_G_MASK			(0xf << 16)
271 #define VIDISD14C_ALPHA0_G_SHIFT		16
272 #define VIDISD14C_ALPHA0_G_LIMIT		0xf
273 #define VIDISD14C_ALPHA0_G(_x)			((_x) << 16)
274 #define VIDISD14C_ALPHA0_B_MASK			(0xf << 12)
275 #define VIDISD14C_ALPHA0_B_SHIFT		12
276 #define VIDISD14C_ALPHA0_B_LIMIT		0xf
277 #define VIDISD14C_ALPHA0_B(_x)			((_x) << 12)
278 #define VIDISD14C_ALPHA1_R_MASK			(0xf << 8)
279 #define VIDISD14C_ALPHA1_R_SHIFT		8
280 #define VIDISD14C_ALPHA1_R_LIMIT		0xf
281 #define VIDISD14C_ALPHA1_R(_x)			((_x) << 8)
282 #define VIDISD14C_ALPHA1_G_MASK			(0xf << 4)
283 #define VIDISD14C_ALPHA1_G_SHIFT		4
284 #define VIDISD14C_ALPHA1_G_LIMIT		0xf
285 #define VIDISD14C_ALPHA1_G(_x)			((_x) << 4)
286 #define VIDISD14C_ALPHA1_B_MASK			(0xf << 0)
287 #define VIDISD14C_ALPHA1_B_SHIFT		0
288 #define VIDISD14C_ALPHA1_B_LIMIT		0xf
289 #define VIDISD14C_ALPHA1_B(_x)			((_x) << 0)
290 
291 #define VIDW_ALPHA				0x021c
292 #define VIDW_ALPHA_R(_x)			((_x) << 16)
293 #define VIDW_ALPHA_G(_x)			((_x) << 8)
294 #define VIDW_ALPHA_B(_x)			((_x) << 0)
295 
296 /* Video buffer addresses */
297 #define VIDW_BUF_START(_buff)			(0xA0 + ((_buff) * 8))
298 #define VIDW_BUF_START_S(_buff)			(0x40A0 + ((_buff) * 8))
299 #define VIDW_BUF_START1(_buff)			(0xA4 + ((_buff) * 8))
300 #define VIDW_BUF_END(_buff)			(0xD0 + ((_buff) * 8))
301 #define VIDW_BUF_END1(_buff)			(0xD4 + ((_buff) * 8))
302 #define VIDW_BUF_SIZE(_buff)			(0x100 + ((_buff) * 4))
303 
304 #define VIDW_BUF_SIZE_OFFSET_E(_x)		((((_x) & 0x2000) >> 13) << 27)
305 #define VIDW_BUF_SIZE_OFFSET_MASK		(0x1fff << 13)
306 #define VIDW_BUF_SIZE_OFFSET_SHIFT		13
307 #define VIDW_BUF_SIZE_OFFSET_LIMIT		0x1fff
308 #define VIDW_BUF_SIZE_OFFSET(_x)		(((_x) & 0x1fff) << 13)
309 
310 #define VIDW_BUF_SIZE_PAGEWIDTH_E(_x)		((((_x) & 0x2000) >> 13) << 26)
311 #define VIDW_BUF_SIZE_PAGEWIDTH_MASK		(0x1fff << 0)
312 #define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT		0
313 #define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT		0x1fff
314 #define VIDW_BUF_SIZE_PAGEWIDTH(_x)		(((_x) & 0x1fff) << 0)
315 
316 /* Interrupt controls and status */
317 
318 #define VIDINTCON0				0x130
319 #define VIDINTCON0_FIFOINTERVAL_MASK		(0x3f << 20)
320 #define VIDINTCON0_FIFOINTERVAL_SHIFT		20
321 #define VIDINTCON0_FIFOINTERVAL_LIMIT		0x3f
322 #define VIDINTCON0_FIFOINTERVAL(_x)		((_x) << 20)
323 
324 #define VIDINTCON0_INT_SYSMAINCON		(1 << 19)
325 #define VIDINTCON0_INT_SYSSUBCON		(1 << 18)
326 #define VIDINTCON0_INT_I80IFDONE		(1 << 17)
327 
328 #define VIDINTCON0_FRAMESEL0_MASK		(0x3 << 15)
329 #define VIDINTCON0_FRAMESEL0_SHIFT		15
330 #define VIDINTCON0_FRAMESEL0_BACKPORCH		(0x0 << 15)
331 #define VIDINTCON0_FRAMESEL0_VSYNC		(0x1 << 15)
332 #define VIDINTCON0_FRAMESEL0_ACTIVE		(0x2 << 15)
333 #define VIDINTCON0_FRAMESEL0_FRONTPORCH		(0x3 << 15)
334 
335 #define VIDINTCON0_FRAMESEL1			(1 << 13)
336 #define VIDINTCON0_FRAMESEL1_MASK		(0x3 << 13)
337 #define VIDINTCON0_FRAMESEL1_NONE		(0x0 << 13)
338 #define VIDINTCON0_FRAMESEL1_BACKPORCH		(0x1 << 13)
339 #define VIDINTCON0_FRAMESEL1_VSYNC		(0x2 << 13)
340 #define VIDINTCON0_FRAMESEL1_FRONTPORCH		(0x3 << 13)
341 
342 #define VIDINTCON0_INT_FRAME			(1 << 12)
343 #define VIDINTCON0_FIFIOSEL_MASK		(0x7f << 5)
344 #define VIDINTCON0_FIFIOSEL_SHIFT		5
345 #define VIDINTCON0_FIFIOSEL_WINDOW0		(0x1 << 5)
346 #define VIDINTCON0_FIFIOSEL_WINDOW1		(0x2 << 5)
347 #define VIDINTCON0_FIFIOSEL_WINDOW2		(0x10 << 5)
348 #define VIDINTCON0_FIFIOSEL_WINDOW3		(0x20 << 5)
349 #define VIDINTCON0_FIFIOSEL_WINDOW4		(0x40 << 5)
350 
351 #define VIDINTCON0_FIFOLEVEL_MASK		(0x7 << 2)
352 #define VIDINTCON0_FIFOLEVEL_SHIFT		2
353 #define VIDINTCON0_FIFOLEVEL_TO25PC		(0x0 << 2)
354 #define VIDINTCON0_FIFOLEVEL_TO50PC		(0x1 << 2)
355 #define VIDINTCON0_FIFOLEVEL_TO75PC		(0x2 << 2)
356 #define VIDINTCON0_FIFOLEVEL_EMPTY		(0x3 << 2)
357 #define VIDINTCON0_FIFOLEVEL_FULL		(0x4 << 2)
358 
359 #define VIDINTCON0_INT_FIFO_MASK		(0x3 << 0)
360 #define VIDINTCON0_INT_FIFO_SHIFT		0
361 #define VIDINTCON0_INT_ENABLE			(1 << 0)
362 
363 #define VIDINTCON1				0x134
364 #define VIDINTCON1_INT_I80			(1 << 2)
365 #define VIDINTCON1_INT_FRAME			(1 << 1)
366 #define VIDINTCON1_INT_FIFO			(1 << 0)
367 
368 /* Window colour-key control registers */
369 #define WKEYCON					0x140
370 
371 #define WKEYCON0				0x00
372 #define WKEYCON1				0x04
373 
374 #define WxKEYCON0_KEYBL_EN			(1 << 26)
375 #define WxKEYCON0_KEYEN_F			(1 << 25)
376 #define WxKEYCON0_DIRCON			(1 << 24)
377 #define WxKEYCON0_COMPKEY_MASK			(0xffffff << 0)
378 #define WxKEYCON0_COMPKEY_SHIFT			0
379 #define WxKEYCON0_COMPKEY_LIMIT			0xffffff
380 #define WxKEYCON0_COMPKEY(_x)			((_x) << 0)
381 #define WxKEYCON1_COLVAL_MASK			(0xffffff << 0)
382 #define WxKEYCON1_COLVAL_SHIFT			0
383 #define WxKEYCON1_COLVAL_LIMIT			0xffffff
384 #define WxKEYCON1_COLVAL(_x)			((_x) << 0)
385 
386 /* Dithering control */
387 #define DITHMODE				0x170
388 #define DITHMODE_R_POS_MASK			(0x3 << 5)
389 #define DITHMODE_R_POS_SHIFT			5
390 #define DITHMODE_R_POS_8BIT			(0x0 << 5)
391 #define DITHMODE_R_POS_6BIT			(0x1 << 5)
392 #define DITHMODE_R_POS_5BIT			(0x2 << 5)
393 #define DITHMODE_G_POS_MASK			(0x3 << 3)
394 #define DITHMODE_G_POS_SHIFT			3
395 #define DITHMODE_G_POS_8BIT			(0x0 << 3)
396 #define DITHMODE_G_POS_6BIT			(0x1 << 3)
397 #define DITHMODE_G_POS_5BIT			(0x2 << 3)
398 #define DITHMODE_B_POS_MASK			(0x3 << 1)
399 #define DITHMODE_B_POS_SHIFT			1
400 #define DITHMODE_B_POS_8BIT			(0x0 << 1)
401 #define DITHMODE_B_POS_6BIT			(0x1 << 1)
402 #define DITHMODE_B_POS_5BIT			(0x2 << 1)
403 #define DITHMODE_DITH_EN			(1 << 0)
404 
405 /* Window blanking (MAP) */
406 #define WINxMAP(_win)				(0x180 + ((_win) * 4))
407 #define WINxMAP_MAP				(1 << 24)
408 #define WINxMAP_MAP_COLOUR_MASK			(0xffffff << 0)
409 #define WINxMAP_MAP_COLOUR_SHIFT		0
410 #define WINxMAP_MAP_COLOUR_LIMIT		0xffffff
411 #define WINxMAP_MAP_COLOUR(_x)			((_x) << 0)
412 
413 /* Winodw palette control */
414 #define WPALCON					0x1A0
415 #define WPALCON_PAL_UPDATE			(1 << 9)
416 #define WPALCON_W4PAL_16BPP_A555		(1 << 8)
417 #define WPALCON_W3PAL_16BPP_A555		(1 << 7)
418 #define WPALCON_W2PAL_16BPP_A555		(1 << 6)
419 #define WPALCON_W1PAL_MASK			(0x7 << 3)
420 #define WPALCON_W1PAL_SHIFT			3
421 #define WPALCON_W1PAL_25BPP_A888		(0x0 << 3)
422 #define WPALCON_W1PAL_24BPP			(0x1 << 3)
423 #define WPALCON_W1PAL_19BPP_A666		(0x2 << 3)
424 #define WPALCON_W1PAL_18BPP_A665		(0x3 << 3)
425 #define WPALCON_W1PAL_18BPP			(0x4 << 3)
426 #define WPALCON_W1PAL_16BPP_A555		(0x5 << 3)
427 #define WPALCON_W1PAL_16BPP_565			(0x6 << 3)
428 #define WPALCON_W0PAL_MASK			(0x7 << 0)
429 #define WPALCON_W0PAL_SHIFT			0
430 #define WPALCON_W0PAL_25BPP_A888		(0x0 << 0)
431 #define WPALCON_W0PAL_24BPP			(0x1 << 0)
432 #define WPALCON_W0PAL_19BPP_A666		(0x2 << 0)
433 #define WPALCON_W0PAL_18BPP_A665		(0x3 << 0)
434 #define WPALCON_W0PAL_18BPP			(0x4 << 0)
435 #define WPALCON_W0PAL_16BPP_A555		(0x5 << 0)
436 #define WPALCON_W0PAL_16BPP_565			(0x6 << 0)
437 
438 /* Blending equation control */
439 #define BLENDEQx(_win)				(0x244 + ((_win - 1) * 4))
440 #define BLENDEQ_ZERO				0x0
441 #define BLENDEQ_ONE				0x1
442 #define BLENDEQ_ALPHA_A				0x2
443 #define BLENDEQ_ONE_MINUS_ALPHA_A		0x3
444 #define BLENDEQ_ALPHA0				0x6
445 #define BLENDEQ_B_FUNC_F(_x)			(_x << 6)
446 #define BLENDEQ_A_FUNC_F(_x)			(_x << 0)
447 #define BLENDCON				0x260
448 #define BLENDCON_NEW_MASK			(1 << 0)
449 #define BLENDCON_NEW_8BIT_ALPHA_VALUE		(1 << 0)
450 #define BLENDCON_NEW_4BIT_ALPHA_VALUE		(0 << 0)
451 
452 /* Display port clock control */
453 #define DP_MIE_CLKCON				0x27c
454 #define DP_MIE_CLK_DISABLE			0x0
455 #define DP_MIE_CLK_DP_ENABLE			0x2
456 #define DP_MIE_CLK_MIE_ENABLE			0x3
457 
458 /* Notes on per-window bpp settings
459  *
460  * Value	Win0	 Win1	  Win2	   Win3	    Win 4
461  * 0000		1(P)	 1(P)	  1(P)	   1(P)	    1(P)
462  * 0001		2(P)	 2(P)     2(P)	   2(P)	    2(P)
463  * 0010		4(P)	 4(P)     4(P)	   4(P)     -none-
464  * 0011		8(P)	 8(P)     -none-   -none-   -none-
465  * 0100		-none-	 8(A232)  8(A232)  -none-   -none-
466  * 0101		16(565)	 16(565)  16(565)  16(565)   16(565)
467  * 0110		-none-	 16(A555) 16(A555) 16(A555)  16(A555)
468  * 0111		16(I555) 16(I565) 16(I555) 16(I555)  16(I555)
469  * 1000		18(666)	 18(666)  18(666)  18(666)   18(666)
470  * 1001		-none-	 18(A665) 18(A665) 18(A665)  16(A665)
471  * 1010		-none-	 19(A666) 19(A666) 19(A666)  19(A666)
472  * 1011		24(888)	 24(888)  24(888)  24(888)   24(888)
473  * 1100		-none-	 24(A887) 24(A887) 24(A887)  24(A887)
474  * 1101		-none-	 25(A888) 25(A888) 25(A888)  25(A888)
475  * 1110		-none-	 -none-	  -none-   -none-    -none-
476  * 1111		-none-	 -none-   -none-   -none-    -none-
477 */
478 
479 #define WIN_RGB_ORDER(_win)			(0x2020 + ((_win) * 4))
480 #define WIN_RGB_ORDER_FORWARD			(0 << 11)
481 #define WIN_RGB_ORDER_REVERSE			(1 << 11)
482 
483 /* FIMD Version 8 register offset definitions */
484 #define FIMD_V8_VIDTCON0	0x20010
485 #define FIMD_V8_VIDTCON1	0x20014
486 #define FIMD_V8_VIDTCON2	0x20018
487 #define FIMD_V8_VIDTCON3	0x2001C
488 #define FIMD_V8_VIDCON1		0x20004
489