1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * vmx.h: VMX Architecture related definitions
4 * Copyright (c) 2004, Intel Corporation.
5 *
6 * A few random additions are:
7 * Copyright (C) 2006 Qumranet
8 * Avi Kivity <avi@qumranet.com>
9 * Yaniv Kamay <yaniv@qumranet.com>
10 */
11 #ifndef VMX_H
12 #define VMX_H
13
14
15 #include <linux/bitops.h>
16 #include <linux/types.h>
17 #include <uapi/asm/vmx.h>
18 #include <asm/vmxfeatures.h>
19
20 #define VMCS_CONTROL_BIT(x) BIT(VMX_FEATURE_##x & 0x1f)
21
22 /*
23 * Definitions of Primary Processor-Based VM-Execution Controls.
24 */
25 #define CPU_BASED_INTR_WINDOW_EXITING VMCS_CONTROL_BIT(INTR_WINDOW_EXITING)
26 #define CPU_BASED_USE_TSC_OFFSETTING VMCS_CONTROL_BIT(USE_TSC_OFFSETTING)
27 #define CPU_BASED_HLT_EXITING VMCS_CONTROL_BIT(HLT_EXITING)
28 #define CPU_BASED_INVLPG_EXITING VMCS_CONTROL_BIT(INVLPG_EXITING)
29 #define CPU_BASED_MWAIT_EXITING VMCS_CONTROL_BIT(MWAIT_EXITING)
30 #define CPU_BASED_RDPMC_EXITING VMCS_CONTROL_BIT(RDPMC_EXITING)
31 #define CPU_BASED_RDTSC_EXITING VMCS_CONTROL_BIT(RDTSC_EXITING)
32 #define CPU_BASED_CR3_LOAD_EXITING VMCS_CONTROL_BIT(CR3_LOAD_EXITING)
33 #define CPU_BASED_CR3_STORE_EXITING VMCS_CONTROL_BIT(CR3_STORE_EXITING)
34 #define CPU_BASED_ACTIVATE_TERTIARY_CONTROLS VMCS_CONTROL_BIT(TERTIARY_CONTROLS)
35 #define CPU_BASED_CR8_LOAD_EXITING VMCS_CONTROL_BIT(CR8_LOAD_EXITING)
36 #define CPU_BASED_CR8_STORE_EXITING VMCS_CONTROL_BIT(CR8_STORE_EXITING)
37 #define CPU_BASED_TPR_SHADOW VMCS_CONTROL_BIT(VIRTUAL_TPR)
38 #define CPU_BASED_NMI_WINDOW_EXITING VMCS_CONTROL_BIT(NMI_WINDOW_EXITING)
39 #define CPU_BASED_MOV_DR_EXITING VMCS_CONTROL_BIT(MOV_DR_EXITING)
40 #define CPU_BASED_UNCOND_IO_EXITING VMCS_CONTROL_BIT(UNCOND_IO_EXITING)
41 #define CPU_BASED_USE_IO_BITMAPS VMCS_CONTROL_BIT(USE_IO_BITMAPS)
42 #define CPU_BASED_MONITOR_TRAP_FLAG VMCS_CONTROL_BIT(MONITOR_TRAP_FLAG)
43 #define CPU_BASED_USE_MSR_BITMAPS VMCS_CONTROL_BIT(USE_MSR_BITMAPS)
44 #define CPU_BASED_MONITOR_EXITING VMCS_CONTROL_BIT(MONITOR_EXITING)
45 #define CPU_BASED_PAUSE_EXITING VMCS_CONTROL_BIT(PAUSE_EXITING)
46 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS VMCS_CONTROL_BIT(SEC_CONTROLS)
47
48 #define CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x0401e172
49
50 /*
51 * Definitions of Secondary Processor-Based VM-Execution Controls.
52 */
53 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES VMCS_CONTROL_BIT(VIRT_APIC_ACCESSES)
54 #define SECONDARY_EXEC_ENABLE_EPT VMCS_CONTROL_BIT(EPT)
55 #define SECONDARY_EXEC_DESC VMCS_CONTROL_BIT(DESC_EXITING)
56 #define SECONDARY_EXEC_ENABLE_RDTSCP VMCS_CONTROL_BIT(RDTSCP)
57 #define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE VMCS_CONTROL_BIT(VIRTUAL_X2APIC)
58 #define SECONDARY_EXEC_ENABLE_VPID VMCS_CONTROL_BIT(VPID)
59 #define SECONDARY_EXEC_WBINVD_EXITING VMCS_CONTROL_BIT(WBINVD_EXITING)
60 #define SECONDARY_EXEC_UNRESTRICTED_GUEST VMCS_CONTROL_BIT(UNRESTRICTED_GUEST)
61 #define SECONDARY_EXEC_APIC_REGISTER_VIRT VMCS_CONTROL_BIT(APIC_REGISTER_VIRT)
62 #define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY VMCS_CONTROL_BIT(VIRT_INTR_DELIVERY)
63 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING VMCS_CONTROL_BIT(PAUSE_LOOP_EXITING)
64 #define SECONDARY_EXEC_RDRAND_EXITING VMCS_CONTROL_BIT(RDRAND_EXITING)
65 #define SECONDARY_EXEC_ENABLE_INVPCID VMCS_CONTROL_BIT(INVPCID)
66 #define SECONDARY_EXEC_ENABLE_VMFUNC VMCS_CONTROL_BIT(VMFUNC)
67 #define SECONDARY_EXEC_SHADOW_VMCS VMCS_CONTROL_BIT(SHADOW_VMCS)
68 #define SECONDARY_EXEC_ENCLS_EXITING VMCS_CONTROL_BIT(ENCLS_EXITING)
69 #define SECONDARY_EXEC_RDSEED_EXITING VMCS_CONTROL_BIT(RDSEED_EXITING)
70 #define SECONDARY_EXEC_ENABLE_PML VMCS_CONTROL_BIT(PAGE_MOD_LOGGING)
71 #define SECONDARY_EXEC_PT_CONCEAL_VMX VMCS_CONTROL_BIT(PT_CONCEAL_VMX)
72 #define SECONDARY_EXEC_XSAVES VMCS_CONTROL_BIT(XSAVES)
73 #define SECONDARY_EXEC_MODE_BASED_EPT_EXEC VMCS_CONTROL_BIT(MODE_BASED_EPT_EXEC)
74 #define SECONDARY_EXEC_PT_USE_GPA VMCS_CONTROL_BIT(PT_USE_GPA)
75 #define SECONDARY_EXEC_TSC_SCALING VMCS_CONTROL_BIT(TSC_SCALING)
76 #define SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE VMCS_CONTROL_BIT(USR_WAIT_PAUSE)
77 #define SECONDARY_EXEC_BUS_LOCK_DETECTION VMCS_CONTROL_BIT(BUS_LOCK_DETECTION)
78 #define SECONDARY_EXEC_NOTIFY_VM_EXITING VMCS_CONTROL_BIT(NOTIFY_VM_EXITING)
79
80 /*
81 * Definitions of Tertiary Processor-Based VM-Execution Controls.
82 */
83 #define TERTIARY_EXEC_IPI_VIRT VMCS_CONTROL_BIT(IPI_VIRT)
84
85 #define PIN_BASED_EXT_INTR_MASK VMCS_CONTROL_BIT(INTR_EXITING)
86 #define PIN_BASED_NMI_EXITING VMCS_CONTROL_BIT(NMI_EXITING)
87 #define PIN_BASED_VIRTUAL_NMIS VMCS_CONTROL_BIT(VIRTUAL_NMIS)
88 #define PIN_BASED_VMX_PREEMPTION_TIMER VMCS_CONTROL_BIT(PREEMPTION_TIMER)
89 #define PIN_BASED_POSTED_INTR VMCS_CONTROL_BIT(POSTED_INTR)
90
91 #define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x00000016
92
93 #define VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004
94 #define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
95 #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
96 #define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
97 #define VM_EXIT_SAVE_IA32_PAT 0x00040000
98 #define VM_EXIT_LOAD_IA32_PAT 0x00080000
99 #define VM_EXIT_SAVE_IA32_EFER 0x00100000
100 #define VM_EXIT_LOAD_IA32_EFER 0x00200000
101 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
102 #define VM_EXIT_CLEAR_BNDCFGS 0x00800000
103 #define VM_EXIT_PT_CONCEAL_PIP 0x01000000
104 #define VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000
105
106 #define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff
107
108 #define VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004
109 #define VM_ENTRY_IA32E_MODE 0x00000200
110 #define VM_ENTRY_SMM 0x00000400
111 #define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
112 #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
113 #define VM_ENTRY_LOAD_IA32_PAT 0x00004000
114 #define VM_ENTRY_LOAD_IA32_EFER 0x00008000
115 #define VM_ENTRY_LOAD_BNDCFGS 0x00010000
116 #define VM_ENTRY_PT_CONCEAL_PIP 0x00020000
117 #define VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000
118
119 #define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff
120
121 #define VMX_MISC_PREEMPTION_TIMER_RATE_MASK 0x0000001f
122 #define VMX_MISC_SAVE_EFER_LMA 0x00000020
123 #define VMX_MISC_ACTIVITY_HLT 0x00000040
124 #define VMX_MISC_ACTIVITY_WAIT_SIPI 0x00000100
125 #define VMX_MISC_ZERO_LEN_INS 0x40000000
126 #define VMX_MISC_MSR_LIST_MULTIPLIER 512
127
128 /* VMFUNC functions */
129 #define VMFUNC_CONTROL_BIT(x) BIT((VMX_FEATURE_##x & 0x1f) - 28)
130
131 #define VMX_VMFUNC_EPTP_SWITCHING VMFUNC_CONTROL_BIT(EPTP_SWITCHING)
132 #define VMFUNC_EPTP_ENTRIES 512
133
vmx_basic_vmcs_revision_id(u64 vmx_basic)134 static inline u32 vmx_basic_vmcs_revision_id(u64 vmx_basic)
135 {
136 return vmx_basic & GENMASK_ULL(30, 0);
137 }
138
vmx_basic_vmcs_size(u64 vmx_basic)139 static inline u32 vmx_basic_vmcs_size(u64 vmx_basic)
140 {
141 return (vmx_basic & GENMASK_ULL(44, 32)) >> 32;
142 }
143
vmx_misc_preemption_timer_rate(u64 vmx_misc)144 static inline int vmx_misc_preemption_timer_rate(u64 vmx_misc)
145 {
146 return vmx_misc & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
147 }
148
vmx_misc_cr3_count(u64 vmx_misc)149 static inline int vmx_misc_cr3_count(u64 vmx_misc)
150 {
151 return (vmx_misc & GENMASK_ULL(24, 16)) >> 16;
152 }
153
vmx_misc_max_msr(u64 vmx_misc)154 static inline int vmx_misc_max_msr(u64 vmx_misc)
155 {
156 return (vmx_misc & GENMASK_ULL(27, 25)) >> 25;
157 }
158
vmx_misc_mseg_revid(u64 vmx_misc)159 static inline int vmx_misc_mseg_revid(u64 vmx_misc)
160 {
161 return (vmx_misc & GENMASK_ULL(63, 32)) >> 32;
162 }
163
164 /* VMCS Encodings */
165 enum vmcs_field {
166 VIRTUAL_PROCESSOR_ID = 0x00000000,
167 POSTED_INTR_NV = 0x00000002,
168 LAST_PID_POINTER_INDEX = 0x00000008,
169 GUEST_ES_SELECTOR = 0x00000800,
170 GUEST_CS_SELECTOR = 0x00000802,
171 GUEST_SS_SELECTOR = 0x00000804,
172 GUEST_DS_SELECTOR = 0x00000806,
173 GUEST_FS_SELECTOR = 0x00000808,
174 GUEST_GS_SELECTOR = 0x0000080a,
175 GUEST_LDTR_SELECTOR = 0x0000080c,
176 GUEST_TR_SELECTOR = 0x0000080e,
177 GUEST_INTR_STATUS = 0x00000810,
178 GUEST_PML_INDEX = 0x00000812,
179 HOST_ES_SELECTOR = 0x00000c00,
180 HOST_CS_SELECTOR = 0x00000c02,
181 HOST_SS_SELECTOR = 0x00000c04,
182 HOST_DS_SELECTOR = 0x00000c06,
183 HOST_FS_SELECTOR = 0x00000c08,
184 HOST_GS_SELECTOR = 0x00000c0a,
185 HOST_TR_SELECTOR = 0x00000c0c,
186 IO_BITMAP_A = 0x00002000,
187 IO_BITMAP_A_HIGH = 0x00002001,
188 IO_BITMAP_B = 0x00002002,
189 IO_BITMAP_B_HIGH = 0x00002003,
190 MSR_BITMAP = 0x00002004,
191 MSR_BITMAP_HIGH = 0x00002005,
192 VM_EXIT_MSR_STORE_ADDR = 0x00002006,
193 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
194 VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
195 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
196 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a,
197 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b,
198 PML_ADDRESS = 0x0000200e,
199 PML_ADDRESS_HIGH = 0x0000200f,
200 TSC_OFFSET = 0x00002010,
201 TSC_OFFSET_HIGH = 0x00002011,
202 VIRTUAL_APIC_PAGE_ADDR = 0x00002012,
203 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
204 APIC_ACCESS_ADDR = 0x00002014,
205 APIC_ACCESS_ADDR_HIGH = 0x00002015,
206 POSTED_INTR_DESC_ADDR = 0x00002016,
207 POSTED_INTR_DESC_ADDR_HIGH = 0x00002017,
208 VM_FUNCTION_CONTROL = 0x00002018,
209 VM_FUNCTION_CONTROL_HIGH = 0x00002019,
210 EPT_POINTER = 0x0000201a,
211 EPT_POINTER_HIGH = 0x0000201b,
212 EOI_EXIT_BITMAP0 = 0x0000201c,
213 EOI_EXIT_BITMAP0_HIGH = 0x0000201d,
214 EOI_EXIT_BITMAP1 = 0x0000201e,
215 EOI_EXIT_BITMAP1_HIGH = 0x0000201f,
216 EOI_EXIT_BITMAP2 = 0x00002020,
217 EOI_EXIT_BITMAP2_HIGH = 0x00002021,
218 EOI_EXIT_BITMAP3 = 0x00002022,
219 EOI_EXIT_BITMAP3_HIGH = 0x00002023,
220 EPTP_LIST_ADDRESS = 0x00002024,
221 EPTP_LIST_ADDRESS_HIGH = 0x00002025,
222 VMREAD_BITMAP = 0x00002026,
223 VMREAD_BITMAP_HIGH = 0x00002027,
224 VMWRITE_BITMAP = 0x00002028,
225 VMWRITE_BITMAP_HIGH = 0x00002029,
226 XSS_EXIT_BITMAP = 0x0000202C,
227 XSS_EXIT_BITMAP_HIGH = 0x0000202D,
228 ENCLS_EXITING_BITMAP = 0x0000202E,
229 ENCLS_EXITING_BITMAP_HIGH = 0x0000202F,
230 TSC_MULTIPLIER = 0x00002032,
231 TSC_MULTIPLIER_HIGH = 0x00002033,
232 TERTIARY_VM_EXEC_CONTROL = 0x00002034,
233 TERTIARY_VM_EXEC_CONTROL_HIGH = 0x00002035,
234 PID_POINTER_TABLE = 0x00002042,
235 PID_POINTER_TABLE_HIGH = 0x00002043,
236 GUEST_PHYSICAL_ADDRESS = 0x00002400,
237 GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401,
238 VMCS_LINK_POINTER = 0x00002800,
239 VMCS_LINK_POINTER_HIGH = 0x00002801,
240 GUEST_IA32_DEBUGCTL = 0x00002802,
241 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
242 GUEST_IA32_PAT = 0x00002804,
243 GUEST_IA32_PAT_HIGH = 0x00002805,
244 GUEST_IA32_EFER = 0x00002806,
245 GUEST_IA32_EFER_HIGH = 0x00002807,
246 GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808,
247 GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809,
248 GUEST_PDPTR0 = 0x0000280a,
249 GUEST_PDPTR0_HIGH = 0x0000280b,
250 GUEST_PDPTR1 = 0x0000280c,
251 GUEST_PDPTR1_HIGH = 0x0000280d,
252 GUEST_PDPTR2 = 0x0000280e,
253 GUEST_PDPTR2_HIGH = 0x0000280f,
254 GUEST_PDPTR3 = 0x00002810,
255 GUEST_PDPTR3_HIGH = 0x00002811,
256 GUEST_BNDCFGS = 0x00002812,
257 GUEST_BNDCFGS_HIGH = 0x00002813,
258 GUEST_IA32_RTIT_CTL = 0x00002814,
259 GUEST_IA32_RTIT_CTL_HIGH = 0x00002815,
260 HOST_IA32_PAT = 0x00002c00,
261 HOST_IA32_PAT_HIGH = 0x00002c01,
262 HOST_IA32_EFER = 0x00002c02,
263 HOST_IA32_EFER_HIGH = 0x00002c03,
264 HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04,
265 HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05,
266 PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
267 CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
268 EXCEPTION_BITMAP = 0x00004004,
269 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006,
270 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008,
271 CR3_TARGET_COUNT = 0x0000400a,
272 VM_EXIT_CONTROLS = 0x0000400c,
273 VM_EXIT_MSR_STORE_COUNT = 0x0000400e,
274 VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
275 VM_ENTRY_CONTROLS = 0x00004012,
276 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
277 VM_ENTRY_INTR_INFO_FIELD = 0x00004016,
278 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018,
279 VM_ENTRY_INSTRUCTION_LEN = 0x0000401a,
280 TPR_THRESHOLD = 0x0000401c,
281 SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
282 PLE_GAP = 0x00004020,
283 PLE_WINDOW = 0x00004022,
284 NOTIFY_WINDOW = 0x00004024,
285 VM_INSTRUCTION_ERROR = 0x00004400,
286 VM_EXIT_REASON = 0x00004402,
287 VM_EXIT_INTR_INFO = 0x00004404,
288 VM_EXIT_INTR_ERROR_CODE = 0x00004406,
289 IDT_VECTORING_INFO_FIELD = 0x00004408,
290 IDT_VECTORING_ERROR_CODE = 0x0000440a,
291 VM_EXIT_INSTRUCTION_LEN = 0x0000440c,
292 VMX_INSTRUCTION_INFO = 0x0000440e,
293 GUEST_ES_LIMIT = 0x00004800,
294 GUEST_CS_LIMIT = 0x00004802,
295 GUEST_SS_LIMIT = 0x00004804,
296 GUEST_DS_LIMIT = 0x00004806,
297 GUEST_FS_LIMIT = 0x00004808,
298 GUEST_GS_LIMIT = 0x0000480a,
299 GUEST_LDTR_LIMIT = 0x0000480c,
300 GUEST_TR_LIMIT = 0x0000480e,
301 GUEST_GDTR_LIMIT = 0x00004810,
302 GUEST_IDTR_LIMIT = 0x00004812,
303 GUEST_ES_AR_BYTES = 0x00004814,
304 GUEST_CS_AR_BYTES = 0x00004816,
305 GUEST_SS_AR_BYTES = 0x00004818,
306 GUEST_DS_AR_BYTES = 0x0000481a,
307 GUEST_FS_AR_BYTES = 0x0000481c,
308 GUEST_GS_AR_BYTES = 0x0000481e,
309 GUEST_LDTR_AR_BYTES = 0x00004820,
310 GUEST_TR_AR_BYTES = 0x00004822,
311 GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
312 GUEST_ACTIVITY_STATE = 0x00004826,
313 GUEST_SYSENTER_CS = 0x0000482A,
314 VMX_PREEMPTION_TIMER_VALUE = 0x0000482E,
315 HOST_IA32_SYSENTER_CS = 0x00004c00,
316 CR0_GUEST_HOST_MASK = 0x00006000,
317 CR4_GUEST_HOST_MASK = 0x00006002,
318 CR0_READ_SHADOW = 0x00006004,
319 CR4_READ_SHADOW = 0x00006006,
320 CR3_TARGET_VALUE0 = 0x00006008,
321 CR3_TARGET_VALUE1 = 0x0000600a,
322 CR3_TARGET_VALUE2 = 0x0000600c,
323 CR3_TARGET_VALUE3 = 0x0000600e,
324 EXIT_QUALIFICATION = 0x00006400,
325 GUEST_LINEAR_ADDRESS = 0x0000640a,
326 GUEST_CR0 = 0x00006800,
327 GUEST_CR3 = 0x00006802,
328 GUEST_CR4 = 0x00006804,
329 GUEST_ES_BASE = 0x00006806,
330 GUEST_CS_BASE = 0x00006808,
331 GUEST_SS_BASE = 0x0000680a,
332 GUEST_DS_BASE = 0x0000680c,
333 GUEST_FS_BASE = 0x0000680e,
334 GUEST_GS_BASE = 0x00006810,
335 GUEST_LDTR_BASE = 0x00006812,
336 GUEST_TR_BASE = 0x00006814,
337 GUEST_GDTR_BASE = 0x00006816,
338 GUEST_IDTR_BASE = 0x00006818,
339 GUEST_DR7 = 0x0000681a,
340 GUEST_RSP = 0x0000681c,
341 GUEST_RIP = 0x0000681e,
342 GUEST_RFLAGS = 0x00006820,
343 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
344 GUEST_SYSENTER_ESP = 0x00006824,
345 GUEST_SYSENTER_EIP = 0x00006826,
346 HOST_CR0 = 0x00006c00,
347 HOST_CR3 = 0x00006c02,
348 HOST_CR4 = 0x00006c04,
349 HOST_FS_BASE = 0x00006c06,
350 HOST_GS_BASE = 0x00006c08,
351 HOST_TR_BASE = 0x00006c0a,
352 HOST_GDTR_BASE = 0x00006c0c,
353 HOST_IDTR_BASE = 0x00006c0e,
354 HOST_IA32_SYSENTER_ESP = 0x00006c10,
355 HOST_IA32_SYSENTER_EIP = 0x00006c12,
356 HOST_RSP = 0x00006c14,
357 HOST_RIP = 0x00006c16,
358 };
359
360 /*
361 * Interruption-information format
362 */
363 #define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */
364 #define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */
365 #define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */
366 #define INTR_INFO_UNBLOCK_NMI 0x1000 /* 12 */
367 #define INTR_INFO_VALID_MASK 0x80000000 /* 31 */
368 #define INTR_INFO_RESVD_BITS_MASK 0x7ffff000
369
370 #define VECTORING_INFO_VECTOR_MASK INTR_INFO_VECTOR_MASK
371 #define VECTORING_INFO_TYPE_MASK INTR_INFO_INTR_TYPE_MASK
372 #define VECTORING_INFO_DELIVER_CODE_MASK INTR_INFO_DELIVER_CODE_MASK
373 #define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK
374
375 #define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */
376 #define INTR_TYPE_RESERVED (1 << 8) /* reserved */
377 #define INTR_TYPE_NMI_INTR (2 << 8) /* NMI */
378 #define INTR_TYPE_HARD_EXCEPTION (3 << 8) /* processor exception */
379 #define INTR_TYPE_SOFT_INTR (4 << 8) /* software interrupt */
380 #define INTR_TYPE_PRIV_SW_EXCEPTION (5 << 8) /* ICE breakpoint - undocumented */
381 #define INTR_TYPE_SOFT_EXCEPTION (6 << 8) /* software exception */
382 #define INTR_TYPE_OTHER_EVENT (7 << 8) /* other event */
383
384 /* GUEST_INTERRUPTIBILITY_INFO flags. */
385 #define GUEST_INTR_STATE_STI 0x00000001
386 #define GUEST_INTR_STATE_MOV_SS 0x00000002
387 #define GUEST_INTR_STATE_SMI 0x00000004
388 #define GUEST_INTR_STATE_NMI 0x00000008
389 #define GUEST_INTR_STATE_ENCLAVE_INTR 0x00000010
390
391 /* GUEST_ACTIVITY_STATE flags */
392 #define GUEST_ACTIVITY_ACTIVE 0
393 #define GUEST_ACTIVITY_HLT 1
394 #define GUEST_ACTIVITY_SHUTDOWN 2
395 #define GUEST_ACTIVITY_WAIT_SIPI 3
396
397 /*
398 * Exit Qualifications for MOV for Control Register Access
399 */
400 #define CONTROL_REG_ACCESS_NUM 0x7 /* 2:0, number of control reg.*/
401 #define CONTROL_REG_ACCESS_TYPE 0x30 /* 5:4, access type */
402 #define CONTROL_REG_ACCESS_REG 0xf00 /* 10:8, general purpose reg. */
403 #define LMSW_SOURCE_DATA_SHIFT 16
404 #define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
405 #define REG_EAX (0 << 8)
406 #define REG_ECX (1 << 8)
407 #define REG_EDX (2 << 8)
408 #define REG_EBX (3 << 8)
409 #define REG_ESP (4 << 8)
410 #define REG_EBP (5 << 8)
411 #define REG_ESI (6 << 8)
412 #define REG_EDI (7 << 8)
413 #define REG_R8 (8 << 8)
414 #define REG_R9 (9 << 8)
415 #define REG_R10 (10 << 8)
416 #define REG_R11 (11 << 8)
417 #define REG_R12 (12 << 8)
418 #define REG_R13 (13 << 8)
419 #define REG_R14 (14 << 8)
420 #define REG_R15 (15 << 8)
421
422 /*
423 * Exit Qualifications for MOV for Debug Register Access
424 */
425 #define DEBUG_REG_ACCESS_NUM 0x7 /* 2:0, number of debug reg. */
426 #define DEBUG_REG_ACCESS_TYPE 0x10 /* 4, direction of access */
427 #define TYPE_MOV_TO_DR (0 << 4)
428 #define TYPE_MOV_FROM_DR (1 << 4)
429 #define DEBUG_REG_ACCESS_REG(eq) (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */
430
431
432 /*
433 * Exit Qualifications for APIC-Access
434 */
435 #define APIC_ACCESS_OFFSET 0xfff /* 11:0, offset within the APIC page */
436 #define APIC_ACCESS_TYPE 0xf000 /* 15:12, access type */
437 #define TYPE_LINEAR_APIC_INST_READ (0 << 12)
438 #define TYPE_LINEAR_APIC_INST_WRITE (1 << 12)
439 #define TYPE_LINEAR_APIC_INST_FETCH (2 << 12)
440 #define TYPE_LINEAR_APIC_EVENT (3 << 12)
441 #define TYPE_PHYSICAL_APIC_EVENT (10 << 12)
442 #define TYPE_PHYSICAL_APIC_INST (15 << 12)
443
444 /* segment AR in VMCS -- these are different from what LAR reports */
445 #define VMX_SEGMENT_AR_L_MASK (1 << 13)
446
447 #define VMX_AR_TYPE_ACCESSES_MASK 1
448 #define VMX_AR_TYPE_READABLE_MASK (1 << 1)
449 #define VMX_AR_TYPE_WRITEABLE_MASK (1 << 2)
450 #define VMX_AR_TYPE_CODE_MASK (1 << 3)
451 #define VMX_AR_TYPE_MASK 0x0f
452 #define VMX_AR_TYPE_BUSY_64_TSS 11
453 #define VMX_AR_TYPE_BUSY_32_TSS 11
454 #define VMX_AR_TYPE_BUSY_16_TSS 3
455 #define VMX_AR_TYPE_LDT 2
456
457 #define VMX_AR_UNUSABLE_MASK (1 << 16)
458 #define VMX_AR_S_MASK (1 << 4)
459 #define VMX_AR_P_MASK (1 << 7)
460 #define VMX_AR_L_MASK (1 << 13)
461 #define VMX_AR_DB_MASK (1 << 14)
462 #define VMX_AR_G_MASK (1 << 15)
463 #define VMX_AR_DPL_SHIFT 5
464 #define VMX_AR_DPL(ar) (((ar) >> VMX_AR_DPL_SHIFT) & 3)
465
466 #define VMX_AR_RESERVD_MASK 0xfffe0f00
467
468 #define TSS_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 0)
469 #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 1)
470 #define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 2)
471
472 #define VMX_NR_VPIDS (1 << 16)
473 #define VMX_VPID_EXTENT_INDIVIDUAL_ADDR 0
474 #define VMX_VPID_EXTENT_SINGLE_CONTEXT 1
475 #define VMX_VPID_EXTENT_ALL_CONTEXT 2
476 #define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL 3
477
478 #define VMX_EPT_EXTENT_CONTEXT 1
479 #define VMX_EPT_EXTENT_GLOBAL 2
480 #define VMX_EPT_EXTENT_SHIFT 24
481
482 #define VMX_EPT_EXECUTE_ONLY_BIT (1ull)
483 #define VMX_EPT_PAGE_WALK_4_BIT (1ull << 6)
484 #define VMX_EPT_PAGE_WALK_5_BIT (1ull << 7)
485 #define VMX_EPTP_UC_BIT (1ull << 8)
486 #define VMX_EPTP_WB_BIT (1ull << 14)
487 #define VMX_EPT_2MB_PAGE_BIT (1ull << 16)
488 #define VMX_EPT_1GB_PAGE_BIT (1ull << 17)
489 #define VMX_EPT_INVEPT_BIT (1ull << 20)
490 #define VMX_EPT_AD_BIT (1ull << 21)
491 #define VMX_EPT_EXTENT_CONTEXT_BIT (1ull << 25)
492 #define VMX_EPT_EXTENT_GLOBAL_BIT (1ull << 26)
493
494 #define VMX_VPID_INVVPID_BIT (1ull << 0) /* (32 - 32) */
495 #define VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT (1ull << 8) /* (40 - 32) */
496 #define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT (1ull << 9) /* (41 - 32) */
497 #define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT (1ull << 10) /* (42 - 32) */
498 #define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT (1ull << 11) /* (43 - 32) */
499
500 #define VMX_EPT_MT_EPTE_SHIFT 3
501 #define VMX_EPTP_PWL_MASK 0x38ull
502 #define VMX_EPTP_PWL_4 0x18ull
503 #define VMX_EPTP_PWL_5 0x20ull
504 #define VMX_EPTP_AD_ENABLE_BIT (1ull << 6)
505 #define VMX_EPTP_MT_MASK 0x7ull
506 #define VMX_EPTP_MT_WB 0x6ull
507 #define VMX_EPTP_MT_UC 0x0ull
508 #define VMX_EPT_READABLE_MASK 0x1ull
509 #define VMX_EPT_WRITABLE_MASK 0x2ull
510 #define VMX_EPT_EXECUTABLE_MASK 0x4ull
511 #define VMX_EPT_IPAT_BIT (1ull << 6)
512 #define VMX_EPT_ACCESS_BIT (1ull << 8)
513 #define VMX_EPT_DIRTY_BIT (1ull << 9)
514 #define VMX_EPT_RWX_MASK (VMX_EPT_READABLE_MASK | \
515 VMX_EPT_WRITABLE_MASK | \
516 VMX_EPT_EXECUTABLE_MASK)
517 #define VMX_EPT_MT_MASK (7ull << VMX_EPT_MT_EPTE_SHIFT)
518
vmx_eptp_page_walk_level(u64 eptp)519 static inline u8 vmx_eptp_page_walk_level(u64 eptp)
520 {
521 u64 encoded_level = eptp & VMX_EPTP_PWL_MASK;
522
523 if (encoded_level == VMX_EPTP_PWL_5)
524 return 5;
525
526 /* @eptp must be pre-validated by the caller. */
527 WARN_ON_ONCE(encoded_level != VMX_EPTP_PWL_4);
528 return 4;
529 }
530
531 /* The mask to use to trigger an EPT Misconfiguration in order to track MMIO */
532 #define VMX_EPT_MISCONFIG_WX_VALUE (VMX_EPT_WRITABLE_MASK | \
533 VMX_EPT_EXECUTABLE_MASK)
534
535 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul
536
537 struct vmx_msr_entry {
538 u32 index;
539 u32 reserved;
540 u64 value;
541 } __aligned(16);
542
543 /*
544 * Exit Qualifications for entry failure during or after loading guest state
545 */
546 enum vm_entry_failure_code {
547 ENTRY_FAIL_DEFAULT = 0,
548 ENTRY_FAIL_PDPTE = 2,
549 ENTRY_FAIL_NMI = 3,
550 ENTRY_FAIL_VMCS_LINK_PTR = 4,
551 };
552
553 /*
554 * Exit Qualifications for EPT Violations
555 */
556 #define EPT_VIOLATION_ACC_READ_BIT 0
557 #define EPT_VIOLATION_ACC_WRITE_BIT 1
558 #define EPT_VIOLATION_ACC_INSTR_BIT 2
559 #define EPT_VIOLATION_RWX_SHIFT 3
560 #define EPT_VIOLATION_GVA_IS_VALID_BIT 7
561 #define EPT_VIOLATION_GVA_TRANSLATED_BIT 8
562 #define EPT_VIOLATION_ACC_READ (1 << EPT_VIOLATION_ACC_READ_BIT)
563 #define EPT_VIOLATION_ACC_WRITE (1 << EPT_VIOLATION_ACC_WRITE_BIT)
564 #define EPT_VIOLATION_ACC_INSTR (1 << EPT_VIOLATION_ACC_INSTR_BIT)
565 #define EPT_VIOLATION_RWX_MASK (VMX_EPT_RWX_MASK << EPT_VIOLATION_RWX_SHIFT)
566 #define EPT_VIOLATION_GVA_IS_VALID (1 << EPT_VIOLATION_GVA_IS_VALID_BIT)
567 #define EPT_VIOLATION_GVA_TRANSLATED (1 << EPT_VIOLATION_GVA_TRANSLATED_BIT)
568
569 /*
570 * Exit Qualifications for NOTIFY VM EXIT
571 */
572 #define NOTIFY_VM_CONTEXT_INVALID BIT(0)
573
574 /*
575 * VM-instruction error numbers
576 */
577 enum vm_instruction_error_number {
578 VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1,
579 VMXERR_VMCLEAR_INVALID_ADDRESS = 2,
580 VMXERR_VMCLEAR_VMXON_POINTER = 3,
581 VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4,
582 VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5,
583 VMXERR_VMRESUME_AFTER_VMXOFF = 6,
584 VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7,
585 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8,
586 VMXERR_VMPTRLD_INVALID_ADDRESS = 9,
587 VMXERR_VMPTRLD_VMXON_POINTER = 10,
588 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11,
589 VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12,
590 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13,
591 VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15,
592 VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16,
593 VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17,
594 VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18,
595 VMXERR_VMCALL_NONCLEAR_VMCS = 19,
596 VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20,
597 VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22,
598 VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23,
599 VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24,
600 VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25,
601 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26,
602 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28,
603 };
604
605 /*
606 * VM-instruction errors that can be encountered on VM-Enter, used to trace
607 * nested VM-Enter failures reported by hardware. Errors unique to VM-Enter
608 * from a SMI Transfer Monitor are not included as things have gone seriously
609 * sideways if we get one of those...
610 */
611 #define VMX_VMENTER_INSTRUCTION_ERRORS \
612 { VMXERR_VMLAUNCH_NONCLEAR_VMCS, "VMLAUNCH_NONCLEAR_VMCS" }, \
613 { VMXERR_VMRESUME_NONLAUNCHED_VMCS, "VMRESUME_NONLAUNCHED_VMCS" }, \
614 { VMXERR_VMRESUME_AFTER_VMXOFF, "VMRESUME_AFTER_VMXOFF" }, \
615 { VMXERR_ENTRY_INVALID_CONTROL_FIELD, "VMENTRY_INVALID_CONTROL_FIELD" }, \
616 { VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, "VMENTRY_INVALID_HOST_STATE_FIELD" }, \
617 { VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, "VMENTRY_EVENTS_BLOCKED_BY_MOV_SS" }
618
619 enum vmx_l1d_flush_state {
620 VMENTER_L1D_FLUSH_AUTO,
621 VMENTER_L1D_FLUSH_NEVER,
622 VMENTER_L1D_FLUSH_COND,
623 VMENTER_L1D_FLUSH_ALWAYS,
624 VMENTER_L1D_FLUSH_EPT_DISABLED,
625 VMENTER_L1D_FLUSH_NOT_REQUIRED,
626 };
627
628 extern enum vmx_l1d_flush_state l1tf_vmx_mitigation;
629
630 #endif
631