1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __KVM_X86_VMX_VMCS_H
3 #define __KVM_X86_VMX_VMCS_H
4 
5 #include <linux/ktime.h>
6 #include <linux/list.h>
7 #include <linux/nospec.h>
8 
9 #include <asm/kvm.h>
10 #include <asm/vmx.h>
11 
12 #include "capabilities.h"
13 
14 #define ROL16(val, n) ((u16)(((u16)(val) << (n)) | ((u16)(val) >> (16 - (n)))))
15 
16 struct vmcs_hdr {
17 	u32 revision_id:31;
18 	u32 shadow_vmcs:1;
19 };
20 
21 struct vmcs {
22 	struct vmcs_hdr hdr;
23 	u32 abort;
24 	char data[];
25 };
26 
27 DECLARE_PER_CPU(struct vmcs *, current_vmcs);
28 
29 /*
30  * vmcs_host_state tracks registers that are loaded from the VMCS on VMEXIT
31  * and whose values change infrequently, but are not constant.  I.e. this is
32  * used as a write-through cache of the corresponding VMCS fields.
33  */
34 struct vmcs_host_state {
35 	unsigned long cr3;	/* May not match real cr3 */
36 	unsigned long cr4;	/* May not match real cr4 */
37 	unsigned long gs_base;
38 	unsigned long fs_base;
39 	unsigned long rsp;
40 
41 	u16           fs_sel, gs_sel, ldt_sel;
42 #ifdef CONFIG_X86_64
43 	u16           ds_sel, es_sel;
44 #endif
45 };
46 
47 struct vmcs_controls_shadow {
48 	u32 vm_entry;
49 	u32 vm_exit;
50 	u32 pin;
51 	u32 exec;
52 	u32 secondary_exec;
53 };
54 
55 /*
56  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
57  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
58  * loaded on this CPU (so we can clear them if the CPU goes down).
59  */
60 struct loaded_vmcs {
61 	struct vmcs *vmcs;
62 	struct vmcs *shadow_vmcs;
63 	int cpu;
64 	bool launched;
65 	bool nmi_known_unmasked;
66 	bool hv_timer_soft_disabled;
67 	/* Support for vnmi-less CPUs */
68 	int soft_vnmi_blocked;
69 	ktime_t entry_time;
70 	s64 vnmi_blocked_time;
71 	unsigned long *msr_bitmap;
72 	struct list_head loaded_vmcss_on_cpu_link;
73 	struct vmcs_host_state host_state;
74 	struct vmcs_controls_shadow controls_shadow;
75 };
76 
is_intr_type(u32 intr_info,u32 type)77 static inline bool is_intr_type(u32 intr_info, u32 type)
78 {
79 	const u32 mask = INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK;
80 
81 	return (intr_info & mask) == (INTR_INFO_VALID_MASK | type);
82 }
83 
is_intr_type_n(u32 intr_info,u32 type,u8 vector)84 static inline bool is_intr_type_n(u32 intr_info, u32 type, u8 vector)
85 {
86 	const u32 mask = INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK |
87 			 INTR_INFO_VECTOR_MASK;
88 
89 	return (intr_info & mask) == (INTR_INFO_VALID_MASK | type | vector);
90 }
91 
is_exception_n(u32 intr_info,u8 vector)92 static inline bool is_exception_n(u32 intr_info, u8 vector)
93 {
94 	return is_intr_type_n(intr_info, INTR_TYPE_HARD_EXCEPTION, vector);
95 }
96 
is_debug(u32 intr_info)97 static inline bool is_debug(u32 intr_info)
98 {
99 	return is_exception_n(intr_info, DB_VECTOR);
100 }
101 
is_breakpoint(u32 intr_info)102 static inline bool is_breakpoint(u32 intr_info)
103 {
104 	return is_exception_n(intr_info, BP_VECTOR);
105 }
106 
is_double_fault(u32 intr_info)107 static inline bool is_double_fault(u32 intr_info)
108 {
109 	return is_exception_n(intr_info, DF_VECTOR);
110 }
111 
is_page_fault(u32 intr_info)112 static inline bool is_page_fault(u32 intr_info)
113 {
114 	return is_exception_n(intr_info, PF_VECTOR);
115 }
116 
is_invalid_opcode(u32 intr_info)117 static inline bool is_invalid_opcode(u32 intr_info)
118 {
119 	return is_exception_n(intr_info, UD_VECTOR);
120 }
121 
is_gp_fault(u32 intr_info)122 static inline bool is_gp_fault(u32 intr_info)
123 {
124 	return is_exception_n(intr_info, GP_VECTOR);
125 }
126 
is_alignment_check(u32 intr_info)127 static inline bool is_alignment_check(u32 intr_info)
128 {
129 	return is_exception_n(intr_info, AC_VECTOR);
130 }
131 
is_machine_check(u32 intr_info)132 static inline bool is_machine_check(u32 intr_info)
133 {
134 	return is_exception_n(intr_info, MC_VECTOR);
135 }
136 
is_nm_fault(u32 intr_info)137 static inline bool is_nm_fault(u32 intr_info)
138 {
139 	return is_exception_n(intr_info, NM_VECTOR);
140 }
141 
142 /* Undocumented: icebp/int1 */
is_icebp(u32 intr_info)143 static inline bool is_icebp(u32 intr_info)
144 {
145 	return is_intr_type(intr_info, INTR_TYPE_PRIV_SW_EXCEPTION);
146 }
147 
is_nmi(u32 intr_info)148 static inline bool is_nmi(u32 intr_info)
149 {
150 	return is_intr_type(intr_info, INTR_TYPE_NMI_INTR);
151 }
152 
is_external_intr(u32 intr_info)153 static inline bool is_external_intr(u32 intr_info)
154 {
155 	return is_intr_type(intr_info, INTR_TYPE_EXT_INTR);
156 }
157 
is_exception_with_error_code(u32 intr_info)158 static inline bool is_exception_with_error_code(u32 intr_info)
159 {
160 	const u32 mask = INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK;
161 
162 	return (intr_info & mask) == mask;
163 }
164 
165 enum vmcs_field_width {
166 	VMCS_FIELD_WIDTH_U16 = 0,
167 	VMCS_FIELD_WIDTH_U64 = 1,
168 	VMCS_FIELD_WIDTH_U32 = 2,
169 	VMCS_FIELD_WIDTH_NATURAL_WIDTH = 3
170 };
171 
vmcs_field_width(unsigned long field)172 static inline int vmcs_field_width(unsigned long field)
173 {
174 	if (0x1 & field)	/* the *_HIGH fields are all 32 bit */
175 		return VMCS_FIELD_WIDTH_U32;
176 	return (field >> 13) & 0x3;
177 }
178 
vmcs_field_readonly(unsigned long field)179 static inline int vmcs_field_readonly(unsigned long field)
180 {
181 	return (((field >> 10) & 0x3) == 1);
182 }
183 
184 #define VMCS_FIELD_INDEX_SHIFT		(1)
185 #define VMCS_FIELD_INDEX_MASK		GENMASK(9, 1)
186 
vmcs_field_index(unsigned long field)187 static inline unsigned int vmcs_field_index(unsigned long field)
188 {
189 	return (field & VMCS_FIELD_INDEX_MASK) >> VMCS_FIELD_INDEX_SHIFT;
190 }
191 
192 #endif /* __KVM_X86_VMX_VMCS_H */
193