1 /*
2 * linux/include/video/vga.h -- standard VGA chipset interaction
3 *
4 * Copyright 1999 Jeff Garzik <jgarzik@pobox.com>
5 *
6 * Copyright history from vga16fb.c:
7 * Copyright 1999 Ben Pfaff and Petr Vandrovec
8 * Based on VGA info at http://www.goodnet.com/~tinara/FreeVGA/home.htm
9 * Based on VESA framebuffer (c) 1998 Gerd Knorr
10 *
11 * This file is subject to the terms and conditions of the GNU General
12 * Public License. See the file COPYING in the main directory of this
13 * archive for more details.
14 *
15 */
16
17 #ifndef __linux_video_vga_h__
18 #define __linux_video_vga_h__
19
20 #include <linux/config.h>
21 #include <linux/types.h>
22 #include <asm/io.h>
23 #ifndef CONFIG_AMIGA
24 #include <asm/vga.h>
25 #else
26 /*
27 * FIXME
28 * Ugh, we don't have PCI space, so map readb() and friends to use Zorro space
29 * for MMIO accesses. This should make clgenfb work again on Amiga
30 */
31 #define inb(port) 0
32 #define inw(port) 0
33 #define outb(port, val) do { } while (0)
34 #define outw(port, val) do { } while (0)
35 #define readb z_readb
36 #define writeb z_writeb
37 #define writew z_writew
38 #endif
39 #include <asm/byteorder.h>
40
41
42 /* Some of the code below is taken from SVGAlib. The original,
43 unmodified copyright notice for that code is below. */
44 /* VGAlib version 1.2 - (c) 1993 Tommy Frandsen */
45 /* */
46 /* This library is free software; you can redistribute it and/or */
47 /* modify it without any restrictions. This library is distributed */
48 /* in the hope that it will be useful, but without any warranty. */
49
50 /* Multi-chipset support Copyright 1993 Harm Hanemaayer */
51 /* partially copyrighted (C) 1993 by Hartmut Schirmer */
52
53 /* VGA data register ports */
54 #define VGA_CRT_DC 0x3D5 /* CRT Controller Data Register - color emulation */
55 #define VGA_CRT_DM 0x3B5 /* CRT Controller Data Register - mono emulation */
56 #define VGA_ATT_R 0x3C1 /* Attribute Controller Data Read Register */
57 #define VGA_ATT_W 0x3C0 /* Attribute Controller Data Write Register */
58 #define VGA_GFX_D 0x3CF /* Graphics Controller Data Register */
59 #define VGA_SEQ_D 0x3C5 /* Sequencer Data Register */
60 #define VGA_MIS_R 0x3CC /* Misc Output Read Register */
61 #define VGA_MIS_W 0x3C2 /* Misc Output Write Register */
62 #define VGA_FTC_R 0x3CA /* Feature Control Read Register */
63 #define VGA_IS1_RC 0x3DA /* Input Status Register 1 - color emulation */
64 #define VGA_IS1_RM 0x3BA /* Input Status Register 1 - mono emulation */
65 #define VGA_PEL_D 0x3C9 /* PEL Data Register */
66 #define VGA_PEL_MSK 0x3C6 /* PEL mask register */
67
68 /* EGA-specific registers */
69 #define EGA_GFX_E0 0x3CC /* Graphics enable processor 0 */
70 #define EGA_GFX_E1 0x3CA /* Graphics enable processor 1 */
71
72 /* VGA index register ports */
73 #define VGA_CRT_IC 0x3D4 /* CRT Controller Index - color emulation */
74 #define VGA_CRT_IM 0x3B4 /* CRT Controller Index - mono emulation */
75 #define VGA_ATT_IW 0x3C0 /* Attribute Controller Index & Data Write Register */
76 #define VGA_GFX_I 0x3CE /* Graphics Controller Index */
77 #define VGA_SEQ_I 0x3C4 /* Sequencer Index */
78 #define VGA_PEL_IW 0x3C8 /* PEL Write Index */
79 #define VGA_PEL_IR 0x3C7 /* PEL Read Index */
80
81 /* standard VGA indexes max counts */
82 #define VGA_CRT_C 0x19 /* Number of CRT Controller Registers */
83 #define VGA_ATT_C 0x15 /* Number of Attribute Controller Registers */
84 #define VGA_GFX_C 0x09 /* Number of Graphics Controller Registers */
85 #define VGA_SEQ_C 0x05 /* Number of Sequencer Registers */
86 #define VGA_MIS_C 0x01 /* Number of Misc Output Register */
87
88 /* VGA misc register bit masks */
89 #define VGA_MIS_COLOR 0x01
90 #define VGA_MIS_ENB_MEM_ACCESS 0x02
91 #define VGA_MIS_DCLK_28322_720 0x04
92 #define VGA_MIS_ENB_PLL_LOAD (0x04 | 0x08)
93 #define VGA_MIS_SEL_HIGH_PAGE 0x20
94
95 /* VGA CRT controller register indices */
96 #define VGA_CRTC_H_TOTAL 0
97 #define VGA_CRTC_H_DISP 1
98 #define VGA_CRTC_H_BLANK_START 2
99 #define VGA_CRTC_H_BLANK_END 3
100 #define VGA_CRTC_H_SYNC_START 4
101 #define VGA_CRTC_H_SYNC_END 5
102 #define VGA_CRTC_V_TOTAL 6
103 #define VGA_CRTC_OVERFLOW 7
104 #define VGA_CRTC_PRESET_ROW 8
105 #define VGA_CRTC_MAX_SCAN 9
106 #define VGA_CRTC_CURSOR_START 0x0A
107 #define VGA_CRTC_CURSOR_END 0x0B
108 #define VGA_CRTC_START_HI 0x0C
109 #define VGA_CRTC_START_LO 0x0D
110 #define VGA_CRTC_CURSOR_HI 0x0E
111 #define VGA_CRTC_CURSOR_LO 0x0F
112 #define VGA_CRTC_V_SYNC_START 0x10
113 #define VGA_CRTC_V_SYNC_END 0x11
114 #define VGA_CRTC_V_DISP_END 0x12
115 #define VGA_CRTC_OFFSET 0x13
116 #define VGA_CRTC_UNDERLINE 0x14
117 #define VGA_CRTC_V_BLANK_START 0x15
118 #define VGA_CRTC_V_BLANK_END 0x16
119 #define VGA_CRTC_MODE 0x17
120 #define VGA_CRTC_LINE_COMPARE 0x18
121 #define VGA_CRTC_REGS VGA_CRT_C
122
123 /* VGA CRT controller bit masks */
124 #define VGA_CR11_LOCK_CR0_CR7 0x80 /* lock writes to CR0 - CR7 */
125 #define VGA_CR17_H_V_SIGNALS_ENABLED 0x80
126
127 /* VGA attribute controller register indices */
128 #define VGA_ATC_PALETTE0 0x00
129 #define VGA_ATC_PALETTE1 0x01
130 #define VGA_ATC_PALETTE2 0x02
131 #define VGA_ATC_PALETTE3 0x03
132 #define VGA_ATC_PALETTE4 0x04
133 #define VGA_ATC_PALETTE5 0x05
134 #define VGA_ATC_PALETTE6 0x06
135 #define VGA_ATC_PALETTE7 0x07
136 #define VGA_ATC_PALETTE8 0x08
137 #define VGA_ATC_PALETTE9 0x09
138 #define VGA_ATC_PALETTEA 0x0A
139 #define VGA_ATC_PALETTEB 0x0B
140 #define VGA_ATC_PALETTEC 0x0C
141 #define VGA_ATC_PALETTED 0x0D
142 #define VGA_ATC_PALETTEE 0x0E
143 #define VGA_ATC_PALETTEF 0x0F
144 #define VGA_ATC_MODE 0x10
145 #define VGA_ATC_OVERSCAN 0x11
146 #define VGA_ATC_PLANE_ENABLE 0x12
147 #define VGA_ATC_PEL 0x13
148 #define VGA_ATC_COLOR_PAGE 0x14
149
150 #define VGA_AR_ENABLE_DISPLAY 0x20
151
152 /* VGA sequencer register indices */
153 #define VGA_SEQ_RESET 0x00
154 #define VGA_SEQ_CLOCK_MODE 0x01
155 #define VGA_SEQ_PLANE_WRITE 0x02
156 #define VGA_SEQ_CHARACTER_MAP 0x03
157 #define VGA_SEQ_MEMORY_MODE 0x04
158
159 /* VGA sequencer register bit masks */
160 #define VGA_SR01_CHAR_CLK_8DOTS 0x01 /* bit 0: character clocks 8 dots wide are generated */
161 #define VGA_SR01_SCREEN_OFF 0x20 /* bit 5: Screen is off */
162 #define VGA_SR02_ALL_PLANES 0x0F /* bits 3-0: enable access to all planes */
163 #define VGA_SR04_EXT_MEM 0x02 /* bit 1: allows complete mem access to 256K */
164 #define VGA_SR04_SEQ_MODE 0x04 /* bit 2: directs system to use a sequential addressing mode */
165 #define VGA_SR04_CHN_4M 0x08 /* bit 3: selects modulo 4 addressing for CPU access to display memory */
166
167 /* VGA graphics controller register indices */
168 #define VGA_GFX_SR_VALUE 0x00
169 #define VGA_GFX_SR_ENABLE 0x01
170 #define VGA_GFX_COMPARE_VALUE 0x02
171 #define VGA_GFX_DATA_ROTATE 0x03
172 #define VGA_GFX_PLANE_READ 0x04
173 #define VGA_GFX_MODE 0x05
174 #define VGA_GFX_MISC 0x06
175 #define VGA_GFX_COMPARE_MASK 0x07
176 #define VGA_GFX_BIT_MASK 0x08
177
178 /* VGA graphics controller bit masks */
179 #define VGA_GR06_GRAPHICS_MODE 0x01
180
181 /* macro for composing an 8-bit VGA register index and value
182 * into a single 16-bit quantity */
183 #define VGA_OUT16VAL(v, r) (((v) << 8) | (r))
184
185 /* decide whether we should enable the faster 16-bit VGA register writes */
186 #ifdef __LITTLE_ENDIAN
187 #define VGA_OUTW_WRITE
188 #endif
189
190
191 /*
192 * generic VGA port read/write
193 */
194
vga_io_r(unsigned short port)195 static inline unsigned char vga_io_r (unsigned short port)
196 {
197 return inb (port);
198 }
199
vga_io_w(unsigned short port,unsigned char val)200 static inline void vga_io_w (unsigned short port, unsigned char val)
201 {
202 outb (val, port);
203 }
204
vga_io_w_fast(unsigned short port,unsigned char reg,unsigned char val)205 static inline void vga_io_w_fast (unsigned short port, unsigned char reg,
206 unsigned char val)
207 {
208 outw (VGA_OUT16VAL (val, reg), port);
209 }
210
vga_mm_r(caddr_t regbase,unsigned short port)211 static inline unsigned char vga_mm_r (caddr_t regbase, unsigned short port)
212 {
213 return readb (regbase + port);
214 }
215
vga_mm_w(caddr_t regbase,unsigned short port,unsigned char val)216 static inline void vga_mm_w (caddr_t regbase, unsigned short port, unsigned char val)
217 {
218 writeb (val, regbase + port);
219 }
220
vga_mm_w_fast(caddr_t regbase,unsigned short port,unsigned char reg,unsigned char val)221 static inline void vga_mm_w_fast (caddr_t regbase, unsigned short port,
222 unsigned char reg, unsigned char val)
223 {
224 writew (VGA_OUT16VAL (val, reg), regbase + port);
225 }
226
vga_r(caddr_t regbase,unsigned short port)227 static inline unsigned char vga_r (caddr_t regbase, unsigned short port)
228 {
229 if (regbase)
230 return vga_mm_r (regbase, port);
231 else
232 return vga_io_r (port);
233 }
234
vga_w(caddr_t regbase,unsigned short port,unsigned char val)235 static inline void vga_w (caddr_t regbase, unsigned short port, unsigned char val)
236 {
237 if (regbase)
238 vga_mm_w (regbase, port, val);
239 else
240 vga_io_w (port, val);
241 }
242
243
vga_w_fast(caddr_t regbase,unsigned short port,unsigned char reg,unsigned char val)244 static inline void vga_w_fast (caddr_t regbase, unsigned short port,
245 unsigned char reg, unsigned char val)
246 {
247 if (regbase)
248 vga_mm_w_fast (regbase, port, reg, val);
249 else
250 vga_io_w_fast (port, reg, val);
251 }
252
253
254 /*
255 * VGA CRTC register read/write
256 */
257
vga_rcrt(caddr_t regbase,unsigned char reg)258 static inline unsigned char vga_rcrt (caddr_t regbase, unsigned char reg)
259 {
260 vga_w (regbase, VGA_CRT_IC, reg);
261 return vga_r (regbase, VGA_CRT_DC);
262 }
263
vga_wcrt(caddr_t regbase,unsigned char reg,unsigned char val)264 static inline void vga_wcrt (caddr_t regbase, unsigned char reg, unsigned char val)
265 {
266 #ifdef VGA_OUTW_WRITE
267 vga_w_fast (regbase, VGA_CRT_IC, reg, val);
268 #else
269 vga_w (regbase, VGA_CRT_IC, reg);
270 vga_w (regbase, VGA_CRT_DC, val);
271 #endif /* VGA_OUTW_WRITE */
272 }
273
vga_io_rcrt(unsigned char reg)274 static inline unsigned char vga_io_rcrt (unsigned char reg)
275 {
276 vga_io_w (VGA_CRT_IC, reg);
277 return vga_io_r (VGA_CRT_DC);
278 }
279
vga_io_wcrt(unsigned char reg,unsigned char val)280 static inline void vga_io_wcrt (unsigned char reg, unsigned char val)
281 {
282 #ifdef VGA_OUTW_WRITE
283 vga_io_w_fast (VGA_CRT_IC, reg, val);
284 #else
285 vga_io_w (VGA_CRT_IC, reg);
286 vga_io_w (VGA_CRT_DC, val);
287 #endif /* VGA_OUTW_WRITE */
288 }
289
vga_mm_rcrt(caddr_t regbase,unsigned char reg)290 static inline unsigned char vga_mm_rcrt (caddr_t regbase, unsigned char reg)
291 {
292 vga_mm_w (regbase, VGA_CRT_IC, reg);
293 return vga_mm_r (regbase, VGA_CRT_DC);
294 }
295
vga_mm_wcrt(caddr_t regbase,unsigned char reg,unsigned char val)296 static inline void vga_mm_wcrt (caddr_t regbase, unsigned char reg, unsigned char val)
297 {
298 #ifdef VGA_OUTW_WRITE
299 vga_mm_w_fast (regbase, VGA_CRT_IC, reg, val);
300 #else
301 vga_mm_w (regbase, VGA_CRT_IC, reg);
302 vga_mm_w (regbase, VGA_CRT_DC, val);
303 #endif /* VGA_OUTW_WRITE */
304 }
305
306
307 /*
308 * VGA sequencer register read/write
309 */
310
vga_rseq(caddr_t regbase,unsigned char reg)311 static inline unsigned char vga_rseq (caddr_t regbase, unsigned char reg)
312 {
313 vga_w (regbase, VGA_SEQ_I, reg);
314 return vga_r (regbase, VGA_SEQ_D);
315 }
316
vga_wseq(caddr_t regbase,unsigned char reg,unsigned char val)317 static inline void vga_wseq (caddr_t regbase, unsigned char reg, unsigned char val)
318 {
319 #ifdef VGA_OUTW_WRITE
320 vga_w_fast (regbase, VGA_SEQ_I, reg, val);
321 #else
322 vga_w (regbase, VGA_SEQ_I, reg);
323 vga_w (regbase, VGA_SEQ_D, val);
324 #endif /* VGA_OUTW_WRITE */
325 }
326
vga_io_rseq(unsigned char reg)327 static inline unsigned char vga_io_rseq (unsigned char reg)
328 {
329 vga_io_w (VGA_SEQ_I, reg);
330 return vga_io_r (VGA_SEQ_D);
331 }
332
vga_io_wseq(unsigned char reg,unsigned char val)333 static inline void vga_io_wseq (unsigned char reg, unsigned char val)
334 {
335 #ifdef VGA_OUTW_WRITE
336 vga_io_w_fast (VGA_SEQ_I, reg, val);
337 #else
338 vga_io_w (VGA_SEQ_I, reg);
339 vga_io_w (VGA_SEQ_D, val);
340 #endif /* VGA_OUTW_WRITE */
341 }
342
vga_mm_rseq(caddr_t regbase,unsigned char reg)343 static inline unsigned char vga_mm_rseq (caddr_t regbase, unsigned char reg)
344 {
345 vga_mm_w (regbase, VGA_SEQ_I, reg);
346 return vga_mm_r (regbase, VGA_SEQ_D);
347 }
348
vga_mm_wseq(caddr_t regbase,unsigned char reg,unsigned char val)349 static inline void vga_mm_wseq (caddr_t regbase, unsigned char reg, unsigned char val)
350 {
351 #ifdef VGA_OUTW_WRITE
352 vga_mm_w_fast (regbase, VGA_SEQ_I, reg, val);
353 #else
354 vga_mm_w (regbase, VGA_SEQ_I, reg);
355 vga_mm_w (regbase, VGA_SEQ_D, val);
356 #endif /* VGA_OUTW_WRITE */
357 }
358
359
360
361 /*
362 * VGA graphics controller register read/write
363 */
364
vga_rgfx(caddr_t regbase,unsigned char reg)365 static inline unsigned char vga_rgfx (caddr_t regbase, unsigned char reg)
366 {
367 vga_w (regbase, VGA_GFX_I, reg);
368 return vga_r (regbase, VGA_GFX_D);
369 }
370
vga_wgfx(caddr_t regbase,unsigned char reg,unsigned char val)371 static inline void vga_wgfx (caddr_t regbase, unsigned char reg, unsigned char val)
372 {
373 #ifdef VGA_OUTW_WRITE
374 vga_w_fast (regbase, VGA_GFX_I, reg, val);
375 #else
376 vga_w (regbase, VGA_GFX_I, reg);
377 vga_w (regbase, VGA_GFX_D, val);
378 #endif /* VGA_OUTW_WRITE */
379 }
380
vga_io_rgfx(unsigned char reg)381 static inline unsigned char vga_io_rgfx (unsigned char reg)
382 {
383 vga_io_w (VGA_GFX_I, reg);
384 return vga_io_r (VGA_GFX_D);
385 }
386
vga_io_wgfx(unsigned char reg,unsigned char val)387 static inline void vga_io_wgfx (unsigned char reg, unsigned char val)
388 {
389 #ifdef VGA_OUTW_WRITE
390 vga_io_w_fast (VGA_GFX_I, reg, val);
391 #else
392 vga_io_w (VGA_GFX_I, reg);
393 vga_io_w (VGA_GFX_D, val);
394 #endif /* VGA_OUTW_WRITE */
395 }
396
vga_mm_rgfx(caddr_t regbase,unsigned char reg)397 static inline unsigned char vga_mm_rgfx (caddr_t regbase, unsigned char reg)
398 {
399 vga_mm_w (regbase, VGA_GFX_I, reg);
400 return vga_mm_r (regbase, VGA_GFX_D);
401 }
402
vga_mm_wgfx(caddr_t regbase,unsigned char reg,unsigned char val)403 static inline void vga_mm_wgfx (caddr_t regbase, unsigned char reg, unsigned char val)
404 {
405 #ifdef VGA_OUTW_WRITE
406 vga_mm_w_fast (regbase, VGA_GFX_I, reg, val);
407 #else
408 vga_mm_w (regbase, VGA_GFX_I, reg);
409 vga_mm_w (regbase, VGA_GFX_D, val);
410 #endif /* VGA_OUTW_WRITE */
411 }
412
413
414 /*
415 * VGA attribute controller register read/write
416 */
417
vga_rattr(caddr_t regbase,unsigned char reg)418 static inline unsigned char vga_rattr (caddr_t regbase, unsigned char reg)
419 {
420 vga_w (regbase, VGA_ATT_IW, reg);
421 return vga_r (regbase, VGA_ATT_R);
422 }
423
vga_wattr(caddr_t regbase,unsigned char reg,unsigned char val)424 static inline void vga_wattr (caddr_t regbase, unsigned char reg, unsigned char val)
425 {
426 vga_w (regbase, VGA_ATT_IW, reg);
427 vga_w (regbase, VGA_ATT_W, val);
428 }
429
vga_io_rattr(unsigned char reg)430 static inline unsigned char vga_io_rattr (unsigned char reg)
431 {
432 vga_io_w (VGA_ATT_IW, reg);
433 return vga_io_r (VGA_ATT_R);
434 }
435
vga_io_wattr(unsigned char reg,unsigned char val)436 static inline void vga_io_wattr (unsigned char reg, unsigned char val)
437 {
438 vga_io_w (VGA_ATT_IW, reg);
439 vga_io_w (VGA_ATT_W, val);
440 }
441
vga_mm_rattr(caddr_t regbase,unsigned char reg)442 static inline unsigned char vga_mm_rattr (caddr_t regbase, unsigned char reg)
443 {
444 vga_mm_w (regbase, VGA_ATT_IW, reg);
445 return vga_mm_r (regbase, VGA_ATT_R);
446 }
447
vga_mm_wattr(caddr_t regbase,unsigned char reg,unsigned char val)448 static inline void vga_mm_wattr (caddr_t regbase, unsigned char reg, unsigned char val)
449 {
450 vga_mm_w (regbase, VGA_ATT_IW, reg);
451 vga_mm_w (regbase, VGA_ATT_W, val);
452 }
453
454
455
456
457 #endif /* __linux_video_vga_h__ */
458