1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * These are the HEVC state controls for use with stateless HEVC
4  * codec drivers.
5  *
6  * It turns out that these structs are not stable yet and will undergo
7  * more changes. So keep them private until they are stable and ready to
8  * become part of the official public API.
9  */
10 
11 #ifndef _HEVC_CTRLS_H_
12 #define _HEVC_CTRLS_H_
13 
14 #include <linux/videodev2.h>
15 
16 /* The pixel format isn't stable at the moment and will likely be renamed. */
17 #define V4L2_PIX_FMT_HEVC_SLICE v4l2_fourcc('S', '2', '6', '5') /* HEVC parsed slices */
18 
19 #define V4L2_CID_MPEG_VIDEO_HEVC_SPS		(V4L2_CID_CODEC_BASE + 1008)
20 #define V4L2_CID_MPEG_VIDEO_HEVC_PPS		(V4L2_CID_CODEC_BASE + 1009)
21 #define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS	(V4L2_CID_CODEC_BASE + 1010)
22 #define V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX	(V4L2_CID_CODEC_BASE + 1011)
23 #define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS	(V4L2_CID_CODEC_BASE + 1012)
24 #define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE	(V4L2_CID_CODEC_BASE + 1015)
25 #define V4L2_CID_MPEG_VIDEO_HEVC_START_CODE	(V4L2_CID_CODEC_BASE + 1016)
26 
27 /* enum v4l2_ctrl_type type values */
28 #define V4L2_CTRL_TYPE_HEVC_SPS 0x0120
29 #define V4L2_CTRL_TYPE_HEVC_PPS 0x0121
30 #define V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS 0x0122
31 #define V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX 0x0123
32 #define V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS 0x0124
33 
34 enum v4l2_mpeg_video_hevc_decode_mode {
35 	V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED,
36 	V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED,
37 };
38 
39 enum v4l2_mpeg_video_hevc_start_code {
40 	V4L2_MPEG_VIDEO_HEVC_START_CODE_NONE,
41 	V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B,
42 };
43 
44 #define V4L2_HEVC_SLICE_TYPE_B	0
45 #define V4L2_HEVC_SLICE_TYPE_P	1
46 #define V4L2_HEVC_SLICE_TYPE_I	2
47 
48 #define V4L2_HEVC_SPS_FLAG_SEPARATE_COLOUR_PLANE		(1ULL << 0)
49 #define V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED			(1ULL << 1)
50 #define V4L2_HEVC_SPS_FLAG_AMP_ENABLED				(1ULL << 2)
51 #define V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET		(1ULL << 3)
52 #define V4L2_HEVC_SPS_FLAG_PCM_ENABLED				(1ULL << 4)
53 #define V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED		(1ULL << 5)
54 #define V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT		(1ULL << 6)
55 #define V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED		(1ULL << 7)
56 #define V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED	(1ULL << 8)
57 
58 /* The controls are not stable at the moment and will likely be reworked. */
59 struct v4l2_ctrl_hevc_sps {
60 	/* ISO/IEC 23008-2, ITU-T Rec. H.265: Sequence parameter set */
61 	__u16	pic_width_in_luma_samples;
62 	__u16	pic_height_in_luma_samples;
63 	__u8	bit_depth_luma_minus8;
64 	__u8	bit_depth_chroma_minus8;
65 	__u8	log2_max_pic_order_cnt_lsb_minus4;
66 	__u8	sps_max_dec_pic_buffering_minus1;
67 	__u8	sps_max_num_reorder_pics;
68 	__u8	sps_max_latency_increase_plus1;
69 	__u8	log2_min_luma_coding_block_size_minus3;
70 	__u8	log2_diff_max_min_luma_coding_block_size;
71 	__u8	log2_min_luma_transform_block_size_minus2;
72 	__u8	log2_diff_max_min_luma_transform_block_size;
73 	__u8	max_transform_hierarchy_depth_inter;
74 	__u8	max_transform_hierarchy_depth_intra;
75 	__u8	pcm_sample_bit_depth_luma_minus1;
76 	__u8	pcm_sample_bit_depth_chroma_minus1;
77 	__u8	log2_min_pcm_luma_coding_block_size_minus3;
78 	__u8	log2_diff_max_min_pcm_luma_coding_block_size;
79 	__u8	num_short_term_ref_pic_sets;
80 	__u8	num_long_term_ref_pics_sps;
81 	__u8	chroma_format_idc;
82 	__u8	sps_max_sub_layers_minus1;
83 
84 	__u64	flags;
85 };
86 
87 #define V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED	(1ULL << 0)
88 #define V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT			(1ULL << 1)
89 #define V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED		(1ULL << 2)
90 #define V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT			(1ULL << 3)
91 #define V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED		(1ULL << 4)
92 #define V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED		(1ULL << 5)
93 #define V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED			(1ULL << 6)
94 #define V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT	(1ULL << 7)
95 #define V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED			(1ULL << 8)
96 #define V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED			(1ULL << 9)
97 #define V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED		(1ULL << 10)
98 #define V4L2_HEVC_PPS_FLAG_TILES_ENABLED			(1ULL << 11)
99 #define V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED		(1ULL << 12)
100 #define V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED	(1ULL << 13)
101 #define V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED (1ULL << 14)
102 #define V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED	(1ULL << 15)
103 #define V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER	(1ULL << 16)
104 #define V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT		(1ULL << 17)
105 #define V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT (1ULL << 18)
106 #define V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT	(1ULL << 19)
107 #define V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING			(1ULL << 20)
108 
109 struct v4l2_ctrl_hevc_pps {
110 	/* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture parameter set */
111 	__u8	num_extra_slice_header_bits;
112 	__u8	num_ref_idx_l0_default_active_minus1;
113 	__u8	num_ref_idx_l1_default_active_minus1;
114 	__s8	init_qp_minus26;
115 	__u8	diff_cu_qp_delta_depth;
116 	__s8	pps_cb_qp_offset;
117 	__s8	pps_cr_qp_offset;
118 	__u8	num_tile_columns_minus1;
119 	__u8	num_tile_rows_minus1;
120 	__u8	column_width_minus1[20];
121 	__u8	row_height_minus1[22];
122 	__s8	pps_beta_offset_div2;
123 	__s8	pps_tc_offset_div2;
124 	__u8	log2_parallel_merge_level_minus2;
125 
126 	__u8	padding[4];
127 	__u64	flags;
128 };
129 
130 #define V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE	0x01
131 
132 #define V4L2_HEVC_DPB_ENTRIES_NUM_MAX		16
133 
134 struct v4l2_hevc_dpb_entry {
135 	__u64	timestamp;
136 	__u8	flags;
137 	__u8	field_pic;
138 	__s32	pic_order_cnt_val;
139 	__u8	padding[2];
140 };
141 
142 struct v4l2_hevc_pred_weight_table {
143 	__s8	delta_luma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
144 	__s8	luma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
145 	__s8	delta_chroma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];
146 	__s8	chroma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];
147 
148 	__s8	delta_luma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
149 	__s8	luma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
150 	__s8	delta_chroma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];
151 	__s8	chroma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];
152 
153 	__u8	padding[6];
154 
155 	__u8	luma_log2_weight_denom;
156 	__s8	delta_chroma_log2_weight_denom;
157 };
158 
159 #define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_LUMA		(1ULL << 0)
160 #define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_CHROMA		(1ULL << 1)
161 #define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_TEMPORAL_MVP_ENABLED	(1ULL << 2)
162 #define V4L2_HEVC_SLICE_PARAMS_FLAG_MVD_L1_ZERO			(1ULL << 3)
163 #define V4L2_HEVC_SLICE_PARAMS_FLAG_CABAC_INIT			(1ULL << 4)
164 #define V4L2_HEVC_SLICE_PARAMS_FLAG_COLLOCATED_FROM_L0		(1ULL << 5)
165 #define V4L2_HEVC_SLICE_PARAMS_FLAG_USE_INTEGER_MV		(1ULL << 6)
166 #define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED (1ULL << 7)
167 #define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED (1ULL << 8)
168 #define V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT	(1ULL << 9)
169 
170 struct v4l2_ctrl_hevc_slice_params {
171 	__u32	bit_size;
172 	__u32	data_bit_offset;
173 
174 	/* ISO/IEC 23008-2, ITU-T Rec. H.265: NAL unit header */
175 	__u8	nal_unit_type;
176 	__u8	nuh_temporal_id_plus1;
177 
178 	/* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */
179 	__u8	slice_type;
180 	__u8	colour_plane_id;
181 	__s32	slice_pic_order_cnt;
182 	__u8	num_ref_idx_l0_active_minus1;
183 	__u8	num_ref_idx_l1_active_minus1;
184 	__u8	collocated_ref_idx;
185 	__u8	five_minus_max_num_merge_cand;
186 	__s8	slice_qp_delta;
187 	__s8	slice_cb_qp_offset;
188 	__s8	slice_cr_qp_offset;
189 	__s8	slice_act_y_qp_offset;
190 	__s8	slice_act_cb_qp_offset;
191 	__s8	slice_act_cr_qp_offset;
192 	__s8	slice_beta_offset_div2;
193 	__s8	slice_tc_offset_div2;
194 
195 	/* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture timing SEI message */
196 	__u8	pic_struct;
197 
198 	/* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */
199 	__u32	slice_segment_addr;
200 	__u8	ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
201 	__u8	ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
202 
203 	__u8	padding;
204 
205 	/* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */
206 	struct v4l2_hevc_pred_weight_table pred_weight_table;
207 
208 	__u64	flags;
209 };
210 
211 #define V4L2_HEVC_DECODE_PARAM_FLAG_IRAP_PIC		0x1
212 #define V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC		0x2
213 #define V4L2_HEVC_DECODE_PARAM_FLAG_NO_OUTPUT_OF_PRIOR  0x4
214 
215 struct v4l2_ctrl_hevc_decode_params {
216 	__s32	pic_order_cnt_val;
217 	__u8	num_active_dpb_entries;
218 	struct	v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
219 	__u8	num_poc_st_curr_before;
220 	__u8	num_poc_st_curr_after;
221 	__u8	num_poc_lt_curr;
222 	__u8	poc_st_curr_before[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
223 	__u8	poc_st_curr_after[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
224 	__u8	poc_lt_curr[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
225 	__u64	flags;
226 };
227 
228 struct v4l2_ctrl_hevc_scaling_matrix {
229 	__u8	scaling_list_4x4[6][16];
230 	__u8	scaling_list_8x8[6][64];
231 	__u8	scaling_list_16x16[6][64];
232 	__u8	scaling_list_32x32[2][64];
233 	__u8	scaling_list_dc_coef_16x16[6];
234 	__u8	scaling_list_dc_coef_32x32[2];
235 };
236 
237 /*  MPEG-class control IDs specific to the Hantro driver as defined by V4L2 */
238 #define V4L2_CID_CODEC_HANTRO_BASE				(V4L2_CTRL_CLASS_CODEC | 0x1200)
239 /*
240  * V4L2_CID_HANTRO_HEVC_SLICE_HEADER_SKIP -
241  * the number of data (in bits) to skip in the
242  * slice segment header.
243  * If non-IDR, the bits to be skipped go from syntax element "pic_output_flag"
244  * to before syntax element "slice_temporal_mvp_enabled_flag".
245  * If IDR, the skipped bits are just "pic_output_flag"
246  * (separate_colour_plane_flag is not supported).
247  */
248 #define V4L2_CID_HANTRO_HEVC_SLICE_HEADER_SKIP	(V4L2_CID_CODEC_HANTRO_BASE + 0)
249 
250 #endif
251