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Searched defs:UVD_MPC_SET_MUX__SET_1__SHIFT (Results 1 – 13 of 13) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/uvd/ !
Duvd_7_0_sh_mask.h635 #define UVD_MPC_SET_MUX__SET_1__SHIFT … macro
Duvd_3_1_sh_mask.h512 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 macro
Duvd_4_0_sh_mask.h531 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x00000003 macro
Duvd_4_2_sh_mask.h516 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 macro
Duvd_5_0_sh_mask.h548 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 macro
Duvd_6_0_sh_mask.h550 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 macro
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/vcn/ !
Dvcn_1_0_sh_mask.h1142 #define UVD_MPC_SET_MUX__SET_1__SHIFT … macro
Dvcn_2_5_sh_mask.h2883 #define UVD_MPC_SET_MUX__SET_1__SHIFT … macro
Dvcn_2_0_0_sh_mask.h2648 #define UVD_MPC_SET_MUX__SET_1__SHIFT … macro
Dvcn_2_6_0_sh_mask.h2875 #define UVD_MPC_SET_MUX__SET_1__SHIFT … macro
Dvcn_3_0_0_sh_mask.h3956 #define UVD_MPC_SET_MUX__SET_1__SHIFT … macro
Dvcn_4_0_0_sh_mask.h4206 #define UVD_MPC_SET_MUX__SET_1__SHIFT … macro
Dvcn_4_0_3_sh_mask.h4249 #define UVD_MPC_SET_MUX__SET_1__SHIFT … macro