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Searched defs:UVD_MPC_SET_MUXA0__VARA_2__SHIFT (Results 1 – 12 of 12) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h600 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT … macro
Duvd_3_1_sh_mask.h482 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc macro
Duvd_4_0_sh_mask.h501 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0x0000000c macro
Duvd_4_2_sh_mask.h486 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc macro
Duvd_5_0_sh_mask.h518 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc macro
Duvd_6_0_sh_mask.h520 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc macro
/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1107 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT … macro
Dvcn_2_5_sh_mask.h2848 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT … macro
Dvcn_2_0_0_sh_mask.h2613 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT … macro
Dvcn_2_6_0_sh_mask.h2840 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT … macro
Dvcn_3_0_0_sh_mask.h3921 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT … macro
Dvcn_4_0_0_sh_mask.h4171 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT … macro