1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2007 - 2011 Realtek Corporation. */
3 
4 #ifndef __RTL8188E_HAL_H__
5 #define __RTL8188E_HAL_H__
6 
7 /* include HAL Related header after HAL Related compiling flags */
8 #include "rtl8188e_spec.h"
9 #include "Hal8188EPhyReg.h"
10 #include "Hal8188EPhyCfg.h"
11 #include "rtl8188e_rf.h"
12 #include "rtl8188e_dm.h"
13 #include "rtl8188e_recv.h"
14 #include "rtl8188e_xmit.h"
15 #include "rtl8188e_cmd.h"
16 #include "rtw_efuse.h"
17 #include "odm_types.h"
18 #include "odm.h"
19 #include "odm_HWConfig.h"
20 #include "odm_RegDefine11N.h"
21 #include "HalPhyRf_8188e.h"
22 #include "Hal8188ERateAdaptive.h"
23 #include "HalHWImg8188E_MAC.h"
24 #include "HalHWImg8188E_RF.h"
25 #include "HalHWImg8188E_BB.h"
26 #include "odm_RTL8188E.h"
27 
28 #define DRVINFO_SZ	4 /*  unit is 8bytes */
29 #define PageNum_128(_Len)	(u32)(((_Len)>>7) + ((_Len) & 0x7F ? 1 : 0))
30 
31 #define DRIVER_EARLY_INT_TIME		0x05
32 #define BCN_DMA_ATIME_INT_TIME		0x02
33 
34 #define MAX_RX_DMA_BUFFER_SIZE_88E				\
35       0x2400 /* 9k for 88E nornal chip , MaxRxBuff=10k-max(TxReportSize(64*8),
36 	      * WOLPattern(16*24)) */
37 
38 #define TX_SELE_LQ			BIT(1)		/*  Low Queue */
39 #define TX_SELE_NQ			BIT(2)		/*  Normal Queue */
40 
41 /*  Note: We will divide number of page equally for each queue other
42  *  than public queue! */
43 /*  22k = 22528 bytes = 176 pages (@page =  128 bytes) */
44 /*  must reserved about 7 pages for LPS =>  176-7 = 169 (0xA9) */
45 /*  2*BCN / 1*ps-poll / 1*null-data /1*prob_rsp /1*QOS null-data /1*BT QOS
46  *  null-data */
47 
48 #define TX_TOTAL_PAGE_NUMBER_88E		0xA9/*   169 (21632=> 21k) */
49 
50 #define TX_PAGE_BOUNDARY_88E (TX_TOTAL_PAGE_NUMBER_88E + 1)
51 
52 #include "HalVerDef.h"
53 #include "hal_com.h"
54 
55 /* 	Channel Plan */
56 enum ChannelPlan {
57 	CHPL_FCC	= 0,
58 	CHPL_IC		= 1,
59 	CHPL_ETSI	= 2,
60 	CHPL_SPA	= 3,
61 	CHPL_FRANCE	= 4,
62 	CHPL_MKK	= 5,
63 	CHPL_MKK1	= 6,
64 	CHPL_ISRAEL	= 7,
65 	CHPL_TELEC	= 8,
66 	CHPL_GLOBAL	= 9,
67 	CHPL_WORLD	= 10,
68 };
69 
70 struct txpowerinfo24g {
71 	u8 IndexCCK_Base[RF_PATH_MAX][MAX_CHNL_GROUP_24G];
72 	u8 IndexBW40_Base[RF_PATH_MAX][MAX_CHNL_GROUP_24G];
73 	/* If only one tx, only BW20 and OFDM are used. */
74 	s8 CCK_Diff[RF_PATH_MAX][MAX_TX_COUNT];
75 	s8 OFDM_Diff[RF_PATH_MAX][MAX_TX_COUNT];
76 	s8 BW20_Diff[RF_PATH_MAX][MAX_TX_COUNT];
77 	s8 BW40_Diff[RF_PATH_MAX][MAX_TX_COUNT];
78 };
79 
80 #define EFUSE_REAL_CONTENT_LEN		512
81 #define AVAILABLE_EFUSE_ADDR(addr)	(addr < EFUSE_REAL_CONTENT_LEN)
82 
83 #define		EFUSE_REAL_CONTENT_LEN_88E	256
84 #define		EFUSE_MAP_LEN_88E		512
85 #define		EFUSE_MAX_SECTION_88E		64
86 /*  To prevent out of boundary programming case, leave 1byte and program
87  *  full section */
88 /*  9bytes + 1byt + 5bytes and pre 1byte. */
89 /*  For worst case: */
90 /*  | 2byte|----8bytes----|1byte|--7bytes--| 92D */
91 /*  PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte. */
92 #define		EFUSE_OOB_PROTECT_BYTES_88E	18
93 
94 #define EFUSE_PROTECT_BYTES_BANK	16
95 
96 #define USB_RXAGG_PAGE_COUNT	48
97 #define USB_RXAGG_PAGE_TIMEOUT	0x4
98 
99 struct hal_data_8188e {
100 	struct HAL_VERSION	VersionID;
101 	/* current WIFI_PHY values */
102 	enum ht_channel_width CurrentChannelBW;
103 	u8	CurrentChannel;
104 	u8	nCur40MhzPrimeSC;/*  Control channel sub-carrier */
105 
106 	u8	EEPROMRegulatory;
107 	u8	EEPROMThermalMeter;
108 
109 	u8	Index24G_CCK_Base[CHANNEL_MAX_NUMBER];
110 	u8	Index24G_BW40_Base[CHANNEL_MAX_NUMBER];
111 	/* If only one tx, only BW20 and OFDM are used. */
112 	s8	OFDM_24G_Diff[MAX_TX_COUNT];
113 	s8	BW20_24G_Diff[MAX_TX_COUNT];
114 
115 	/*  HT 20<->40 Pwr diff */
116 	u8	TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
117 	/*  For HT<->legacy pwr diff */
118 	u8	TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
119 	/*  For power group */
120 	u8	PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
121 	u8	PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
122 
123 	/*  Read/write are allow for following hardware information variables */
124 	u8	pwrGroupCnt;
125 	u32	MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16];
126 
127 	u8	CrystalCap;
128 
129 	u32	AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */
130 
131 	struct bb_reg_def PHYRegDef;
132 
133 	u32	RfRegChnlVal;
134 
135 	/* for host message to fw */
136 	u8	LastHMEBoxNum;
137 
138 	u8	fw_ractrl;
139 	u8	RegFwHwTxQCtrl;
140 	u8	RegReg542;
141 	u8	RegCR_1;
142 
143 	struct dm_priv	dmpriv;
144 	struct odm_dm_struct odmpriv;
145 
146 	u8	CurAntenna;
147 	u8	AntDivCfg;
148 	u8	TRxAntDivType;
149 
150 	u8	out_ep_extra_queues;
151 
152 	struct P2P_PS_Offload_t	p2p_ps_offload;
153 
154 	/*  Auto FSM to Turn On, include clock, isolation, power control
155 	 *  for MAC only */
156 	u8	bMacPwrCtrlOn;
157 };
158 
159 s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy);
160 
161 /*  EFuse */
162 void Hal_EfuseParseIDCode88E(struct adapter *padapter, u8 *hwinfo);
163 void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *hwinfo,
164 			    bool AutoLoadFail);
165 
166 void rtl8188e_EfuseParseChnlPlan(struct adapter *padapter, u8 *hwinfo,
167 				 bool AutoLoadFail);
168 void Hal_ReadAntennaDiversity88E(struct adapter *pAdapter,u8 *PROMContent,
169 				 bool AutoLoadFail);
170 void Hal_ReadThermalMeter_88E(struct adapter *	dapter, u8 *PROMContent,
171 			      bool AutoloadFail);
172 void Hal_EfuseParseXtal_8188E(struct adapter *pAdapter, u8 *hwinfo,
173 			      bool AutoLoadFail);
174 void Hal_ReadPowerSavingMode88E(struct adapter *pAdapter, u8 *hwinfo,
175 				bool AutoLoadFail);
176 
177 void rtl8188e_read_chip_version(struct adapter *padapter);
178 
179 s32 rtl8188e_iol_efuse_patch(struct adapter *padapter);
180 void rtw_cancel_all_timer(struct adapter *padapter);
181 
182 #endif /* __RTL8188E_HAL_H__ */
183