1 /* SPDX-License-Identifier: ISC */
2 /* Copyright (C) 2020 MediaTek Inc. */
3 
4 #ifndef __MT76_CONNAC_MCU_H
5 #define __MT76_CONNAC_MCU_H
6 
7 #include "mt76_connac.h"
8 
9 #define FW_FEATURE_SET_ENCRYPT		BIT(0)
10 #define FW_FEATURE_SET_KEY_IDX		GENMASK(2, 1)
11 #define FW_FEATURE_ENCRY_MODE		BIT(4)
12 #define FW_FEATURE_OVERRIDE_ADDR	BIT(5)
13 
14 #define DL_MODE_ENCRYPT			BIT(0)
15 #define DL_MODE_KEY_IDX			GENMASK(2, 1)
16 #define DL_MODE_RESET_SEC_IV		BIT(3)
17 #define DL_MODE_WORKING_PDA_CR4		BIT(4)
18 #define DL_MODE_VALID_RAM_ENTRY         BIT(5)
19 #define DL_CONFIG_ENCRY_MODE_SEL	BIT(6)
20 #define DL_MODE_NEED_RSP		BIT(31)
21 
22 #define FW_START_OVERRIDE		BIT(0)
23 #define FW_START_WORKING_PDA_CR4	BIT(2)
24 
25 #define PATCH_SEC_NOT_SUPPORT		GENMASK(31, 0)
26 #define PATCH_SEC_TYPE_MASK		GENMASK(15, 0)
27 #define PATCH_SEC_TYPE_INFO		0x2
28 
29 struct tlv {
30 	__le16 tag;
31 	__le16 len;
32 } __packed;
33 
34 struct bss_info_omac {
35 	__le16 tag;
36 	__le16 len;
37 	u8 hw_bss_idx;
38 	u8 omac_idx;
39 	u8 band_idx;
40 	u8 rsv0;
41 	__le32 conn_type;
42 	u32 rsv1;
43 } __packed;
44 
45 struct bss_info_basic {
46 	__le16 tag;
47 	__le16 len;
48 	__le32 network_type;
49 	u8 active;
50 	u8 rsv0;
51 	__le16 bcn_interval;
52 	u8 bssid[ETH_ALEN];
53 	u8 wmm_idx;
54 	u8 dtim_period;
55 	u8 bmc_wcid_lo;
56 	u8 cipher;
57 	u8 phy_mode;
58 	u8 max_bssid;	/* max BSSID. range: 1 ~ 8, 0: MBSSID disabled */
59 	u8 non_tx_bssid;/* non-transmitted BSSID, 0: transmitted BSSID */
60 	u8 bmc_wcid_hi;	/* high Byte and version */
61 	u8 rsv[2];
62 } __packed;
63 
64 struct bss_info_rf_ch {
65 	__le16 tag;
66 	__le16 len;
67 	u8 pri_ch;
68 	u8 center_ch0;
69 	u8 center_ch1;
70 	u8 bw;
71 	u8 he_ru26_block;	/* 1: don't send HETB in RU26, 0: allow */
72 	u8 he_all_disable;	/* 1: disallow all HETB, 0: allow */
73 	u8 rsv[2];
74 } __packed;
75 
76 struct bss_info_ext_bss {
77 	__le16 tag;
78 	__le16 len;
79 	__le32 mbss_tsf_offset; /* in unit of us */
80 	u8 rsv[8];
81 } __packed;
82 
83 enum {
84 	BSS_INFO_OMAC,
85 	BSS_INFO_BASIC,
86 	BSS_INFO_RF_CH,		/* optional, for BT/LTE coex */
87 	BSS_INFO_PM,		/* sta only */
88 	BSS_INFO_UAPSD,		/* sta only */
89 	BSS_INFO_ROAM_DETECT,	/* obsoleted */
90 	BSS_INFO_LQ_RM,		/* obsoleted */
91 	BSS_INFO_EXT_BSS,
92 	BSS_INFO_BMC_RATE,	/* for bmc rate control in CR4 */
93 	BSS_INFO_SYNC_MODE,	/* obsoleted */
94 	BSS_INFO_RA,
95 	BSS_INFO_HW_AMSDU,
96 	BSS_INFO_BSS_COLOR,
97 	BSS_INFO_HE_BASIC,
98 	BSS_INFO_PROTECT_INFO,
99 	BSS_INFO_OFFLOAD,
100 	BSS_INFO_11V_MBSSID,
101 	BSS_INFO_MAX_NUM
102 };
103 
104 /* sta_rec */
105 
106 struct sta_ntlv_hdr {
107 	u8 rsv[2];
108 	__le16 tlv_num;
109 } __packed;
110 
111 struct sta_req_hdr {
112 	u8 bss_idx;
113 	u8 wlan_idx_lo;
114 	__le16 tlv_num;
115 	u8 is_tlv_append;
116 	u8 muar_idx;
117 	u8 wlan_idx_hi;
118 	u8 rsv;
119 } __packed;
120 
121 struct sta_rec_basic {
122 	__le16 tag;
123 	__le16 len;
124 	__le32 conn_type;
125 	u8 conn_state;
126 	u8 qos;
127 	__le16 aid;
128 	u8 peer_addr[ETH_ALEN];
129 #define EXTRA_INFO_VER	BIT(0)
130 #define EXTRA_INFO_NEW	BIT(1)
131 	__le16 extra_info;
132 } __packed;
133 
134 struct sta_rec_ht {
135 	__le16 tag;
136 	__le16 len;
137 	__le16 ht_cap;
138 	u16 rsv;
139 } __packed;
140 
141 struct sta_rec_vht {
142 	__le16 tag;
143 	__le16 len;
144 	__le32 vht_cap;
145 	__le16 vht_rx_mcs_map;
146 	__le16 vht_tx_mcs_map;
147 	/* mt7915 - mt7921 */
148 	u8 rts_bw_sig;
149 	u8 rsv[3];
150 } __packed;
151 
152 struct sta_rec_uapsd {
153 	__le16 tag;
154 	__le16 len;
155 	u8 dac_map;
156 	u8 tac_map;
157 	u8 max_sp;
158 	u8 rsv0;
159 	__le16 listen_interval;
160 	u8 rsv1[2];
161 } __packed;
162 
163 struct sta_rec_ba {
164 	__le16 tag;
165 	__le16 len;
166 	u8 tid;
167 	u8 ba_type;
168 	u8 amsdu;
169 	u8 ba_en;
170 	__le16 ssn;
171 	__le16 winsize;
172 } __packed;
173 
174 struct sta_rec_he {
175 	__le16 tag;
176 	__le16 len;
177 
178 	__le32 he_cap;
179 
180 	u8 t_frame_dur;
181 	u8 max_ampdu_exp;
182 	u8 bw_set;
183 	u8 device_class;
184 	u8 dcm_tx_mode;
185 	u8 dcm_tx_max_nss;
186 	u8 dcm_rx_mode;
187 	u8 dcm_rx_max_nss;
188 	u8 dcm_max_ru;
189 	u8 punc_pream_rx;
190 	u8 pkt_ext;
191 	u8 rsv1;
192 
193 	__le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
194 
195 	u8 rsv2[2];
196 } __packed;
197 
198 struct sta_rec_amsdu {
199 	__le16 tag;
200 	__le16 len;
201 	u8 max_amsdu_num;
202 	u8 max_mpdu_size;
203 	u8 amsdu_en;
204 	u8 rsv;
205 } __packed;
206 
207 struct sta_rec_state {
208 	__le16 tag;
209 	__le16 len;
210 	__le32 flags;
211 	u8 state;
212 	u8 vht_opmode;
213 	u8 action;
214 	u8 rsv[1];
215 } __packed;
216 
217 #define RA_LEGACY_OFDM GENMASK(13, 6)
218 #define RA_LEGACY_CCK  GENMASK(3, 0)
219 #define HT_MCS_MASK_NUM 10
220 struct sta_rec_ra_info {
221 	__le16 tag;
222 	__le16 len;
223 	__le16 legacy;
224 	u8 rx_mcs_bitmask[HT_MCS_MASK_NUM];
225 } __packed;
226 
227 struct sta_rec_phy {
228 	__le16 tag;
229 	__le16 len;
230 	__le16 basic_rate;
231 	u8 phy_type;
232 	u8 ampdu;
233 	u8 rts_policy;
234 	u8 rcpi;
235 	u8 rsv[2];
236 } __packed;
237 
238 struct sta_rec_he_6g_capa {
239 	__le16 tag;
240 	__le16 len;
241 	__le16 capa;
242 	u8 rsv[2];
243 } __packed;
244 
245 struct sec_key {
246 	u8 cipher_id;
247 	u8 cipher_len;
248 	u8 key_id;
249 	u8 key_len;
250 	u8 key[32];
251 } __packed;
252 
253 struct sta_rec_sec {
254 	__le16 tag;
255 	__le16 len;
256 	u8 add;
257 	u8 n_cipher;
258 	u8 rsv[2];
259 
260 	struct sec_key key[2];
261 } __packed;
262 
263 struct sta_rec_bf {
264 	__le16 tag;
265 	__le16 len;
266 
267 	__le16 pfmu;		/* 0xffff: no access right for PFMU */
268 	bool su_mu;		/* 0: SU, 1: MU */
269 	u8 bf_cap;		/* 0: iBF, 1: eBF */
270 	u8 sounding_phy;	/* 0: legacy, 1: OFDM, 2: HT, 4: VHT */
271 	u8 ndpa_rate;
272 	u8 ndp_rate;
273 	u8 rept_poll_rate;
274 	u8 tx_mode;		/* 0: legacy, 1: OFDM, 2: HT, 4: VHT ... */
275 	u8 ncol;
276 	u8 nrow;
277 	u8 bw;			/* 0: 20M, 1: 40M, 2: 80M, 3: 160M */
278 
279 	u8 mem_total;
280 	u8 mem_20m;
281 	struct {
282 		u8 row;
283 		u8 col: 6, row_msb: 2;
284 	} mem[4];
285 
286 	__le16 smart_ant;
287 	u8 se_idx;
288 	u8 auto_sounding;	/* b7: low traffic indicator
289 				 * b6: Stop sounding for this entry
290 				 * b5 ~ b0: postpone sounding
291 				 */
292 	u8 ibf_timeout;
293 	u8 ibf_dbw;
294 	u8 ibf_ncol;
295 	u8 ibf_nrow;
296 	u8 nrow_bw160;
297 	u8 ncol_bw160;
298 	u8 ru_start_idx;
299 	u8 ru_end_idx;
300 
301 	bool trigger_su;
302 	bool trigger_mu;
303 	bool ng16_su;
304 	bool ng16_mu;
305 	bool codebook42_su;
306 	bool codebook75_mu;
307 
308 	u8 he_ltf;
309 	u8 rsv[3];
310 } __packed;
311 
312 struct sta_rec_bfee {
313 	__le16 tag;
314 	__le16 len;
315 	bool fb_identity_matrix;	/* 1: feedback identity matrix */
316 	bool ignore_feedback;		/* 1: ignore */
317 	u8 rsv[2];
318 } __packed;
319 
320 struct sta_rec_muru {
321 	__le16 tag;
322 	__le16 len;
323 
324 	struct {
325 		bool ofdma_dl_en;
326 		bool ofdma_ul_en;
327 		bool mimo_dl_en;
328 		bool mimo_ul_en;
329 		u8 rsv[4];
330 	} cfg;
331 
332 	struct {
333 		u8 punc_pream_rx;
334 		bool he_20m_in_40m_2g;
335 		bool he_20m_in_160m;
336 		bool he_80m_in_160m;
337 		bool lt16_sigb;
338 		bool rx_su_comp_sigb;
339 		bool rx_su_non_comp_sigb;
340 		u8 rsv;
341 	} ofdma_dl;
342 
343 	struct {
344 		u8 t_frame_dur;
345 		u8 mu_cascading;
346 		u8 uo_ra;
347 		u8 he_2x996_tone;
348 		u8 rx_t_frame_11ac;
349 		u8 rsv[3];
350 	} ofdma_ul;
351 
352 	struct {
353 		bool vht_mu_bfee;
354 		bool partial_bw_dl_mimo;
355 		u8 rsv[2];
356 	} mimo_dl;
357 
358 	struct {
359 		bool full_ul_mimo;
360 		bool partial_ul_mimo;
361 		u8 rsv[2];
362 	} mimo_ul;
363 } __packed;
364 
365 struct sta_phy {
366 	u8 type;
367 	u8 flag;
368 	u8 stbc;
369 	u8 sgi;
370 	u8 bw;
371 	u8 ldpc;
372 	u8 mcs;
373 	u8 nss;
374 	u8 he_ltf;
375 };
376 
377 struct sta_rec_ra {
378 	__le16 tag;
379 	__le16 len;
380 
381 	u8 valid;
382 	u8 auto_rate;
383 	u8 phy_mode;
384 	u8 channel;
385 	u8 bw;
386 	u8 disable_cck;
387 	u8 ht_mcs32;
388 	u8 ht_gf;
389 	u8 ht_mcs[4];
390 	u8 mmps_mode;
391 	u8 gband_256;
392 	u8 af;
393 	u8 auth_wapi_mode;
394 	u8 rate_len;
395 
396 	u8 supp_mode;
397 	u8 supp_cck_rate;
398 	u8 supp_ofdm_rate;
399 	__le32 supp_ht_mcs;
400 	__le16 supp_vht_mcs[4];
401 
402 	u8 op_mode;
403 	u8 op_vht_chan_width;
404 	u8 op_vht_rx_nss;
405 	u8 op_vht_rx_nss_type;
406 
407 	__le32 sta_cap;
408 
409 	struct sta_phy phy;
410 } __packed;
411 
412 struct sta_rec_ra_fixed {
413 	__le16 tag;
414 	__le16 len;
415 
416 	__le32 field;
417 	u8 op_mode;
418 	u8 op_vht_chan_width;
419 	u8 op_vht_rx_nss;
420 	u8 op_vht_rx_nss_type;
421 
422 	struct sta_phy phy;
423 
424 	u8 spe_en;
425 	u8 short_preamble;
426 	u8 is_5g;
427 	u8 mmps_mode;
428 } __packed;
429 
430 /* wtbl_rec */
431 
432 struct wtbl_req_hdr {
433 	u8 wlan_idx_lo;
434 	u8 operation;
435 	__le16 tlv_num;
436 	u8 wlan_idx_hi;
437 	u8 rsv[3];
438 } __packed;
439 
440 struct wtbl_generic {
441 	__le16 tag;
442 	__le16 len;
443 	u8 peer_addr[ETH_ALEN];
444 	u8 muar_idx;
445 	u8 skip_tx;
446 	u8 cf_ack;
447 	u8 qos;
448 	u8 mesh;
449 	u8 adm;
450 	__le16 partial_aid;
451 	u8 baf_en;
452 	u8 aad_om;
453 } __packed;
454 
455 struct wtbl_rx {
456 	__le16 tag;
457 	__le16 len;
458 	u8 rcid;
459 	u8 rca1;
460 	u8 rca2;
461 	u8 rv;
462 	u8 rsv[4];
463 } __packed;
464 
465 struct wtbl_ht {
466 	__le16 tag;
467 	__le16 len;
468 	u8 ht;
469 	u8 ldpc;
470 	u8 af;
471 	u8 mm;
472 	u8 rsv[4];
473 } __packed;
474 
475 struct wtbl_vht {
476 	__le16 tag;
477 	__le16 len;
478 	u8 ldpc;
479 	u8 dyn_bw;
480 	u8 vht;
481 	u8 txop_ps;
482 	u8 rsv[4];
483 } __packed;
484 
485 struct wtbl_tx_ps {
486 	__le16 tag;
487 	__le16 len;
488 	u8 txps;
489 	u8 rsv[3];
490 } __packed;
491 
492 struct wtbl_hdr_trans {
493 	__le16 tag;
494 	__le16 len;
495 	u8 to_ds;
496 	u8 from_ds;
497 	u8 no_rx_trans;
498 	u8 rsv;
499 } __packed;
500 
501 struct wtbl_ba {
502 	__le16 tag;
503 	__le16 len;
504 	/* common */
505 	u8 tid;
506 	u8 ba_type;
507 	u8 rsv0[2];
508 	/* originator only */
509 	__le16 sn;
510 	u8 ba_en;
511 	u8 ba_winsize_idx;
512 	/* originator & recipient */
513 	__le16 ba_winsize;
514 	/* recipient only */
515 	u8 peer_addr[ETH_ALEN];
516 	u8 rst_ba_tid;
517 	u8 rst_ba_sel;
518 	u8 rst_ba_sb;
519 	u8 band_idx;
520 	u8 rsv1[4];
521 } __packed;
522 
523 struct wtbl_smps {
524 	__le16 tag;
525 	__le16 len;
526 	u8 smps;
527 	u8 rsv[3];
528 } __packed;
529 
530 /* mt7615 only */
531 
532 struct wtbl_bf {
533 	__le16 tag;
534 	__le16 len;
535 	u8 ibf;
536 	u8 ebf;
537 	u8 ibf_vht;
538 	u8 ebf_vht;
539 	u8 gid;
540 	u8 pfmu_idx;
541 	u8 rsv[2];
542 } __packed;
543 
544 struct wtbl_pn {
545 	__le16 tag;
546 	__le16 len;
547 	u8 pn[6];
548 	u8 rsv[2];
549 } __packed;
550 
551 struct wtbl_spe {
552 	__le16 tag;
553 	__le16 len;
554 	u8 spe_idx;
555 	u8 rsv[3];
556 } __packed;
557 
558 struct wtbl_raw {
559 	__le16 tag;
560 	__le16 len;
561 	u8 wtbl_idx;
562 	u8 dw;
563 	u8 rsv[2];
564 	__le32 msk;
565 	__le32 val;
566 } __packed;
567 
568 #define MT76_CONNAC_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) +	\
569 					  sizeof(struct wtbl_generic) +	\
570 					  sizeof(struct wtbl_rx) +	\
571 					  sizeof(struct wtbl_ht) +	\
572 					  sizeof(struct wtbl_vht) +	\
573 					  sizeof(struct wtbl_tx_ps) +	\
574 					  sizeof(struct wtbl_hdr_trans) +\
575 					  sizeof(struct wtbl_ba) +	\
576 					  sizeof(struct wtbl_bf) +	\
577 					  sizeof(struct wtbl_smps) +	\
578 					  sizeof(struct wtbl_pn) +	\
579 					  sizeof(struct wtbl_spe))
580 
581 #define MT76_CONNAC_STA_UPDATE_MAX_SIZE	(sizeof(struct sta_req_hdr) +	\
582 					 sizeof(struct sta_rec_basic) +	\
583 					 sizeof(struct sta_rec_bf) +	\
584 					 sizeof(struct sta_rec_ht) +	\
585 					 sizeof(struct sta_rec_he) +	\
586 					 sizeof(struct sta_rec_ba) +	\
587 					 sizeof(struct sta_rec_vht) +	\
588 					 sizeof(struct sta_rec_uapsd) + \
589 					 sizeof(struct sta_rec_amsdu) +	\
590 					 sizeof(struct sta_rec_muru) +	\
591 					 sizeof(struct sta_rec_bfee) +	\
592 					 sizeof(struct sta_rec_ra) +	\
593 					 sizeof(struct sta_rec_sec) +	\
594 					 sizeof(struct sta_rec_ra_fixed) + \
595 					 sizeof(struct sta_rec_he_6g_capa) + \
596 					 sizeof(struct tlv) +		\
597 					 MT76_CONNAC_WTBL_UPDATE_MAX_SIZE)
598 
599 enum {
600 	STA_REC_BASIC,
601 	STA_REC_RA,
602 	STA_REC_RA_CMM_INFO,
603 	STA_REC_RA_UPDATE,
604 	STA_REC_BF,
605 	STA_REC_AMSDU,
606 	STA_REC_BA,
607 	STA_REC_STATE,
608 	STA_REC_TX_PROC,	/* for hdr trans and CSO in CR4 */
609 	STA_REC_HT,
610 	STA_REC_VHT,
611 	STA_REC_APPS,
612 	STA_REC_KEY,
613 	STA_REC_WTBL,
614 	STA_REC_HE,
615 	STA_REC_HW_AMSDU,
616 	STA_REC_WTBL_AADOM,
617 	STA_REC_KEY_V2,
618 	STA_REC_MURU,
619 	STA_REC_MUEDCA,
620 	STA_REC_BFEE,
621 	STA_REC_PHY = 0x15,
622 	STA_REC_HE_6G = 0x17,
623 	STA_REC_MAX_NUM
624 };
625 
626 enum {
627 	WTBL_GENERIC,
628 	WTBL_RX,
629 	WTBL_HT,
630 	WTBL_VHT,
631 	WTBL_PEER_PS,		/* not used */
632 	WTBL_TX_PS,
633 	WTBL_HDR_TRANS,
634 	WTBL_SEC_KEY,
635 	WTBL_BA,
636 	WTBL_RDG,		/* obsoleted */
637 	WTBL_PROTECT,		/* not used */
638 	WTBL_CLEAR,		/* not used */
639 	WTBL_BF,
640 	WTBL_SMPS,
641 	WTBL_RAW_DATA,		/* debug only */
642 	WTBL_PN,
643 	WTBL_SPE,
644 	WTBL_MAX_NUM
645 };
646 
647 #define STA_TYPE_STA			BIT(0)
648 #define STA_TYPE_AP			BIT(1)
649 #define STA_TYPE_ADHOC			BIT(2)
650 #define STA_TYPE_WDS			BIT(4)
651 #define STA_TYPE_BC			BIT(5)
652 
653 #define NETWORK_INFRA			BIT(16)
654 #define NETWORK_P2P			BIT(17)
655 #define NETWORK_IBSS			BIT(18)
656 #define NETWORK_WDS			BIT(21)
657 
658 #define SCAN_FUNC_RANDOM_MAC		BIT(0)
659 #define SCAN_FUNC_SPLIT_SCAN		BIT(5)
660 
661 #define CONNECTION_INFRA_STA		(STA_TYPE_STA | NETWORK_INFRA)
662 #define CONNECTION_INFRA_AP		(STA_TYPE_AP | NETWORK_INFRA)
663 #define CONNECTION_P2P_GC		(STA_TYPE_STA | NETWORK_P2P)
664 #define CONNECTION_P2P_GO		(STA_TYPE_AP | NETWORK_P2P)
665 #define CONNECTION_IBSS_ADHOC		(STA_TYPE_ADHOC | NETWORK_IBSS)
666 #define CONNECTION_WDS			(STA_TYPE_WDS | NETWORK_WDS)
667 #define CONNECTION_INFRA_BC		(STA_TYPE_BC | NETWORK_INFRA)
668 
669 #define CONN_STATE_DISCONNECT		0
670 #define CONN_STATE_CONNECT		1
671 #define CONN_STATE_PORT_SECURE		2
672 
673 /* HE MAC */
674 #define STA_REC_HE_CAP_HTC			BIT(0)
675 #define STA_REC_HE_CAP_BQR			BIT(1)
676 #define STA_REC_HE_CAP_BSR			BIT(2)
677 #define STA_REC_HE_CAP_OM			BIT(3)
678 #define STA_REC_HE_CAP_AMSDU_IN_AMPDU		BIT(4)
679 /* HE PHY */
680 #define STA_REC_HE_CAP_DUAL_BAND		BIT(5)
681 #define STA_REC_HE_CAP_LDPC			BIT(6)
682 #define STA_REC_HE_CAP_TRIG_CQI_FK		BIT(7)
683 #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE	BIT(8)
684 /* STBC */
685 #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC	BIT(9)
686 #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC	BIT(10)
687 #define STA_REC_HE_CAP_GT_80M_TX_STBC		BIT(11)
688 #define STA_REC_HE_CAP_GT_80M_RX_STBC		BIT(12)
689 /* GI */
690 #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI	BIT(13)
691 #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI	BIT(14)
692 #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI	BIT(15)
693 #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI	BIT(16)
694 #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI	BIT(17)
695 /* 242 TONE */
696 #define STA_REC_HE_CAP_BW20_RU242_SUPPORT	BIT(18)
697 #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242	BIT(19)
698 #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242	BIT(20)
699 
700 #define PHY_MODE_A				BIT(0)
701 #define PHY_MODE_B				BIT(1)
702 #define PHY_MODE_G				BIT(2)
703 #define PHY_MODE_GN				BIT(3)
704 #define PHY_MODE_AN				BIT(4)
705 #define PHY_MODE_AC				BIT(5)
706 #define PHY_MODE_AX_24G				BIT(6)
707 #define PHY_MODE_AX_5G				BIT(7)
708 
709 #define PHY_MODE_AX_6G				BIT(0) /* phymode_ext */
710 
711 #define MODE_CCK				BIT(0)
712 #define MODE_OFDM				BIT(1)
713 #define MODE_HT					BIT(2)
714 #define MODE_VHT				BIT(3)
715 #define MODE_HE					BIT(4)
716 
717 #define STA_CAP_WMM				BIT(0)
718 #define STA_CAP_SGI_20				BIT(4)
719 #define STA_CAP_SGI_40				BIT(5)
720 #define STA_CAP_TX_STBC				BIT(6)
721 #define STA_CAP_RX_STBC				BIT(7)
722 #define STA_CAP_VHT_SGI_80			BIT(16)
723 #define STA_CAP_VHT_SGI_160			BIT(17)
724 #define STA_CAP_VHT_TX_STBC			BIT(18)
725 #define STA_CAP_VHT_RX_STBC			BIT(19)
726 #define STA_CAP_VHT_LDPC			BIT(23)
727 #define STA_CAP_LDPC				BIT(24)
728 #define STA_CAP_HT				BIT(26)
729 #define STA_CAP_VHT				BIT(27)
730 #define STA_CAP_HE				BIT(28)
731 
732 enum {
733 	PHY_TYPE_HR_DSSS_INDEX = 0,
734 	PHY_TYPE_ERP_INDEX,
735 	PHY_TYPE_ERP_P2P_INDEX,
736 	PHY_TYPE_OFDM_INDEX,
737 	PHY_TYPE_HT_INDEX,
738 	PHY_TYPE_VHT_INDEX,
739 	PHY_TYPE_HE_INDEX,
740 	PHY_TYPE_INDEX_NUM
741 };
742 
743 #define PHY_TYPE_BIT_HR_DSSS			BIT(PHY_TYPE_HR_DSSS_INDEX)
744 #define PHY_TYPE_BIT_ERP			BIT(PHY_TYPE_ERP_INDEX)
745 #define PHY_TYPE_BIT_OFDM			BIT(PHY_TYPE_OFDM_INDEX)
746 #define PHY_TYPE_BIT_HT				BIT(PHY_TYPE_HT_INDEX)
747 #define PHY_TYPE_BIT_VHT			BIT(PHY_TYPE_VHT_INDEX)
748 #define PHY_TYPE_BIT_HE				BIT(PHY_TYPE_HE_INDEX)
749 
750 #define MT_WTBL_RATE_TX_MODE			GENMASK(9, 6)
751 #define MT_WTBL_RATE_MCS			GENMASK(5, 0)
752 #define MT_WTBL_RATE_NSS			GENMASK(12, 10)
753 #define MT_WTBL_RATE_HE_GI			GENMASK(7, 4)
754 #define MT_WTBL_RATE_GI				GENMASK(3, 0)
755 
756 #define MT_WTBL_W5_CHANGE_BW_RATE		GENMASK(7, 5)
757 #define MT_WTBL_W5_SHORT_GI_20			BIT(8)
758 #define MT_WTBL_W5_SHORT_GI_40			BIT(9)
759 #define MT_WTBL_W5_SHORT_GI_80			BIT(10)
760 #define MT_WTBL_W5_SHORT_GI_160			BIT(11)
761 #define MT_WTBL_W5_BW_CAP			GENMASK(13, 12)
762 #define MT_WTBL_W5_MPDU_FAIL_COUNT		GENMASK(25, 23)
763 #define MT_WTBL_W5_MPDU_OK_COUNT		GENMASK(28, 26)
764 #define MT_WTBL_W5_RATE_IDX			GENMASK(31, 29)
765 
766 enum {
767 	WTBL_RESET_AND_SET = 1,
768 	WTBL_SET,
769 	WTBL_QUERY,
770 	WTBL_RESET_ALL
771 };
772 
773 enum {
774 	MT_BA_TYPE_INVALID,
775 	MT_BA_TYPE_ORIGINATOR,
776 	MT_BA_TYPE_RECIPIENT
777 };
778 
779 enum {
780 	RST_BA_MAC_TID_MATCH,
781 	RST_BA_MAC_MATCH,
782 	RST_BA_NO_MATCH
783 };
784 
785 enum {
786 	DEV_INFO_ACTIVE,
787 	DEV_INFO_MAX_NUM
788 };
789 
790 /* event table */
791 enum {
792 	MCU_EVENT_TARGET_ADDRESS_LEN = 0x01,
793 	MCU_EVENT_FW_START = 0x01,
794 	MCU_EVENT_GENERIC = 0x01,
795 	MCU_EVENT_ACCESS_REG = 0x02,
796 	MCU_EVENT_MT_PATCH_SEM = 0x04,
797 	MCU_EVENT_REG_ACCESS = 0x05,
798 	MCU_EVENT_LP_INFO = 0x07,
799 	MCU_EVENT_SCAN_DONE = 0x0d,
800 	MCU_EVENT_TX_DONE = 0x0f,
801 	MCU_EVENT_ROC = 0x10,
802 	MCU_EVENT_BSS_ABSENCE  = 0x11,
803 	MCU_EVENT_BSS_BEACON_LOSS = 0x13,
804 	MCU_EVENT_CH_PRIVILEGE = 0x18,
805 	MCU_EVENT_SCHED_SCAN_DONE = 0x23,
806 	MCU_EVENT_DBG_MSG = 0x27,
807 	MCU_EVENT_TXPWR = 0xd0,
808 	MCU_EVENT_EXT = 0xed,
809 	MCU_EVENT_RESTART_DL = 0xef,
810 	MCU_EVENT_COREDUMP = 0xf0,
811 };
812 
813 /* ext event table */
814 enum {
815 	MCU_EXT_EVENT_PS_SYNC = 0x5,
816 	MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13,
817 	MCU_EXT_EVENT_THERMAL_PROTECT = 0x22,
818 	MCU_EXT_EVENT_ASSERT_DUMP = 0x23,
819 	MCU_EXT_EVENT_RDD_REPORT = 0x3a,
820 	MCU_EXT_EVENT_CSA_NOTIFY = 0x4f,
821 	MCU_EXT_EVENT_BCC_NOTIFY = 0x75,
822 	MCU_EXT_EVENT_MURU_CTRL = 0x9f,
823 };
824 
825 enum {
826 	MCU_Q_QUERY,
827 	MCU_Q_SET,
828 	MCU_Q_RESERVED,
829 	MCU_Q_NA
830 };
831 
832 enum {
833 	MCU_S2D_H2N,
834 	MCU_S2D_C2N,
835 	MCU_S2D_H2C,
836 	MCU_S2D_H2CN
837 };
838 
839 enum {
840 	PATCH_NOT_DL_SEM_FAIL,
841 	PATCH_IS_DL,
842 	PATCH_NOT_DL_SEM_SUCCESS,
843 	PATCH_REL_SEM_SUCCESS
844 };
845 
846 enum {
847 	FW_STATE_INITIAL,
848 	FW_STATE_FW_DOWNLOAD,
849 	FW_STATE_NORMAL_OPERATION,
850 	FW_STATE_NORMAL_TRX,
851 	FW_STATE_RDY = 7
852 };
853 
854 enum {
855 	CH_SWITCH_NORMAL = 0,
856 	CH_SWITCH_SCAN = 3,
857 	CH_SWITCH_MCC = 4,
858 	CH_SWITCH_DFS = 5,
859 	CH_SWITCH_BACKGROUND_SCAN_START = 6,
860 	CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7,
861 	CH_SWITCH_BACKGROUND_SCAN_STOP = 8,
862 	CH_SWITCH_SCAN_BYPASS_DPD = 9
863 };
864 
865 enum {
866 	THERMAL_SENSOR_TEMP_QUERY,
867 	THERMAL_SENSOR_MANUAL_CTRL,
868 	THERMAL_SENSOR_INFO_QUERY,
869 	THERMAL_SENSOR_TASK_CTRL,
870 };
871 
872 enum mcu_cipher_type {
873 	MCU_CIPHER_NONE = 0,
874 	MCU_CIPHER_WEP40,
875 	MCU_CIPHER_WEP104,
876 	MCU_CIPHER_WEP128,
877 	MCU_CIPHER_TKIP,
878 	MCU_CIPHER_AES_CCMP,
879 	MCU_CIPHER_CCMP_256,
880 	MCU_CIPHER_GCMP,
881 	MCU_CIPHER_GCMP_256,
882 	MCU_CIPHER_WAPI,
883 	MCU_CIPHER_BIP_CMAC_128,
884 };
885 
886 enum {
887 	EE_MODE_EFUSE,
888 	EE_MODE_BUFFER,
889 };
890 
891 enum {
892 	EE_FORMAT_BIN,
893 	EE_FORMAT_WHOLE,
894 	EE_FORMAT_MULTIPLE,
895 };
896 
897 enum {
898 	MCU_PHY_STATE_TX_RATE,
899 	MCU_PHY_STATE_RX_RATE,
900 	MCU_PHY_STATE_RSSI,
901 	MCU_PHY_STATE_CONTENTION_RX_RATE,
902 	MCU_PHY_STATE_OFDMLQ_CNINFO,
903 };
904 
905 #define MCU_CMD_ACK				BIT(0)
906 #define MCU_CMD_UNI				BIT(1)
907 #define MCU_CMD_QUERY				BIT(2)
908 
909 #define MCU_CMD_UNI_EXT_ACK			(MCU_CMD_ACK | MCU_CMD_UNI | \
910 						 MCU_CMD_QUERY)
911 
912 #define __MCU_CMD_FIELD_ID			GENMASK(7, 0)
913 #define __MCU_CMD_FIELD_EXT_ID			GENMASK(15, 8)
914 #define __MCU_CMD_FIELD_QUERY			BIT(16)
915 #define __MCU_CMD_FIELD_UNI			BIT(17)
916 #define __MCU_CMD_FIELD_CE			BIT(18)
917 #define __MCU_CMD_FIELD_WA			BIT(19)
918 
919 #define MCU_CMD(_t)				FIELD_PREP(__MCU_CMD_FIELD_ID,		\
920 							   MCU_CMD_##_t)
921 #define MCU_EXT_CMD(_t)				(MCU_CMD(EXT_CID) | \
922 						 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID,	\
923 							    MCU_EXT_CMD_##_t))
924 #define MCU_EXT_QUERY(_t)			(MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_QUERY)
925 #define MCU_UNI_CMD(_t)				(__MCU_CMD_FIELD_UNI |			\
926 						 FIELD_PREP(__MCU_CMD_FIELD_ID,		\
927 							    MCU_UNI_CMD_##_t))
928 #define MCU_CE_CMD(_t)				(__MCU_CMD_FIELD_CE |			\
929 						 FIELD_PREP(__MCU_CMD_FIELD_ID,		\
930 							   MCU_CE_CMD_##_t))
931 #define MCU_CE_QUERY(_t)			(MCU_CE_CMD(_t) | __MCU_CMD_FIELD_QUERY)
932 
933 #define MCU_WA_CMD(_t)				(MCU_CMD(_t) | __MCU_CMD_FIELD_WA)
934 #define MCU_WA_EXT_CMD(_t)			(MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_WA)
935 #define MCU_WA_PARAM_CMD(_t)			(MCU_WA_CMD(WA_PARAM) | \
936 						 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \
937 							    MCU_WA_PARAM_CMD_##_t))
938 
939 enum {
940 	MCU_EXT_CMD_EFUSE_ACCESS = 0x01,
941 	MCU_EXT_CMD_RF_REG_ACCESS = 0x02,
942 	MCU_EXT_CMD_RF_TEST = 0x04,
943 	MCU_EXT_CMD_PM_STATE_CTRL = 0x07,
944 	MCU_EXT_CMD_CHANNEL_SWITCH = 0x08,
945 	MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11,
946 	MCU_EXT_CMD_FW_LOG_2_HOST = 0x13,
947 	MCU_EXT_CMD_TXBF_ACTION = 0x1e,
948 	MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21,
949 	MCU_EXT_CMD_THERMAL_PROT = 0x23,
950 	MCU_EXT_CMD_STA_REC_UPDATE = 0x25,
951 	MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26,
952 	MCU_EXT_CMD_EDCA_UPDATE = 0x27,
953 	MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A,
954 	MCU_EXT_CMD_THERMAL_CTRL = 0x2c,
955 	MCU_EXT_CMD_WTBL_UPDATE = 0x32,
956 	MCU_EXT_CMD_SET_DRR_CTRL = 0x36,
957 	MCU_EXT_CMD_SET_RDD_CTRL = 0x3a,
958 	MCU_EXT_CMD_ATE_CTRL = 0x3d,
959 	MCU_EXT_CMD_PROTECT_CTRL = 0x3e,
960 	MCU_EXT_CMD_DBDC_CTRL = 0x45,
961 	MCU_EXT_CMD_MAC_INIT_CTRL = 0x46,
962 	MCU_EXT_CMD_RX_HDR_TRANS = 0x47,
963 	MCU_EXT_CMD_MUAR_UPDATE = 0x48,
964 	MCU_EXT_CMD_BCN_OFFLOAD = 0x49,
965 	MCU_EXT_CMD_RX_AIRTIME_CTRL = 0x4a,
966 	MCU_EXT_CMD_SET_RX_PATH = 0x4e,
967 	MCU_EXT_CMD_EFUSE_FREE_BLOCK = 0x4f,
968 	MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
969 	MCU_EXT_CMD_RXDCOC_CAL = 0x59,
970 	MCU_EXT_CMD_GET_MIB_INFO = 0x5a,
971 	MCU_EXT_CMD_TXDPD_CAL = 0x60,
972 	MCU_EXT_CMD_CAL_CACHE = 0x67,
973 	MCU_EXT_CMD_SET_RADAR_TH = 0x7c,
974 	MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d,
975 	MCU_EXT_CMD_MWDS_SUPPORT = 0x80,
976 	MCU_EXT_CMD_SET_SER_TRIGGER = 0x81,
977 	MCU_EXT_CMD_TWT_AGRT_UPDATE = 0x94,
978 	MCU_EXT_CMD_FW_DBG_CTRL = 0x95,
979 	MCU_EXT_CMD_OFFCH_SCAN_CTRL = 0x9a,
980 	MCU_EXT_CMD_SET_RDD_TH = 0x9d,
981 	MCU_EXT_CMD_MURU_CTRL = 0x9f,
982 	MCU_EXT_CMD_SET_SPR = 0xa8,
983 	MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab,
984 	MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac,
985 	MCU_EXT_CMD_PHY_STAT_INFO = 0xad,
986 };
987 
988 enum {
989 	MCU_UNI_CMD_DEV_INFO_UPDATE = 0x01,
990 	MCU_UNI_CMD_BSS_INFO_UPDATE = 0x02,
991 	MCU_UNI_CMD_STA_REC_UPDATE = 0x03,
992 	MCU_UNI_CMD_SUSPEND = 0x05,
993 	MCU_UNI_CMD_OFFLOAD = 0x06,
994 	MCU_UNI_CMD_HIF_CTRL = 0x07,
995 	MCU_UNI_CMD_SNIFFER = 0x24,
996 };
997 
998 enum {
999 	MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01,
1000 	MCU_CMD_FW_START_REQ = 0x02,
1001 	MCU_CMD_INIT_ACCESS_REG = 0x3,
1002 	MCU_CMD_NIC_POWER_CTRL = 0x4,
1003 	MCU_CMD_PATCH_START_REQ = 0x05,
1004 	MCU_CMD_PATCH_FINISH_REQ = 0x07,
1005 	MCU_CMD_PATCH_SEM_CONTROL = 0x10,
1006 	MCU_CMD_WA_PARAM = 0xc4,
1007 	MCU_CMD_EXT_CID = 0xed,
1008 	MCU_CMD_FW_SCATTER = 0xee,
1009 	MCU_CMD_RESTART_DL_REQ = 0xef,
1010 };
1011 
1012 /* offload mcu commands */
1013 enum {
1014 	MCU_CE_CMD_TEST_CTRL = 0x01,
1015 	MCU_CE_CMD_START_HW_SCAN = 0x03,
1016 	MCU_CE_CMD_SET_PS_PROFILE = 0x05,
1017 	MCU_CE_CMD_SET_CHAN_DOMAIN = 0x0f,
1018 	MCU_CE_CMD_SET_BSS_CONNECTED = 0x16,
1019 	MCU_CE_CMD_SET_BSS_ABORT = 0x17,
1020 	MCU_CE_CMD_CANCEL_HW_SCAN = 0x1b,
1021 	MCU_CE_CMD_SET_ROC = 0x1c,
1022 	MCU_CE_CMD_SET_EDCA_PARMS = 0x1d,
1023 	MCU_CE_CMD_SET_P2P_OPPPS = 0x33,
1024 	MCU_CE_CMD_SET_RATE_TX_POWER = 0x5d,
1025 	MCU_CE_CMD_SCHED_SCAN_ENABLE = 0x61,
1026 	MCU_CE_CMD_SCHED_SCAN_REQ = 0x62,
1027 	MCU_CE_CMD_GET_NIC_CAPAB = 0x8a,
1028 	MCU_CE_CMD_SET_MU_EDCA_PARMS = 0xb0,
1029 	MCU_CE_CMD_REG_WRITE = 0xc0,
1030 	MCU_CE_CMD_REG_READ = 0xc0,
1031 	MCU_CE_CMD_CHIP_CONFIG = 0xca,
1032 	MCU_CE_CMD_FWLOG_2_HOST = 0xc5,
1033 	MCU_CE_CMD_GET_WTBL = 0xcd,
1034 	MCU_CE_CMD_GET_TXPWR = 0xd0,
1035 };
1036 
1037 enum {
1038 	PATCH_SEM_RELEASE,
1039 	PATCH_SEM_GET
1040 };
1041 
1042 enum {
1043 	UNI_BSS_INFO_BASIC = 0,
1044 	UNI_BSS_INFO_RLM = 2,
1045 	UNI_BSS_INFO_BSS_COLOR = 4,
1046 	UNI_BSS_INFO_HE_BASIC = 5,
1047 	UNI_BSS_INFO_BCN_CONTENT = 7,
1048 	UNI_BSS_INFO_QBSS = 15,
1049 	UNI_BSS_INFO_UAPSD = 19,
1050 	UNI_BSS_INFO_PS = 21,
1051 	UNI_BSS_INFO_BCNFT = 22,
1052 };
1053 
1054 enum {
1055 	UNI_OFFLOAD_OFFLOAD_ARP,
1056 	UNI_OFFLOAD_OFFLOAD_ND,
1057 	UNI_OFFLOAD_OFFLOAD_GTK_REKEY,
1058 	UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT,
1059 };
1060 
1061 enum {
1062 	MT_NIC_CAP_TX_RESOURCE,
1063 	MT_NIC_CAP_TX_EFUSE_ADDR,
1064 	MT_NIC_CAP_COEX,
1065 	MT_NIC_CAP_SINGLE_SKU,
1066 	MT_NIC_CAP_CSUM_OFFLOAD,
1067 	MT_NIC_CAP_HW_VER,
1068 	MT_NIC_CAP_SW_VER,
1069 	MT_NIC_CAP_MAC_ADDR,
1070 	MT_NIC_CAP_PHY,
1071 	MT_NIC_CAP_MAC,
1072 	MT_NIC_CAP_FRAME_BUF,
1073 	MT_NIC_CAP_BEAM_FORM,
1074 	MT_NIC_CAP_LOCATION,
1075 	MT_NIC_CAP_MUMIMO,
1076 	MT_NIC_CAP_BUFFER_MODE_INFO,
1077 	MT_NIC_CAP_HW_ADIE_VERSION = 0x14,
1078 	MT_NIC_CAP_ANTSWP = 0x16,
1079 	MT_NIC_CAP_WFDMA_REALLOC,
1080 	MT_NIC_CAP_6G,
1081 };
1082 
1083 #define UNI_WOW_DETECT_TYPE_MAGIC		BIT(0)
1084 #define UNI_WOW_DETECT_TYPE_ANY			BIT(1)
1085 #define UNI_WOW_DETECT_TYPE_DISCONNECT		BIT(2)
1086 #define UNI_WOW_DETECT_TYPE_GTK_REKEY_FAIL	BIT(3)
1087 #define UNI_WOW_DETECT_TYPE_BCN_LOST		BIT(4)
1088 #define UNI_WOW_DETECT_TYPE_SCH_SCAN_HIT	BIT(5)
1089 #define UNI_WOW_DETECT_TYPE_BITMAP		BIT(6)
1090 
1091 enum {
1092 	UNI_SUSPEND_MODE_SETTING,
1093 	UNI_SUSPEND_WOW_CTRL,
1094 	UNI_SUSPEND_WOW_GPIO_PARAM,
1095 	UNI_SUSPEND_WOW_WAKEUP_PORT,
1096 	UNI_SUSPEND_WOW_PATTERN,
1097 };
1098 
1099 enum {
1100 	WOW_USB = 1,
1101 	WOW_PCIE = 2,
1102 	WOW_GPIO = 3,
1103 };
1104 
1105 struct mt76_connac_bss_basic_tlv {
1106 	__le16 tag;
1107 	__le16 len;
1108 	u8 active;
1109 	u8 omac_idx;
1110 	u8 hw_bss_idx;
1111 	u8 band_idx;
1112 	__le32 conn_type;
1113 	u8 conn_state;
1114 	u8 wmm_idx;
1115 	u8 bssid[ETH_ALEN];
1116 	__le16 bmc_tx_wlan_idx;
1117 	__le16 bcn_interval;
1118 	u8 dtim_period;
1119 	u8 phymode; /* bit(0): A
1120 		     * bit(1): B
1121 		     * bit(2): G
1122 		     * bit(3): GN
1123 		     * bit(4): AN
1124 		     * bit(5): AC
1125 		     * bit(6): AX2
1126 		     * bit(7): AX5
1127 		     * bit(8): AX6
1128 		     */
1129 	__le16 sta_idx;
1130 	__le16 nonht_basic_phy;
1131 	u8 phymode_ext; /* bit(0) AX_6G */
1132 	u8 pad[1];
1133 } __packed;
1134 
1135 struct mt76_connac_bss_qos_tlv {
1136 	__le16 tag;
1137 	__le16 len;
1138 	u8 qos;
1139 	u8 pad[3];
1140 } __packed;
1141 
1142 struct mt76_connac_beacon_loss_event {
1143 	u8 bss_idx;
1144 	u8 reason;
1145 	u8 pad[2];
1146 } __packed;
1147 
1148 struct mt76_connac_mcu_bss_event {
1149 	u8 bss_idx;
1150 	u8 is_absent;
1151 	u8 free_quota;
1152 	u8 pad;
1153 } __packed;
1154 
1155 struct mt76_connac_mcu_scan_ssid {
1156 	__le32 ssid_len;
1157 	u8 ssid[IEEE80211_MAX_SSID_LEN];
1158 } __packed;
1159 
1160 struct mt76_connac_mcu_scan_channel {
1161 	u8 band; /* 1: 2.4GHz
1162 		  * 2: 5.0GHz
1163 		  * Others: Reserved
1164 		  */
1165 	u8 channel_num;
1166 } __packed;
1167 
1168 struct mt76_connac_mcu_scan_match {
1169 	__le32 rssi_th;
1170 	u8 ssid[IEEE80211_MAX_SSID_LEN];
1171 	u8 ssid_len;
1172 	u8 rsv[3];
1173 } __packed;
1174 
1175 struct mt76_connac_hw_scan_req {
1176 	u8 seq_num;
1177 	u8 bss_idx;
1178 	u8 scan_type; /* 0: PASSIVE SCAN
1179 		       * 1: ACTIVE SCAN
1180 		       */
1181 	u8 ssid_type; /* BIT(0) wildcard SSID
1182 		       * BIT(1) P2P wildcard SSID
1183 		       * BIT(2) specified SSID + wildcard SSID
1184 		       * BIT(2) + ssid_type_ext BIT(0) specified SSID only
1185 		       */
1186 	u8 ssids_num;
1187 	u8 probe_req_num; /* Number of probe request for each SSID */
1188 	u8 scan_func; /* BIT(0) Enable random MAC scan
1189 		       * BIT(1) Disable DBDC scan type 1~3.
1190 		       * BIT(2) Use DBDC scan type 3 (dedicated one RF to scan).
1191 		       */
1192 	u8 version; /* 0: Not support fields after ies.
1193 		     * 1: Support fields after ies.
1194 		     */
1195 	struct mt76_connac_mcu_scan_ssid ssids[4];
1196 	__le16 probe_delay_time;
1197 	__le16 channel_dwell_time; /* channel Dwell interval */
1198 	__le16 timeout_value;
1199 	u8 channel_type; /* 0: Full channels
1200 			  * 1: Only 2.4GHz channels
1201 			  * 2: Only 5GHz channels
1202 			  * 3: P2P social channel only (channel #1, #6 and #11)
1203 			  * 4: Specified channels
1204 			  * Others: Reserved
1205 			  */
1206 	u8 channels_num; /* valid when channel_type is 4 */
1207 	/* valid when channels_num is set */
1208 	struct mt76_connac_mcu_scan_channel channels[32];
1209 	__le16 ies_len;
1210 	u8 ies[MT76_CONNAC_SCAN_IE_LEN];
1211 	/* following fields are valid if version > 0 */
1212 	u8 ext_channels_num;
1213 	u8 ext_ssids_num;
1214 	__le16 channel_min_dwell_time;
1215 	struct mt76_connac_mcu_scan_channel ext_channels[32];
1216 	struct mt76_connac_mcu_scan_ssid ext_ssids[6];
1217 	u8 bssid[ETH_ALEN];
1218 	u8 random_mac[ETH_ALEN]; /* valid when BIT(1) in scan_func is set. */
1219 	u8 pad[63];
1220 	u8 ssid_type_ext;
1221 } __packed;
1222 
1223 #define MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM		64
1224 
1225 struct mt76_connac_hw_scan_done {
1226 	u8 seq_num;
1227 	u8 sparse_channel_num;
1228 	struct mt76_connac_mcu_scan_channel sparse_channel;
1229 	u8 complete_channel_num;
1230 	u8 current_state;
1231 	u8 version;
1232 	u8 pad;
1233 	__le32 beacon_scan_num;
1234 	u8 pno_enabled;
1235 	u8 pad2[3];
1236 	u8 sparse_channel_valid_num;
1237 	u8 pad3[3];
1238 	u8 channel_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1239 	/* idle format for channel_idle_time
1240 	 * 0: first bytes: idle time(ms) 2nd byte: dwell time(ms)
1241 	 * 1: first bytes: idle time(8ms) 2nd byte: dwell time(8ms)
1242 	 * 2: dwell time (16us)
1243 	 */
1244 	__le16 channel_idle_time[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1245 	/* beacon and probe response count */
1246 	u8 beacon_probe_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1247 	u8 mdrdy_count[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1248 	__le32 beacon_2g_num;
1249 	__le32 beacon_5g_num;
1250 } __packed;
1251 
1252 struct mt76_connac_sched_scan_req {
1253 	u8 version;
1254 	u8 seq_num;
1255 	u8 stop_on_match;
1256 	u8 ssids_num;
1257 	u8 match_num;
1258 	u8 pad;
1259 	__le16 ie_len;
1260 	struct mt76_connac_mcu_scan_ssid ssids[MT76_CONNAC_MAX_SCHED_SCAN_SSID];
1261 	struct mt76_connac_mcu_scan_match match[MT76_CONNAC_MAX_SCAN_MATCH];
1262 	u8 channel_type;
1263 	u8 channels_num;
1264 	u8 intervals_num;
1265 	u8 scan_func; /* MT7663: BIT(0) eable random mac address */
1266 	struct mt76_connac_mcu_scan_channel channels[64];
1267 	__le16 intervals[MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL];
1268 	union {
1269 		struct {
1270 			u8 random_mac[ETH_ALEN];
1271 			u8 pad2[58];
1272 		} mt7663;
1273 		struct {
1274 			u8 bss_idx;
1275 			u8 pad1[3];
1276 			__le32 delay;
1277 			u8 pad2[12];
1278 			u8 random_mac[ETH_ALEN];
1279 			u8 pad3[38];
1280 		} mt7921;
1281 	};
1282 } __packed;
1283 
1284 struct mt76_connac_sched_scan_done {
1285 	u8 seq_num;
1286 	u8 status; /* 0: ssid found */
1287 	__le16 pad;
1288 } __packed;
1289 
1290 struct bss_info_uni_bss_color {
1291 	__le16 tag;
1292 	__le16 len;
1293 	u8 enable;
1294 	u8 bss_color;
1295 	u8 rsv[2];
1296 } __packed;
1297 
1298 struct bss_info_uni_he {
1299 	__le16 tag;
1300 	__le16 len;
1301 	__le16 he_rts_thres;
1302 	u8 he_pe_duration;
1303 	u8 su_disable;
1304 	__le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
1305 	u8 rsv[2];
1306 } __packed;
1307 
1308 struct mt76_connac_gtk_rekey_tlv {
1309 	__le16 tag;
1310 	__le16 len;
1311 	u8 kek[NL80211_KEK_LEN];
1312 	u8 kck[NL80211_KCK_LEN];
1313 	u8 replay_ctr[NL80211_REPLAY_CTR_LEN];
1314 	u8 rekey_mode; /* 0: rekey offload enable
1315 			* 1: rekey offload disable
1316 			* 2: rekey update
1317 			*/
1318 	u8 keyid;
1319 	u8 option; /* 1: rekey data update without enabling offload */
1320 	u8 pad[1];
1321 	__le32 proto; /* WPA-RSN-WAPI-OPSN */
1322 	__le32 pairwise_cipher;
1323 	__le32 group_cipher;
1324 	__le32 key_mgmt; /* NONE-PSK-IEEE802.1X */
1325 	__le32 mgmt_group_cipher;
1326 	u8 reserverd[4];
1327 } __packed;
1328 
1329 #define MT76_CONNAC_WOW_MASK_MAX_LEN			16
1330 #define MT76_CONNAC_WOW_PATTEN_MAX_LEN			128
1331 
1332 struct mt76_connac_wow_pattern_tlv {
1333 	__le16 tag;
1334 	__le16 len;
1335 	u8 index; /* pattern index */
1336 	u8 enable; /* 0: disable
1337 		    * 1: enable
1338 		    */
1339 	u8 data_len; /* pattern length */
1340 	u8 pad;
1341 	u8 mask[MT76_CONNAC_WOW_MASK_MAX_LEN];
1342 	u8 pattern[MT76_CONNAC_WOW_PATTEN_MAX_LEN];
1343 	u8 rsv[4];
1344 } __packed;
1345 
1346 struct mt76_connac_wow_ctrl_tlv {
1347 	__le16 tag;
1348 	__le16 len;
1349 	u8 cmd; /* 0x1: PM_WOWLAN_REQ_START
1350 		 * 0x2: PM_WOWLAN_REQ_STOP
1351 		 * 0x3: PM_WOWLAN_PARAM_CLEAR
1352 		 */
1353 	u8 trigger; /* 0: NONE
1354 		     * BIT(0): NL80211_WOWLAN_TRIG_MAGIC_PKT
1355 		     * BIT(1): NL80211_WOWLAN_TRIG_ANY
1356 		     * BIT(2): NL80211_WOWLAN_TRIG_DISCONNECT
1357 		     * BIT(3): NL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE
1358 		     * BIT(4): BEACON_LOST
1359 		     * BIT(5): NL80211_WOWLAN_TRIG_NET_DETECT
1360 		     */
1361 	u8 wakeup_hif; /* 0x0: HIF_SDIO
1362 			* 0x1: HIF_USB
1363 			* 0x2: HIF_PCIE
1364 			* 0x3: HIF_GPIO
1365 			*/
1366 	u8 pad;
1367 	u8 rsv[4];
1368 } __packed;
1369 
1370 struct mt76_connac_wow_gpio_param_tlv {
1371 	__le16 tag;
1372 	__le16 len;
1373 	u8 gpio_pin;
1374 	u8 trigger_lvl;
1375 	u8 pad[2];
1376 	__le32 gpio_interval;
1377 	u8 rsv[4];
1378 } __packed;
1379 
1380 struct mt76_connac_arpns_tlv {
1381 	__le16 tag;
1382 	__le16 len;
1383 	u8 mode;
1384 	u8 ips_num;
1385 	u8 option;
1386 	u8 pad[1];
1387 } __packed;
1388 
1389 struct mt76_connac_suspend_tlv {
1390 	__le16 tag;
1391 	__le16 len;
1392 	u8 enable; /* 0: suspend mode disabled
1393 		    * 1: suspend mode enabled
1394 		    */
1395 	u8 mdtim; /* LP parameter */
1396 	u8 wow_suspend; /* 0: update by origin policy
1397 			 * 1: update by wow dtim
1398 			 */
1399 	u8 pad[5];
1400 } __packed;
1401 
1402 enum mt76_sta_info_state {
1403 	MT76_STA_INFO_STATE_NONE,
1404 	MT76_STA_INFO_STATE_AUTH,
1405 	MT76_STA_INFO_STATE_ASSOC
1406 };
1407 
1408 struct mt76_sta_cmd_info {
1409 	struct ieee80211_sta *sta;
1410 	struct mt76_wcid *wcid;
1411 
1412 	struct ieee80211_vif *vif;
1413 
1414 	bool offload_fw;
1415 	bool enable;
1416 	bool newly;
1417 	int cmd;
1418 	u8 rcpi;
1419 	u8 state;
1420 };
1421 
1422 #define MT_SKU_POWER_LIMIT	161
1423 
1424 struct mt76_connac_sku_tlv {
1425 	u8 channel;
1426 	s8 pwr_limit[MT_SKU_POWER_LIMIT];
1427 } __packed;
1428 
1429 struct mt76_connac_tx_power_limit_tlv {
1430 	/* DW0 - common info*/
1431 	u8 ver;
1432 	u8 pad0;
1433 	__le16 len;
1434 	/* DW1 - cmd hint */
1435 	u8 n_chan; /* # channel */
1436 	u8 band; /* 2.4GHz - 5GHz - 6GHz */
1437 	u8 last_msg;
1438 	u8 pad1;
1439 	/* DW3 */
1440 	u8 alpha2[4]; /* regulatory_request.alpha2 */
1441 	u8 pad2[32];
1442 } __packed;
1443 
1444 struct mt76_connac_config {
1445 	__le16 id;
1446 	u8 type;
1447 	u8 resp_type;
1448 	__le16 data_size;
1449 	__le16 resv;
1450 	u8 data[320];
1451 } __packed;
1452 
1453 static inline enum mcu_cipher_type
mt76_connac_mcu_get_cipher(int cipher)1454 mt76_connac_mcu_get_cipher(int cipher)
1455 {
1456 	switch (cipher) {
1457 	case WLAN_CIPHER_SUITE_WEP40:
1458 		return MCU_CIPHER_WEP40;
1459 	case WLAN_CIPHER_SUITE_WEP104:
1460 		return MCU_CIPHER_WEP104;
1461 	case WLAN_CIPHER_SUITE_TKIP:
1462 		return MCU_CIPHER_TKIP;
1463 	case WLAN_CIPHER_SUITE_AES_CMAC:
1464 		return MCU_CIPHER_BIP_CMAC_128;
1465 	case WLAN_CIPHER_SUITE_CCMP:
1466 		return MCU_CIPHER_AES_CCMP;
1467 	case WLAN_CIPHER_SUITE_CCMP_256:
1468 		return MCU_CIPHER_CCMP_256;
1469 	case WLAN_CIPHER_SUITE_GCMP:
1470 		return MCU_CIPHER_GCMP;
1471 	case WLAN_CIPHER_SUITE_GCMP_256:
1472 		return MCU_CIPHER_GCMP_256;
1473 	case WLAN_CIPHER_SUITE_SMS4:
1474 		return MCU_CIPHER_WAPI;
1475 	default:
1476 		return MCU_CIPHER_NONE;
1477 	}
1478 }
1479 
1480 static inline u32
mt76_connac_mcu_gen_dl_mode(struct mt76_dev * dev,u8 feature_set,bool is_wa)1481 mt76_connac_mcu_gen_dl_mode(struct mt76_dev *dev, u8 feature_set, bool is_wa)
1482 {
1483 	u32 ret = 0;
1484 
1485 	ret |= feature_set & FW_FEATURE_SET_ENCRYPT ?
1486 	       DL_MODE_ENCRYPT | DL_MODE_RESET_SEC_IV : 0;
1487 	if (is_mt7921(dev))
1488 		ret |= feature_set & FW_FEATURE_ENCRY_MODE ?
1489 		       DL_CONFIG_ENCRY_MODE_SEL : 0;
1490 	ret |= FIELD_PREP(DL_MODE_KEY_IDX,
1491 			  FIELD_GET(FW_FEATURE_SET_KEY_IDX, feature_set));
1492 	ret |= DL_MODE_NEED_RSP;
1493 	ret |= is_wa ? DL_MODE_WORKING_PDA_CR4 : 0;
1494 
1495 	return ret;
1496 }
1497 
1498 #define to_wcid_lo(id)		FIELD_GET(GENMASK(7, 0), (u16)id)
1499 #define to_wcid_hi(id)		FIELD_GET(GENMASK(9, 8), (u16)id)
1500 
1501 static inline void
mt76_connac_mcu_get_wlan_idx(struct mt76_dev * dev,struct mt76_wcid * wcid,u8 * wlan_idx_lo,u8 * wlan_idx_hi)1502 mt76_connac_mcu_get_wlan_idx(struct mt76_dev *dev, struct mt76_wcid *wcid,
1503 			     u8 *wlan_idx_lo, u8 *wlan_idx_hi)
1504 {
1505 	*wlan_idx_hi = 0;
1506 
1507 	if (!is_connac_v1(dev)) {
1508 		*wlan_idx_lo = wcid ? to_wcid_lo(wcid->idx) : 0;
1509 		*wlan_idx_hi = wcid ? to_wcid_hi(wcid->idx) : 0;
1510 	} else {
1511 		*wlan_idx_lo = wcid ? wcid->idx : 0;
1512 	}
1513 }
1514 
1515 struct sk_buff *
1516 __mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif,
1517 				struct mt76_wcid *wcid, int len);
1518 static inline struct sk_buff *
mt76_connac_mcu_alloc_sta_req(struct mt76_dev * dev,struct mt76_vif * mvif,struct mt76_wcid * wcid)1519 mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif,
1520 			      struct mt76_wcid *wcid)
1521 {
1522 	return __mt76_connac_mcu_alloc_sta_req(dev, mvif, wcid,
1523 					       MT76_CONNAC_STA_UPDATE_MAX_SIZE);
1524 }
1525 
1526 struct wtbl_req_hdr *
1527 mt76_connac_mcu_alloc_wtbl_req(struct mt76_dev *dev, struct mt76_wcid *wcid,
1528 			       int cmd, void *sta_wtbl, struct sk_buff **skb);
1529 struct tlv *mt76_connac_mcu_add_nested_tlv(struct sk_buff *skb, int tag,
1530 					   int len, void *sta_ntlv,
1531 					   void *sta_wtbl);
1532 static inline struct tlv *
mt76_connac_mcu_add_tlv(struct sk_buff * skb,int tag,int len)1533 mt76_connac_mcu_add_tlv(struct sk_buff *skb, int tag, int len)
1534 {
1535 	return mt76_connac_mcu_add_nested_tlv(skb, tag, len, skb->data, NULL);
1536 }
1537 
1538 int mt76_connac_mcu_set_channel_domain(struct mt76_phy *phy);
1539 int mt76_connac_mcu_set_vif_ps(struct mt76_dev *dev, struct ieee80211_vif *vif);
1540 void mt76_connac_mcu_sta_basic_tlv(struct sk_buff *skb,
1541 				   struct ieee80211_vif *vif,
1542 				   struct ieee80211_sta *sta, bool enable,
1543 				   bool newly);
1544 void mt76_connac_mcu_wtbl_generic_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1545 				      struct ieee80211_vif *vif,
1546 				      struct ieee80211_sta *sta, void *sta_wtbl,
1547 				      void *wtbl_tlv);
1548 void mt76_connac_mcu_wtbl_hdr_trans_tlv(struct sk_buff *skb,
1549 					struct ieee80211_vif *vif,
1550 					struct mt76_wcid *wcid,
1551 					void *sta_wtbl, void *wtbl_tlv);
1552 int mt76_connac_mcu_sta_update_hdr_trans(struct mt76_dev *dev,
1553 					 struct ieee80211_vif *vif,
1554 					 struct mt76_wcid *wcid, int cmd);
1555 int mt76_connac_mcu_wtbl_update_hdr_trans(struct mt76_dev *dev,
1556 					  struct ieee80211_vif *vif,
1557 					  struct ieee80211_sta *sta);
1558 void mt76_connac_mcu_sta_tlv(struct mt76_phy *mphy, struct sk_buff *skb,
1559 			     struct ieee80211_sta *sta,
1560 			     struct ieee80211_vif *vif,
1561 			     u8 rcpi, u8 state);
1562 void mt76_connac_mcu_wtbl_ht_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1563 				 struct ieee80211_sta *sta, void *sta_wtbl,
1564 				 void *wtbl_tlv, bool ht_ldpc, bool vht_ldpc);
1565 void mt76_connac_mcu_wtbl_ba_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1566 				 struct ieee80211_ampdu_params *params,
1567 				 bool enable, bool tx, void *sta_wtbl,
1568 				 void *wtbl_tlv);
1569 void mt76_connac_mcu_sta_ba_tlv(struct sk_buff *skb,
1570 				struct ieee80211_ampdu_params *params,
1571 				bool enable, bool tx);
1572 int mt76_connac_mcu_uni_add_dev(struct mt76_phy *phy,
1573 				struct ieee80211_vif *vif,
1574 				struct mt76_wcid *wcid,
1575 				bool enable);
1576 int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
1577 			   struct ieee80211_ampdu_params *params,
1578 			   int cmd, bool enable, bool tx);
1579 int mt76_connac_mcu_uni_add_bss(struct mt76_phy *phy,
1580 				struct ieee80211_vif *vif,
1581 				struct mt76_wcid *wcid,
1582 				bool enable);
1583 int mt76_connac_mcu_sta_cmd(struct mt76_phy *phy,
1584 			    struct mt76_sta_cmd_info *info);
1585 void mt76_connac_mcu_beacon_loss_iter(void *priv, u8 *mac,
1586 				      struct ieee80211_vif *vif);
1587 int mt76_connac_mcu_set_rts_thresh(struct mt76_dev *dev, u32 val, u8 band);
1588 int mt76_connac_mcu_set_mac_enable(struct mt76_dev *dev, int band, bool enable,
1589 				   bool hdr_trans);
1590 int mt76_connac_mcu_init_download(struct mt76_dev *dev, u32 addr, u32 len,
1591 				  u32 mode);
1592 int mt76_connac_mcu_start_patch(struct mt76_dev *dev);
1593 int mt76_connac_mcu_patch_sem_ctrl(struct mt76_dev *dev, bool get);
1594 int mt76_connac_mcu_start_firmware(struct mt76_dev *dev, u32 addr, u32 option);
1595 int mt76_connac_mcu_get_nic_capability(struct mt76_phy *phy);
1596 
1597 int mt76_connac_mcu_hw_scan(struct mt76_phy *phy, struct ieee80211_vif *vif,
1598 			    struct ieee80211_scan_request *scan_req);
1599 int mt76_connac_mcu_cancel_hw_scan(struct mt76_phy *phy,
1600 				   struct ieee80211_vif *vif);
1601 int mt76_connac_mcu_sched_scan_req(struct mt76_phy *phy,
1602 				   struct ieee80211_vif *vif,
1603 				   struct cfg80211_sched_scan_request *sreq);
1604 int mt76_connac_mcu_sched_scan_enable(struct mt76_phy *phy,
1605 				      struct ieee80211_vif *vif,
1606 				      bool enable);
1607 int mt76_connac_mcu_update_arp_filter(struct mt76_dev *dev,
1608 				      struct mt76_vif *vif,
1609 				      struct ieee80211_bss_conf *info);
1610 int mt76_connac_mcu_update_gtk_rekey(struct ieee80211_hw *hw,
1611 				     struct ieee80211_vif *vif,
1612 				     struct cfg80211_gtk_rekey_data *key);
1613 int mt76_connac_mcu_set_hif_suspend(struct mt76_dev *dev, bool suspend);
1614 void mt76_connac_mcu_set_suspend_iter(void *priv, u8 *mac,
1615 				      struct ieee80211_vif *vif);
1616 int mt76_connac_sta_state_dp(struct mt76_dev *dev,
1617 			     enum ieee80211_sta_state old_state,
1618 			     enum ieee80211_sta_state new_state);
1619 int mt76_connac_mcu_chip_config(struct mt76_dev *dev);
1620 int mt76_connac_mcu_set_deep_sleep(struct mt76_dev *dev, bool enable);
1621 void mt76_connac_mcu_coredump_event(struct mt76_dev *dev, struct sk_buff *skb,
1622 				    struct mt76_connac_coredump *coredump);
1623 int mt76_connac_mcu_set_rate_txpower(struct mt76_phy *phy);
1624 int mt76_connac_mcu_set_p2p_oppps(struct ieee80211_hw *hw,
1625 				  struct ieee80211_vif *vif);
1626 u32 mt76_connac_mcu_reg_rr(struct mt76_dev *dev, u32 offset);
1627 void mt76_connac_mcu_reg_wr(struct mt76_dev *dev, u32 offset, u32 val);
1628 
1629 const struct ieee80211_sta_he_cap *
1630 mt76_connac_get_he_phy_cap(struct mt76_phy *phy, struct ieee80211_vif *vif);
1631 u8 mt76_connac_get_phy_mode(struct mt76_phy *phy, struct ieee80211_vif *vif,
1632 			    enum nl80211_band band, struct ieee80211_sta *sta);
1633 
1634 int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
1635 			    struct mt76_connac_sta_key_conf *sta_key_conf,
1636 			    struct ieee80211_key_conf *key, int mcu_cmd,
1637 			    struct mt76_wcid *wcid, enum set_key_cmd cmd);
1638 
1639 void mt76_connac_mcu_bss_ext_tlv(struct sk_buff *skb, struct mt76_vif *mvif);
1640 void mt76_connac_mcu_bss_omac_tlv(struct sk_buff *skb,
1641 				  struct ieee80211_vif *vif);
1642 int mt76_connac_mcu_bss_basic_tlv(struct sk_buff *skb,
1643 				  struct ieee80211_vif *vif,
1644 				  struct ieee80211_sta *sta,
1645 				  struct mt76_phy *phy, u16 wlan_idx,
1646 				  bool enable);
1647 void mt76_connac_mcu_sta_uapsd(struct sk_buff *skb, struct ieee80211_vif *vif,
1648 			       struct ieee80211_sta *sta);
1649 void mt76_connac_mcu_wtbl_smps_tlv(struct sk_buff *skb,
1650 				   struct ieee80211_sta *sta,
1651 				   void *sta_wtbl, void *wtbl_tlv);
1652 int mt76_connac_mcu_set_pm(struct mt76_dev *dev, int band, int enter);
1653 int mt76_connac_mcu_restart(struct mt76_dev *dev);
1654 int mt76_connac_mcu_rdd_cmd(struct mt76_dev *dev, int cmd, u8 index,
1655 			    u8 rx_sel, u8 val);
1656 #endif /* __MT76_CONNAC_MCU_H */
1657