1 /* 2 * 3 * arch/arm/mach-u300/include/mach/u300-regs.h 4 * 5 * 6 * Copyright (C) 2006-2009 ST-Ericsson AB 7 * License terms: GNU General Public License (GPL) version 2 8 * Basic register address definitions in physical memory and 9 * some block definitions for core devices like the timer. 10 * Author: Linus Walleij <linus.walleij@stericsson.com> 11 */ 12 13 #ifndef __MACH_U300_REGS_H 14 #define __MACH_U300_REGS_H 15 16 /* 17 * These are the large blocks of memory allocated for I/O. 18 * the defines are used for setting up the I/O memory mapping. 19 */ 20 21 /* NAND Flash CS0 */ 22 #define U300_NAND_CS0_PHYS_BASE 0x80000000 23 24 /* NFIF */ 25 #define U300_NAND_IF_PHYS_BASE 0x9f800000 26 27 /* ALE, CLE offset for FSMC NAND */ 28 #define PLAT_NAND_CLE (1 << 16) 29 #define PLAT_NAND_ALE (1 << 17) 30 31 32 /* AHB Peripherals */ 33 #define U300_AHB_PER_PHYS_BASE 0xa0000000 34 #define U300_AHB_PER_VIRT_BASE 0xff010000 35 36 /* FAST Peripherals */ 37 #define U300_FAST_PER_PHYS_BASE 0xc0000000 38 #define U300_FAST_PER_VIRT_BASE 0xff020000 39 40 /* SLOW Peripherals */ 41 #define U300_SLOW_PER_PHYS_BASE 0xc0010000 42 #define U300_SLOW_PER_VIRT_BASE 0xff000000 43 44 /* Boot ROM */ 45 #define U300_BOOTROM_PHYS_BASE 0xffff0000 46 #define U300_BOOTROM_VIRT_BASE 0xffff0000 47 48 /* SEMI config base */ 49 #ifdef CONFIG_MACH_U300_BS335 50 #define U300_SEMI_CONFIG_BASE 0x2FFE0000 51 #else 52 #define U300_SEMI_CONFIG_BASE 0x30000000 53 #endif 54 55 /* 56 * AHB peripherals 57 */ 58 59 /* AHB Peripherals Bridge Controller */ 60 #define U300_AHB_BRIDGE_BASE (U300_AHB_PER_PHYS_BASE+0x0000) 61 62 /* Vectored Interrupt Controller 0, servicing 32 interrupts */ 63 #define U300_INTCON0_BASE (U300_AHB_PER_PHYS_BASE+0x1000) 64 #define U300_INTCON0_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x1000) 65 66 /* Vectored Interrupt Controller 1, servicing 32 interrupts */ 67 #define U300_INTCON1_BASE (U300_AHB_PER_PHYS_BASE+0x2000) 68 #define U300_INTCON1_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x2000) 69 70 /* Memory Stick Pro (MSPRO) controller */ 71 #define U300_MSPRO_BASE (U300_AHB_PER_PHYS_BASE+0x3000) 72 73 /* EMIF Configuration Area */ 74 #define U300_EMIF_CFG_BASE (U300_AHB_PER_PHYS_BASE+0x4000) 75 76 77 /* 78 * FAST peripherals 79 */ 80 81 /* FAST bridge control */ 82 #define U300_FAST_BRIDGE_BASE (U300_FAST_PER_PHYS_BASE+0x0000) 83 84 /* MMC/SD controller */ 85 #define U300_MMCSD_BASE (U300_FAST_PER_PHYS_BASE+0x1000) 86 87 /* PCM I2S0 controller */ 88 #define U300_PCM_I2S0_BASE (U300_FAST_PER_PHYS_BASE+0x2000) 89 90 /* PCM I2S1 controller */ 91 #define U300_PCM_I2S1_BASE (U300_FAST_PER_PHYS_BASE+0x3000) 92 93 /* I2C0 controller */ 94 #define U300_I2C0_BASE (U300_FAST_PER_PHYS_BASE+0x4000) 95 96 /* I2C1 controller */ 97 #define U300_I2C1_BASE (U300_FAST_PER_PHYS_BASE+0x5000) 98 99 /* SPI controller */ 100 #define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000) 101 102 #ifdef CONFIG_MACH_U300_BS335 103 /* Fast UART1 on U335 only */ 104 #define U300_UART1_BASE (U300_FAST_PER_PHYS_BASE+0x7000) 105 #endif 106 107 /* 108 * SLOW peripherals 109 */ 110 111 /* SLOW bridge control */ 112 #define U300_SLOW_BRIDGE_BASE (U300_SLOW_PER_PHYS_BASE) 113 114 /* SYSCON */ 115 #define U300_SYSCON_BASE (U300_SLOW_PER_PHYS_BASE+0x1000) 116 #define U300_SYSCON_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000) 117 118 /* Watchdog */ 119 #define U300_WDOG_BASE (U300_SLOW_PER_PHYS_BASE+0x2000) 120 121 /* UART0 */ 122 #define U300_UART0_BASE (U300_SLOW_PER_PHYS_BASE+0x3000) 123 124 /* APP side special timer */ 125 #define U300_TIMER_APP_BASE (U300_SLOW_PER_PHYS_BASE+0x4000) 126 #define U300_TIMER_APP_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000) 127 128 /* Keypad */ 129 #define U300_KEYPAD_BASE (U300_SLOW_PER_PHYS_BASE+0x5000) 130 131 /* GPIO */ 132 #define U300_GPIO_BASE (U300_SLOW_PER_PHYS_BASE+0x6000) 133 134 /* RTC */ 135 #define U300_RTC_BASE (U300_SLOW_PER_PHYS_BASE+0x7000) 136 137 /* Bus tracer */ 138 #define U300_BUSTR_BASE (U300_SLOW_PER_PHYS_BASE+0x8000) 139 140 /* Event handler (hardware queue) */ 141 #define U300_EVHIST_BASE (U300_SLOW_PER_PHYS_BASE+0x9000) 142 143 /* Genric Timer */ 144 #define U300_TIMER_BASE (U300_SLOW_PER_PHYS_BASE+0xa000) 145 146 /* PPM */ 147 #define U300_PPM_BASE (U300_SLOW_PER_PHYS_BASE+0xb000) 148 149 150 /* 151 * REST peripherals 152 */ 153 154 /* ISP (image signal processor) is only available in U335 */ 155 #ifdef CONFIG_MACH_U300_BS335 156 #define U300_ISP_BASE (0xA0008000) 157 #endif 158 159 /* DMA Controller base */ 160 #define U300_DMAC_BASE (0xC0020000) 161 162 /* MSL Base */ 163 #define U300_MSL_BASE (0xc0022000) 164 165 /* APEX Base */ 166 #define U300_APEX_BASE (0xc0030000) 167 168 /* Video Encoder Base */ 169 #ifdef CONFIG_MACH_U300_BS335 170 #define U300_VIDEOENC_BASE (0xc0080000) 171 #else 172 #define U300_VIDEOENC_BASE (0xc0040000) 173 #endif 174 175 /* XGAM Base */ 176 #define U300_XGAM_BASE (0xd0000000) 177 178 /* 179 * Virtual accessor macros for static devices 180 */ 181 182 #endif 183