1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #ifndef XILINX_LL_TEMAC_H 4 #define XILINX_LL_TEMAC_H 5 6 #include <linux/netdevice.h> 7 #include <linux/of.h> 8 #include <linux/spinlock.h> 9 10 #ifdef CONFIG_PPC_DCR 11 #include <asm/dcr.h> 12 #include <asm/dcr-regs.h> 13 #endif 14 15 /* packet size info */ 16 #define XTE_HDR_SIZE 14 /* size of Ethernet header */ 17 #define XTE_TRL_SIZE 4 /* size of Ethernet trailer (FCS) */ 18 #define XTE_JUMBO_MTU 9000 19 #define XTE_MAX_JUMBO_FRAME_SIZE (XTE_JUMBO_MTU + XTE_HDR_SIZE + XTE_TRL_SIZE) 20 21 /* Configuration options */ 22 23 /* Accept all incoming packets. 24 * This option defaults to disabled (cleared) 25 */ 26 #define XTE_OPTION_PROMISC (1 << 0) 27 /* Jumbo frame support for Tx & Rx. 28 * This option defaults to disabled (cleared) 29 */ 30 #define XTE_OPTION_JUMBO (1 << 1) 31 /* VLAN Rx & Tx frame support. 32 * This option defaults to disabled (cleared) 33 */ 34 #define XTE_OPTION_VLAN (1 << 2) 35 /* Enable recognition of flow control frames on Rx 36 * This option defaults to enabled (set) 37 */ 38 #define XTE_OPTION_FLOW_CONTROL (1 << 4) 39 /* Strip FCS and PAD from incoming frames. 40 * Note: PAD from VLAN frames is not stripped. 41 * This option defaults to disabled (set) 42 */ 43 #define XTE_OPTION_FCS_STRIP (1 << 5) 44 /* Generate FCS field and add PAD automatically for outgoing frames. 45 * This option defaults to enabled (set) 46 */ 47 #define XTE_OPTION_FCS_INSERT (1 << 6) 48 /* Enable Length/Type error checking for incoming frames. When this option is 49 * set, the MAC will filter frames that have a mismatched type/length field 50 * and if XTE_OPTION_REPORT_RXERR is set, the user is notified when these 51 * types of frames are encountered. When this option is cleared, the MAC will 52 * allow these types of frames to be received. 53 * This option defaults to enabled (set) 54 */ 55 #define XTE_OPTION_LENTYPE_ERR (1 << 7) 56 /* Enable the transmitter. 57 * This option defaults to enabled (set) 58 */ 59 #define XTE_OPTION_TXEN (1 << 11) 60 /* Enable the receiver 61 * This option defaults to enabled (set) 62 */ 63 #define XTE_OPTION_RXEN (1 << 12) 64 65 /* Default options set when device is initialized or reset */ 66 #define XTE_OPTION_DEFAULTS \ 67 (XTE_OPTION_TXEN | \ 68 XTE_OPTION_FLOW_CONTROL | \ 69 XTE_OPTION_RXEN) 70 71 /* XPS_LL_TEMAC SDMA registers definition */ 72 73 #define TX_NXTDESC_PTR 0x00 /* r */ 74 #define TX_CURBUF_ADDR 0x01 /* r */ 75 #define TX_CURBUF_LENGTH 0x02 /* r */ 76 #define TX_CURDESC_PTR 0x03 /* rw */ 77 #define TX_TAILDESC_PTR 0x04 /* rw */ 78 #define TX_CHNL_CTRL 0x05 /* rw */ 79 /* 80 * 0:7 24:31 IRQTimeout 81 * 8:15 16:23 IRQCount 82 * 16:20 11:15 Reserved 83 * 21 10 0 84 * 22 9 UseIntOnEnd 85 * 23 8 LdIRQCnt 86 * 24 7 IRQEn 87 * 25:28 3:6 Reserved 88 * 29 2 IrqErrEn 89 * 30 1 IrqDlyEn 90 * 31 0 IrqCoalEn 91 */ 92 #define CHNL_CTRL_IRQ_IOE (1 << 9) 93 #define CHNL_CTRL_IRQ_EN (1 << 7) 94 #define CHNL_CTRL_IRQ_ERR_EN (1 << 2) 95 #define CHNL_CTRL_IRQ_DLY_EN (1 << 1) 96 #define CHNL_CTRL_IRQ_COAL_EN (1 << 0) 97 #define TX_IRQ_REG 0x06 /* rw */ 98 /* 99 * 0:7 24:31 DltTmrValue 100 * 8:15 16:23 ClscCntrValue 101 * 16:17 14:15 Reserved 102 * 18:21 10:13 ClscCnt 103 * 22:23 8:9 DlyCnt 104 * 24:28 3::7 Reserved 105 * 29 2 ErrIrq 106 * 30 1 DlyIrq 107 * 31 0 CoalIrq 108 */ 109 #define TX_CHNL_STS 0x07 /* r */ 110 /* 111 * 0:9 22:31 Reserved 112 * 10 21 TailPErr 113 * 11 20 CmpErr 114 * 12 19 AddrErr 115 * 13 18 NxtPErr 116 * 14 17 CurPErr 117 * 15 16 BsyWr 118 * 16:23 8:15 Reserved 119 * 24 7 Error 120 * 25 6 IOE 121 * 26 5 SOE 122 * 27 4 Cmplt 123 * 28 3 SOP 124 * 29 2 EOP 125 * 30 1 EngBusy 126 * 31 0 Reserved 127 */ 128 129 #define RX_NXTDESC_PTR 0x08 /* r */ 130 #define RX_CURBUF_ADDR 0x09 /* r */ 131 #define RX_CURBUF_LENGTH 0x0a /* r */ 132 #define RX_CURDESC_PTR 0x0b /* rw */ 133 #define RX_TAILDESC_PTR 0x0c /* rw */ 134 #define RX_CHNL_CTRL 0x0d /* rw */ 135 /* 136 * 0:7 24:31 IRQTimeout 137 * 8:15 16:23 IRQCount 138 * 16:20 11:15 Reserved 139 * 21 10 0 140 * 22 9 UseIntOnEnd 141 * 23 8 LdIRQCnt 142 * 24 7 IRQEn 143 * 25:28 3:6 Reserved 144 * 29 2 IrqErrEn 145 * 30 1 IrqDlyEn 146 * 31 0 IrqCoalEn 147 */ 148 #define RX_IRQ_REG 0x0e /* rw */ 149 #define IRQ_COAL (1 << 0) 150 #define IRQ_DLY (1 << 1) 151 #define IRQ_ERR (1 << 2) 152 #define IRQ_DMAERR (1 << 7) /* this is not documented ??? */ 153 /* 154 * 0:7 24:31 DltTmrValue 155 * 8:15 16:23 ClscCntrValue 156 * 16:17 14:15 Reserved 157 * 18:21 10:13 ClscCnt 158 * 22:23 8:9 DlyCnt 159 * 24:28 3::7 Reserved 160 */ 161 #define RX_CHNL_STS 0x0f /* r */ 162 #define CHNL_STS_ENGBUSY (1 << 1) 163 #define CHNL_STS_EOP (1 << 2) 164 #define CHNL_STS_SOP (1 << 3) 165 #define CHNL_STS_CMPLT (1 << 4) 166 #define CHNL_STS_SOE (1 << 5) 167 #define CHNL_STS_IOE (1 << 6) 168 #define CHNL_STS_ERR (1 << 7) 169 170 #define CHNL_STS_BSYWR (1 << 16) 171 #define CHNL_STS_CURPERR (1 << 17) 172 #define CHNL_STS_NXTPERR (1 << 18) 173 #define CHNL_STS_ADDRERR (1 << 19) 174 #define CHNL_STS_CMPERR (1 << 20) 175 #define CHNL_STS_TAILERR (1 << 21) 176 /* 177 * 0:9 22:31 Reserved 178 * 10 21 TailPErr 179 * 11 20 CmpErr 180 * 12 19 AddrErr 181 * 13 18 NxtPErr 182 * 14 17 CurPErr 183 * 15 16 BsyWr 184 * 16:23 8:15 Reserved 185 * 24 7 Error 186 * 25 6 IOE 187 * 26 5 SOE 188 * 27 4 Cmplt 189 * 28 3 SOP 190 * 29 2 EOP 191 * 30 1 EngBusy 192 * 31 0 Reserved 193 */ 194 195 #define DMA_CONTROL_REG 0x10 /* rw */ 196 #define DMA_CONTROL_RST (1 << 0) 197 #define DMA_TAIL_ENABLE (1 << 2) 198 199 /* XPS_LL_TEMAC direct registers definition */ 200 201 #define XTE_RAF0_OFFSET 0x00 202 #define RAF0_RST (1 << 0) 203 #define RAF0_MCSTREJ (1 << 1) 204 #define RAF0_BCSTREJ (1 << 2) 205 #define XTE_TPF0_OFFSET 0x04 206 #define XTE_IFGP0_OFFSET 0x08 207 #define XTE_ISR0_OFFSET 0x0c 208 #define ISR0_HARDACSCMPLT (1 << 0) 209 #define ISR0_AUTONEG (1 << 1) 210 #define ISR0_RXCMPLT (1 << 2) 211 #define ISR0_RXREJ (1 << 3) 212 #define ISR0_RXFIFOOVR (1 << 4) 213 #define ISR0_TXCMPLT (1 << 5) 214 #define ISR0_RXDCMLCK (1 << 6) 215 216 #define XTE_IPR0_OFFSET 0x10 217 #define XTE_IER0_OFFSET 0x14 218 219 #define XTE_MSW0_OFFSET 0x20 220 #define XTE_LSW0_OFFSET 0x24 221 #define XTE_CTL0_OFFSET 0x28 222 #define XTE_RDY0_OFFSET 0x2c 223 224 #define XTE_RSE_MIIM_RR_MASK 0x0002 225 #define XTE_RSE_MIIM_WR_MASK 0x0004 226 #define XTE_RSE_CFG_RR_MASK 0x0020 227 #define XTE_RSE_CFG_WR_MASK 0x0040 228 #define XTE_RDY0_HARD_ACS_RDY_MASK (0x10000) 229 230 /* XPS_LL_TEMAC indirect registers offset definition */ 231 232 #define XTE_RXC0_OFFSET 0x00000200 /* Rx configuration word 0 */ 233 #define XTE_RXC1_OFFSET 0x00000240 /* Rx configuration word 1 */ 234 #define XTE_RXC1_RXRST_MASK (1 << 31) /* Receiver reset */ 235 #define XTE_RXC1_RXJMBO_MASK (1 << 30) /* Jumbo frame enable */ 236 #define XTE_RXC1_RXFCS_MASK (1 << 29) /* FCS not stripped */ 237 #define XTE_RXC1_RXEN_MASK (1 << 28) /* Receiver enable */ 238 #define XTE_RXC1_RXVLAN_MASK (1 << 27) /* VLAN enable */ 239 #define XTE_RXC1_RXHD_MASK (1 << 26) /* Half duplex */ 240 #define XTE_RXC1_RXLT_MASK (1 << 25) /* Length/type check disable */ 241 242 #define XTE_TXC_OFFSET 0x00000280 /* Tx configuration */ 243 #define XTE_TXC_TXRST_MASK (1 << 31) /* Transmitter reset */ 244 #define XTE_TXC_TXJMBO_MASK (1 << 30) /* Jumbo frame enable */ 245 #define XTE_TXC_TXFCS_MASK (1 << 29) /* Generate FCS */ 246 #define XTE_TXC_TXEN_MASK (1 << 28) /* Transmitter enable */ 247 #define XTE_TXC_TXVLAN_MASK (1 << 27) /* VLAN enable */ 248 #define XTE_TXC_TXHD_MASK (1 << 26) /* Half duplex */ 249 250 #define XTE_FCC_OFFSET 0x000002C0 /* Flow control config */ 251 #define XTE_FCC_RXFLO_MASK (1 << 29) /* Rx flow control enable */ 252 #define XTE_FCC_TXFLO_MASK (1 << 30) /* Tx flow control enable */ 253 254 #define XTE_EMCFG_OFFSET 0x00000300 /* EMAC configuration */ 255 #define XTE_EMCFG_LINKSPD_MASK 0xC0000000 /* Link speed */ 256 #define XTE_EMCFG_HOSTEN_MASK (1 << 26) /* Host interface enable */ 257 #define XTE_EMCFG_LINKSPD_10 0x00000000 /* 10 Mbit LINKSPD_MASK */ 258 #define XTE_EMCFG_LINKSPD_100 (1 << 30) /* 100 Mbit LINKSPD_MASK */ 259 #define XTE_EMCFG_LINKSPD_1000 (1 << 31) /* 1000 Mbit LINKSPD_MASK */ 260 261 #define XTE_GMIC_OFFSET 0x00000320 /* RGMII/SGMII config */ 262 #define XTE_MC_OFFSET 0x00000340 /* MDIO configuration */ 263 #define XTE_UAW0_OFFSET 0x00000380 /* Unicast address word 0 */ 264 #define XTE_UAW1_OFFSET 0x00000384 /* Unicast address word 1 */ 265 266 #define XTE_MAW0_OFFSET 0x00000388 /* Multicast addr word 0 */ 267 #define XTE_MAW1_OFFSET 0x0000038C /* Multicast addr word 1 */ 268 #define XTE_AFM_OFFSET 0x00000390 /* Promiscuous mode */ 269 #define XTE_AFM_EPPRM_MASK (1 << 31) /* Promiscuous mode enable */ 270 271 /* Interrupt Request status */ 272 #define XTE_TIS_OFFSET 0x000003A0 273 #define TIS_FRIS (1 << 0) 274 #define TIS_MRIS (1 << 1) 275 #define TIS_MWIS (1 << 2) 276 #define TIS_ARIS (1 << 3) 277 #define TIS_AWIS (1 << 4) 278 #define TIS_CRIS (1 << 5) 279 #define TIS_CWIS (1 << 6) 280 281 #define XTE_TIE_OFFSET 0x000003A4 /* Interrupt enable */ 282 283 /* MII Management Control register (MGTCR) */ 284 #define XTE_MGTDR_OFFSET 0x000003B0 /* MII data */ 285 #define XTE_MIIMAI_OFFSET 0x000003B4 /* MII control */ 286 287 #define CNTLREG_WRITE_ENABLE_MASK 0x8000 288 #define CNTLREG_EMAC1SEL_MASK 0x0400 289 #define CNTLREG_ADDRESSCODE_MASK 0x03ff 290 291 /* CDMAC descriptor status bit definitions */ 292 293 #define STS_CTRL_APP0_ERR (1 << 31) 294 #define STS_CTRL_APP0_IRQONEND (1 << 30) 295 /* undocumented */ 296 #define STS_CTRL_APP0_STOPONEND (1 << 29) 297 #define STS_CTRL_APP0_CMPLT (1 << 28) 298 #define STS_CTRL_APP0_SOP (1 << 27) 299 #define STS_CTRL_APP0_EOP (1 << 26) 300 #define STS_CTRL_APP0_ENGBUSY (1 << 25) 301 /* undocumented */ 302 #define STS_CTRL_APP0_ENGRST (1 << 24) 303 304 #define TX_CONTROL_CALC_CSUM_MASK 1 305 306 #define MULTICAST_CAM_TABLE_NUM 4 307 308 /* TEMAC Synthesis features */ 309 #define TEMAC_FEATURE_RX_CSUM (1 << 0) 310 #define TEMAC_FEATURE_TX_CSUM (1 << 1) 311 312 /* TX/RX CURDESC_PTR points to first descriptor */ 313 /* TX/RX TAILDESC_PTR points to last descriptor in linked list */ 314 315 /** 316 * struct cdmac_bd - LocalLink buffer descriptor format 317 * 318 * app0 bits: 319 * 0 Error 320 * 1 IrqOnEnd generate an interrupt at completion of DMA op 321 * 2 reserved 322 * 3 completed Current descriptor completed 323 * 4 SOP TX - marks first desc/ RX marks first desct 324 * 5 EOP TX marks last desc/RX marks last desc 325 * 6 EngBusy DMA is processing 326 * 7 reserved 327 * 8:31 application specific 328 */ 329 struct cdmac_bd { 330 u32 next; /* Physical address of next buffer descriptor */ 331 u32 phys; 332 u32 len; 333 u32 app0; 334 u32 app1; /* TX start << 16 | insert */ 335 u32 app2; /* TX csum */ 336 u32 app3; 337 u32 app4; /* skb for TX length for RX */ 338 }; 339 340 struct temac_local { 341 struct net_device *ndev; 342 struct device *dev; 343 344 /* Connection to PHY device */ 345 struct device_node *phy_node; 346 /* For non-device-tree devices */ 347 char phy_name[MII_BUS_ID_SIZE + 3]; 348 phy_interface_t phy_interface; 349 350 /* MDIO bus data */ 351 struct mii_bus *mii_bus; /* MII bus reference */ 352 353 /* IO registers, dma functions and IRQs */ 354 void __iomem *regs; 355 void __iomem *sdma_regs; 356 #ifdef CONFIG_PPC_DCR 357 dcr_host_t sdma_dcrs; 358 #endif 359 u32 (*temac_ior)(struct temac_local *lp, int offset); 360 void (*temac_iow)(struct temac_local *lp, int offset, u32 value); 361 u32 (*dma_in)(struct temac_local *lp, int reg); 362 void (*dma_out)(struct temac_local *lp, int reg, u32 value); 363 364 int tx_irq; 365 int rx_irq; 366 int emac_num; 367 368 struct sk_buff **rx_skb; 369 spinlock_t rx_lock; 370 /* For synchronization of indirect register access. Must be 371 * shared mutex between interfaces in same TEMAC block. 372 */ 373 spinlock_t *indirect_lock; 374 u32 options; /* Current options word */ 375 int last_link; 376 unsigned int temac_features; 377 378 /* Buffer descriptors */ 379 struct cdmac_bd *tx_bd_v; 380 dma_addr_t tx_bd_p; 381 u32 tx_bd_num; 382 struct cdmac_bd *rx_bd_v; 383 dma_addr_t rx_bd_p; 384 u32 rx_bd_num; 385 int tx_bd_ci; 386 int tx_bd_tail; 387 int rx_bd_ci; 388 int rx_bd_tail; 389 390 /* DMA channel control setup */ 391 u8 coalesce_count_tx; 392 u8 coalesce_delay_tx; 393 u8 coalesce_count_rx; 394 u8 coalesce_delay_rx; 395 396 struct delayed_work restart_work; 397 }; 398 399 /* Wrappers for temac_ior()/temac_iow() function pointers above */ 400 #define temac_ior(lp, o) ((lp)->temac_ior(lp, o)) 401 #define temac_iow(lp, o, v) ((lp)->temac_iow(lp, o, v)) 402 403 /* xilinx_temac.c */ 404 int temac_indirect_busywait(struct temac_local *lp); 405 u32 temac_indirect_in32(struct temac_local *lp, int reg); 406 u32 temac_indirect_in32_locked(struct temac_local *lp, int reg); 407 void temac_indirect_out32(struct temac_local *lp, int reg, u32 value); 408 void temac_indirect_out32_locked(struct temac_local *lp, int reg, u32 value); 409 410 /* xilinx_temac_mdio.c */ 411 int temac_mdio_setup(struct temac_local *lp, struct platform_device *pdev); 412 void temac_mdio_teardown(struct temac_local *lp); 413 414 #endif /* XILINX_LL_TEMAC_H */ 415