1 /*
2 * Copyright (c) 2001-2002 by David Brownell
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19 #ifndef __LINUX_USB_EHCI_DEF_H
20 #define __LINUX_USB_EHCI_DEF_H
21
22 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
23
24 /* Section 2.2 Host Controller Capability Registers */
25 struct ehci_caps {
26 /* these fields are specified as 8 and 16 bit registers,
27 * but some hosts can't perform 8 or 16 bit PCI accesses.
28 */
29 u32 hc_capbase;
30 #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
31 #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
32 u32 hcs_params; /* HCSPARAMS - offset 0x4 */
33 #define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */
34 #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
35 #define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
36 #define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */
37 #define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */
38 #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
39 #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
40
41 u32 hcc_params; /* HCCPARAMS - offset 0x8 */
42 /* EHCI 1.1 addendum */
43 #define HCC_32FRAME_PERIODIC_LIST(p) ((p)&(1 << 19))
44 #define HCC_PER_PORT_CHANGE_EVENT(p) ((p)&(1 << 18))
45 #define HCC_LPM(p) ((p)&(1 << 17))
46 #define HCC_HW_PREFETCH(p) ((p)&(1 << 16))
47
48 #define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */
49 #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
50 #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
51 #define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
52 #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
53 #define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */
54 u8 portroute[8]; /* nibbles for routing - offset 0xC */
55 } __attribute__ ((packed));
56
57
58 /* Section 2.3 Host Controller Operational Registers */
59 struct ehci_regs {
60
61 /* USBCMD: offset 0x00 */
62 u32 command;
63
64 /* EHCI 1.1 addendum */
65 #define CMD_HIRD (0xf<<24) /* host initiated resume duration */
66 #define CMD_PPCEE (1<<15) /* per port change event enable */
67 #define CMD_FSP (1<<14) /* fully synchronized prefetch */
68 #define CMD_ASPE (1<<13) /* async schedule prefetch enable */
69 #define CMD_PSPE (1<<12) /* periodic schedule prefetch enable */
70 /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
71 #define CMD_PARK (1<<11) /* enable "park" on async qh */
72 #define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
73 #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
74 #define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
75 #define CMD_ASE (1<<5) /* async schedule enable */
76 #define CMD_PSE (1<<4) /* periodic schedule enable */
77 /* 3:2 is periodic frame list size */
78 #define CMD_RESET (1<<1) /* reset HC not bus */
79 #define CMD_RUN (1<<0) /* start/stop HC */
80
81 /* USBSTS: offset 0x04 */
82 u32 status;
83 #define STS_PPCE_MASK (0xff<<16) /* Per-Port change event 1-16 */
84 #define STS_ASS (1<<15) /* Async Schedule Status */
85 #define STS_PSS (1<<14) /* Periodic Schedule Status */
86 #define STS_RECL (1<<13) /* Reclamation */
87 #define STS_HALT (1<<12) /* Not running (any reason) */
88 /* some bits reserved */
89 /* these STS_* flags are also intr_enable bits (USBINTR) */
90 #define STS_IAA (1<<5) /* Interrupted on async advance */
91 #define STS_FATAL (1<<4) /* such as some PCI access errors */
92 #define STS_FLR (1<<3) /* frame list rolled over */
93 #define STS_PCD (1<<2) /* port change detect */
94 #define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
95 #define STS_INT (1<<0) /* "normal" completion (short, ...) */
96
97 /* USBINTR: offset 0x08 */
98 u32 intr_enable;
99
100 /* FRINDEX: offset 0x0C */
101 u32 frame_index; /* current microframe number */
102 /* CTRLDSSEGMENT: offset 0x10 */
103 u32 segment; /* address bits 63:32 if needed */
104 /* PERIODICLISTBASE: offset 0x14 */
105 u32 frame_list; /* points to periodic list */
106 /* ASYNCLISTADDR: offset 0x18 */
107 u32 async_next; /* address of next async queue head */
108
109 u32 reserved[9];
110
111 /* CONFIGFLAG: offset 0x40 */
112 u32 configured_flag;
113 #define FLAG_CF (1<<0) /* true: we'll support "high speed" */
114
115 /* PORTSC: offset 0x44 */
116 u32 port_status[0]; /* up to N_PORTS */
117 /* EHCI 1.1 addendum */
118 #define PORTSC_SUSPEND_STS_ACK 0
119 #define PORTSC_SUSPEND_STS_NYET 1
120 #define PORTSC_SUSPEND_STS_STALL 2
121 #define PORTSC_SUSPEND_STS_ERR 3
122
123 #define PORT_DEV_ADDR (0x7f<<25) /* device address */
124 #define PORT_SSTS (0x3<<23) /* suspend status */
125 /* 31:23 reserved */
126 #define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */
127 #define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */
128 #define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */
129 /* 19:16 for port testing */
130 #define PORT_TEST(x) (((x)&0xf)<<16) /* Port Test Control */
131 #define PORT_TEST_PKT PORT_TEST(0x4) /* Port Test Control - packet test */
132 #define PORT_TEST_FORCE PORT_TEST(0x5) /* Port Test Control - force enable */
133 #define PORT_LED_OFF (0<<14)
134 #define PORT_LED_AMBER (1<<14)
135 #define PORT_LED_GREEN (2<<14)
136 #define PORT_LED_MASK (3<<14)
137 #define PORT_OWNER (1<<13) /* true: companion hc owns this port */
138 #define PORT_POWER (1<<12) /* true: has power (see PPC) */
139 #define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */
140 /* 11:10 for detecting lowspeed devices (reset vs release ownership) */
141 /* 9 reserved */
142 #define PORT_LPM (1<<9) /* LPM transaction */
143 #define PORT_RESET (1<<8) /* reset port */
144 #define PORT_SUSPEND (1<<7) /* suspend port */
145 #define PORT_RESUME (1<<6) /* resume it */
146 #define PORT_OCC (1<<5) /* over current change */
147 #define PORT_OC (1<<4) /* over current active */
148 #define PORT_PEC (1<<3) /* port enable change */
149 #define PORT_PE (1<<2) /* port enable */
150 #define PORT_CSC (1<<1) /* connect status change */
151 #define PORT_CONNECT (1<<0) /* device connected */
152 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
153 } __attribute__ ((packed));
154
155 #define USBMODE 0x68 /* USB Device mode */
156 #define USBMODE_SDIS (1<<3) /* Stream disable */
157 #define USBMODE_BE (1<<2) /* BE/LE endianness select */
158 #define USBMODE_CM_HC (3<<0) /* host controller mode */
159 #define USBMODE_CM_IDLE (0<<0) /* idle state */
160
161 /* Moorestown has some non-standard registers, partially due to the fact that
162 * its EHCI controller has both TT and LPM support. HOSTPCx are extensions to
163 * PORTSCx
164 */
165 #define HOSTPC0 0x84 /* HOSTPC extension */
166 #define HOSTPC_PHCD (1<<22) /* Phy clock disable */
167 #define HOSTPC_PSPD (3<<25) /* Port speed detection */
168 #define USBMODE_EX 0xc8 /* USB Device mode extension */
169 #define USBMODE_EX_VBPS (1<<5) /* VBus Power Select On */
170 #define USBMODE_EX_HC (3<<0) /* host controller mode */
171 #define TXFILLTUNING 0x24 /* TX FIFO Tuning register */
172 #define TXFIFO_DEFAULT (8<<16) /* FIFO burst threshold 8 */
173
174 /* Appendix C, Debug port ... intended for use with special "debug devices"
175 * that can help if there's no serial console. (nonstandard enumeration.)
176 */
177 struct ehci_dbg_port {
178 u32 control;
179 #define DBGP_OWNER (1<<30)
180 #define DBGP_ENABLED (1<<28)
181 #define DBGP_DONE (1<<16)
182 #define DBGP_INUSE (1<<10)
183 #define DBGP_ERRCODE(x) (((x)>>7)&0x07)
184 # define DBGP_ERR_BAD 1
185 # define DBGP_ERR_SIGNAL 2
186 #define DBGP_ERROR (1<<6)
187 #define DBGP_GO (1<<5)
188 #define DBGP_OUT (1<<4)
189 #define DBGP_LEN(x) (((x)>>0)&0x0f)
190 u32 pids;
191 #define DBGP_PID_GET(x) (((x)>>16)&0xff)
192 #define DBGP_PID_SET(data, tok) (((data)<<8)|(tok))
193 u32 data03;
194 u32 data47;
195 u32 address;
196 #define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep))
197 } __attribute__ ((packed));
198
199 #ifdef CONFIG_EARLY_PRINTK_DBGP
200 #include <linux/init.h>
201 extern int __init early_dbgp_init(char *s);
202 extern struct console early_dbgp_console;
203 #endif /* CONFIG_EARLY_PRINTK_DBGP */
204
205 #ifdef CONFIG_EARLY_PRINTK_DBGP
206 /* Call backs from ehci host driver to ehci debug driver */
207 extern int dbgp_external_startup(void);
208 extern int dbgp_reset_prep(void);
209 #else
dbgp_reset_prep(void)210 static inline int dbgp_reset_prep(void)
211 {
212 return 1;
213 }
dbgp_external_startup(void)214 static inline int dbgp_external_startup(void)
215 {
216 return -1;
217 }
218 #endif
219
220 #endif /* __LINUX_USB_EHCI_DEF_H */
221