1 /*
2  * Definitions for TUSB6010 USB 2.0 OTG Dual Role controller
3  *
4  * Copyright (C) 2006 Nokia Corporation
5  * Tony Lindgren <tony@atomide.com>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11 
12 #ifndef __TUSB6010_H__
13 #define __TUSB6010_H__
14 
15 extern u8 tusb_get_revision(struct musb *musb);
16 
17 #ifdef CONFIG_USB_TUSB6010
18 #define musb_in_tusb()			1
19 #else
20 #define musb_in_tusb()			0
21 #endif
22 
23 #ifdef CONFIG_USB_TUSB_OMAP_DMA
24 #define tusb_dma_omap()			1
25 #else
26 #define tusb_dma_omap()			0
27 #endif
28 
29 /* VLYNQ control register. 32-bit at offset 0x000 */
30 #define TUSB_VLYNQ_CTRL			0x004
31 
32 /* Mentor Graphics OTG core registers. 8,- 16- and 32-bit at offset 0x400 */
33 #define TUSB_BASE_OFFSET		0x400
34 
35 /* FIFO registers 32-bit at offset 0x600 */
36 #define TUSB_FIFO_BASE			0x600
37 
38 /* Device System & Control registers. 32-bit at offset 0x800 */
39 #define TUSB_SYS_REG_BASE		0x800
40 
41 #define TUSB_DEV_CONF			(TUSB_SYS_REG_BASE + 0x000)
42 #define		TUSB_DEV_CONF_USB_HOST_MODE		(1 << 16)
43 #define		TUSB_DEV_CONF_PROD_TEST_MODE		(1 << 15)
44 #define		TUSB_DEV_CONF_SOFT_ID			(1 << 1)
45 #define		TUSB_DEV_CONF_ID_SEL			(1 << 0)
46 
47 #define TUSB_PHY_OTG_CTRL_ENABLE	(TUSB_SYS_REG_BASE + 0x004)
48 #define TUSB_PHY_OTG_CTRL		(TUSB_SYS_REG_BASE + 0x008)
49 #define		TUSB_PHY_OTG_CTRL_WRPROTECT		(0xa5 << 24)
50 #define		TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP		(1 << 23)
51 #define		TUSB_PHY_OTG_CTRL_OTG_VBUS_DET_EN	(1 << 19)
52 #define		TUSB_PHY_OTG_CTRL_OTG_SESS_END_EN	(1 << 18)
53 #define		TUSB_PHY_OTG_CTRL_TESTM2		(1 << 17)
54 #define		TUSB_PHY_OTG_CTRL_TESTM1		(1 << 16)
55 #define		TUSB_PHY_OTG_CTRL_TESTM0		(1 << 15)
56 #define		TUSB_PHY_OTG_CTRL_TX_DATA2		(1 << 14)
57 #define		TUSB_PHY_OTG_CTRL_TX_GZ2		(1 << 13)
58 #define		TUSB_PHY_OTG_CTRL_TX_ENABLE2		(1 << 12)
59 #define		TUSB_PHY_OTG_CTRL_DM_PULLDOWN		(1 << 11)
60 #define		TUSB_PHY_OTG_CTRL_DP_PULLDOWN		(1 << 10)
61 #define		TUSB_PHY_OTG_CTRL_OSC_EN		(1 << 9)
62 #define		TUSB_PHY_OTG_CTRL_PHYREF_CLKSEL(v)	(((v) & 3) << 7)
63 #define		TUSB_PHY_OTG_CTRL_PD			(1 << 6)
64 #define		TUSB_PHY_OTG_CTRL_PLL_ON		(1 << 5)
65 #define		TUSB_PHY_OTG_CTRL_EXT_RPU		(1 << 4)
66 #define		TUSB_PHY_OTG_CTRL_PWR_GOOD		(1 << 3)
67 #define		TUSB_PHY_OTG_CTRL_RESET			(1 << 2)
68 #define		TUSB_PHY_OTG_CTRL_SUSPENDM		(1 << 1)
69 #define		TUSB_PHY_OTG_CTRL_CLK_MODE		(1 << 0)
70 
71 /*OTG status register */
72 #define TUSB_DEV_OTG_STAT		(TUSB_SYS_REG_BASE + 0x00c)
73 #define		TUSB_DEV_OTG_STAT_PWR_CLK_GOOD		(1 << 8)
74 #define		TUSB_DEV_OTG_STAT_SESS_END		(1 << 7)
75 #define		TUSB_DEV_OTG_STAT_SESS_VALID		(1 << 6)
76 #define		TUSB_DEV_OTG_STAT_VBUS_VALID		(1 << 5)
77 #define		TUSB_DEV_OTG_STAT_VBUS_SENSE		(1 << 4)
78 #define		TUSB_DEV_OTG_STAT_ID_STATUS		(1 << 3)
79 #define		TUSB_DEV_OTG_STAT_HOST_DISCON		(1 << 2)
80 #define		TUSB_DEV_OTG_STAT_LINE_STATE		(3 << 0)
81 #define		TUSB_DEV_OTG_STAT_DP_ENABLE		(1 << 1)
82 #define		TUSB_DEV_OTG_STAT_DM_ENABLE		(1 << 0)
83 
84 #define TUSB_DEV_OTG_TIMER		(TUSB_SYS_REG_BASE + 0x010)
85 #	define TUSB_DEV_OTG_TIMER_ENABLE		(1 << 31)
86 #	define TUSB_DEV_OTG_TIMER_VAL(v)		((v) & 0x07ffffff)
87 #define TUSB_PRCM_REV			(TUSB_SYS_REG_BASE + 0x014)
88 
89 /* PRCM configuration register */
90 #define TUSB_PRCM_CONF			(TUSB_SYS_REG_BASE + 0x018)
91 #define		TUSB_PRCM_CONF_SFW_CPEN		(1 << 24)
92 #define		TUSB_PRCM_CONF_SYS_CLKSEL(v)	(((v) & 3) << 16)
93 
94 /* PRCM management register */
95 #define TUSB_PRCM_MNGMT			(TUSB_SYS_REG_BASE + 0x01c)
96 #define		TUSB_PRCM_MNGMT_SRP_FIX_TIMER(v)	(((v) & 0xf) << 25)
97 #define		TUSB_PRCM_MNGMT_SRP_FIX_EN		(1 << 24)
98 #define		TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(v)	(((v) & 0xf) << 20)
99 #define		TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN	(1 << 19)
100 #define		TUSB_PRCM_MNGMT_DFT_CLK_DIS		(1 << 18)
101 #define		TUSB_PRCM_MNGMT_VLYNQ_CLK_DIS		(1 << 17)
102 #define		TUSB_PRCM_MNGMT_OTG_SESS_END_EN		(1 << 10)
103 #define		TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN		(1 << 9)
104 #define		TUSB_PRCM_MNGMT_OTG_ID_PULLUP		(1 << 8)
105 #define		TUSB_PRCM_MNGMT_15_SW_EN		(1 << 4)
106 #define		TUSB_PRCM_MNGMT_33_SW_EN		(1 << 3)
107 #define		TUSB_PRCM_MNGMT_5V_CPEN			(1 << 2)
108 #define		TUSB_PRCM_MNGMT_PM_IDLE			(1 << 1)
109 #define		TUSB_PRCM_MNGMT_DEV_IDLE		(1 << 0)
110 
111 /* Wake-up source clear and mask registers */
112 #define TUSB_PRCM_WAKEUP_SOURCE		(TUSB_SYS_REG_BASE + 0x020)
113 #define TUSB_PRCM_WAKEUP_CLEAR		(TUSB_SYS_REG_BASE + 0x028)
114 #define TUSB_PRCM_WAKEUP_MASK		(TUSB_SYS_REG_BASE + 0x02c)
115 #define		TUSB_PRCM_WAKEUP_RESERVED_BITS	(0xffffe << 13)
116 #define		TUSB_PRCM_WGPIO_7	(1 << 12)
117 #define		TUSB_PRCM_WGPIO_6	(1 << 11)
118 #define		TUSB_PRCM_WGPIO_5	(1 << 10)
119 #define		TUSB_PRCM_WGPIO_4	(1 << 9)
120 #define		TUSB_PRCM_WGPIO_3	(1 << 8)
121 #define		TUSB_PRCM_WGPIO_2	(1 << 7)
122 #define		TUSB_PRCM_WGPIO_1	(1 << 6)
123 #define		TUSB_PRCM_WGPIO_0	(1 << 5)
124 #define		TUSB_PRCM_WHOSTDISCON	(1 << 4)	/* Host disconnect */
125 #define		TUSB_PRCM_WBUS		(1 << 3)	/* USB bus resume */
126 #define		TUSB_PRCM_WNORCS	(1 << 2)	/* NOR chip select */
127 #define		TUSB_PRCM_WVBUS		(1 << 1)	/* OTG PHY VBUS */
128 #define		TUSB_PRCM_WID		(1 << 0)	/* OTG PHY ID detect */
129 
130 #define TUSB_PULLUP_1_CTRL		(TUSB_SYS_REG_BASE + 0x030)
131 #define TUSB_PULLUP_2_CTRL		(TUSB_SYS_REG_BASE + 0x034)
132 #define TUSB_INT_CTRL_REV		(TUSB_SYS_REG_BASE + 0x038)
133 #define TUSB_INT_CTRL_CONF		(TUSB_SYS_REG_BASE + 0x03c)
134 #define TUSB_USBIP_INT_SRC		(TUSB_SYS_REG_BASE + 0x040)
135 #define TUSB_USBIP_INT_SET		(TUSB_SYS_REG_BASE + 0x044)
136 #define TUSB_USBIP_INT_CLEAR		(TUSB_SYS_REG_BASE + 0x048)
137 #define TUSB_USBIP_INT_MASK		(TUSB_SYS_REG_BASE + 0x04c)
138 #define TUSB_DMA_INT_SRC		(TUSB_SYS_REG_BASE + 0x050)
139 #define TUSB_DMA_INT_SET		(TUSB_SYS_REG_BASE + 0x054)
140 #define TUSB_DMA_INT_CLEAR		(TUSB_SYS_REG_BASE + 0x058)
141 #define TUSB_DMA_INT_MASK		(TUSB_SYS_REG_BASE + 0x05c)
142 #define TUSB_GPIO_INT_SRC		(TUSB_SYS_REG_BASE + 0x060)
143 #define TUSB_GPIO_INT_SET		(TUSB_SYS_REG_BASE + 0x064)
144 #define TUSB_GPIO_INT_CLEAR		(TUSB_SYS_REG_BASE + 0x068)
145 #define TUSB_GPIO_INT_MASK		(TUSB_SYS_REG_BASE + 0x06c)
146 
147 /* NOR flash interrupt source registers */
148 #define TUSB_INT_SRC			(TUSB_SYS_REG_BASE + 0x070)
149 #define TUSB_INT_SRC_SET		(TUSB_SYS_REG_BASE + 0x074)
150 #define TUSB_INT_SRC_CLEAR		(TUSB_SYS_REG_BASE + 0x078)
151 #define TUSB_INT_MASK			(TUSB_SYS_REG_BASE + 0x07c)
152 #define		TUSB_INT_SRC_TXRX_DMA_DONE		(1 << 24)
153 #define		TUSB_INT_SRC_USB_IP_CORE		(1 << 17)
154 #define		TUSB_INT_SRC_OTG_TIMEOUT		(1 << 16)
155 #define		TUSB_INT_SRC_VBUS_SENSE_CHNG		(1 << 15)
156 #define		TUSB_INT_SRC_ID_STATUS_CHNG		(1 << 14)
157 #define		TUSB_INT_SRC_DEV_WAKEUP			(1 << 13)
158 #define		TUSB_INT_SRC_DEV_READY			(1 << 12)
159 #define		TUSB_INT_SRC_USB_IP_TX			(1 << 9)
160 #define		TUSB_INT_SRC_USB_IP_RX			(1 << 8)
161 #define		TUSB_INT_SRC_USB_IP_VBUS_ERR		(1 << 7)
162 #define		TUSB_INT_SRC_USB_IP_VBUS_REQ		(1 << 6)
163 #define		TUSB_INT_SRC_USB_IP_DISCON		(1 << 5)
164 #define		TUSB_INT_SRC_USB_IP_CONN		(1 << 4)
165 #define		TUSB_INT_SRC_USB_IP_SOF			(1 << 3)
166 #define		TUSB_INT_SRC_USB_IP_RST_BABBLE		(1 << 2)
167 #define		TUSB_INT_SRC_USB_IP_RESUME		(1 << 1)
168 #define		TUSB_INT_SRC_USB_IP_SUSPEND		(1 << 0)
169 
170 /* NOR flash interrupt registers reserved bits. Must be written as 0 */
171 #define		TUSB_INT_MASK_RESERVED_17		(0x3fff << 17)
172 #define		TUSB_INT_MASK_RESERVED_13		(1 << 13)
173 #define		TUSB_INT_MASK_RESERVED_8		(0xf << 8)
174 #define		TUSB_INT_SRC_RESERVED_26		(0x1f << 26)
175 #define		TUSB_INT_SRC_RESERVED_18		(0x3f << 18)
176 #define		TUSB_INT_SRC_RESERVED_10		(0x03 << 10)
177 
178 /* Reserved bits for NOR flash interrupt mask and clear register */
179 #define		TUSB_INT_MASK_RESERVED_BITS	(TUSB_INT_MASK_RESERVED_17 | \
180 						TUSB_INT_MASK_RESERVED_13 | \
181 						TUSB_INT_MASK_RESERVED_8)
182 
183 /* Reserved bits for NOR flash interrupt status register */
184 #define		TUSB_INT_SRC_RESERVED_BITS	(TUSB_INT_SRC_RESERVED_26 | \
185 						TUSB_INT_SRC_RESERVED_18 | \
186 						TUSB_INT_SRC_RESERVED_10)
187 
188 #define TUSB_GPIO_REV			(TUSB_SYS_REG_BASE + 0x080)
189 #define TUSB_GPIO_CONF			(TUSB_SYS_REG_BASE + 0x084)
190 #define TUSB_DMA_CTRL_REV		(TUSB_SYS_REG_BASE + 0x100)
191 #define TUSB_DMA_REQ_CONF		(TUSB_SYS_REG_BASE + 0x104)
192 #define TUSB_EP0_CONF			(TUSB_SYS_REG_BASE + 0x108)
193 #define TUSB_DMA_EP_MAP			(TUSB_SYS_REG_BASE + 0x148)
194 
195 /* Offsets from each ep base register */
196 #define TUSB_EP_TX_OFFSET		0x10c	/* EP_IN in docs */
197 #define TUSB_EP_RX_OFFSET		0x14c	/* EP_OUT in docs */
198 #define TUSB_EP_MAX_PACKET_SIZE_OFFSET	0x188
199 
200 #define TUSB_WAIT_COUNT			(TUSB_SYS_REG_BASE + 0x1c8)
201 #define TUSB_SCRATCH_PAD		(TUSB_SYS_REG_BASE + 0x1c4)
202 #define TUSB_PROD_TEST_RESET		(TUSB_SYS_REG_BASE + 0x1d8)
203 
204 /* Device System & Control register bitfields */
205 #define TUSB_INT_CTRL_CONF_INT_RELCYC(v)	(((v) & 0x7) << 18)
206 #define TUSB_INT_CTRL_CONF_INT_POLARITY		(1 << 17)
207 #define TUSB_INT_CTRL_CONF_INT_MODE		(1 << 16)
208 #define TUSB_GPIO_CONF_DMAREQ(v)		(((v) & 0x3f) << 24)
209 #define TUSB_DMA_REQ_CONF_BURST_SIZE(v)		(((v) & 3) << 26)
210 #define TUSB_DMA_REQ_CONF_DMA_REQ_EN(v)		(((v) & 0x3f) << 20)
211 #define TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(v)	(((v) & 0xf) << 16)
212 #define TUSB_EP0_CONFIG_SW_EN			(1 << 8)
213 #define TUSB_EP0_CONFIG_DIR_TX			(1 << 7)
214 #define TUSB_EP0_CONFIG_XFR_SIZE(v)		((v) & 0x7f)
215 #define TUSB_EP_CONFIG_SW_EN			(1 << 31)
216 #define TUSB_EP_CONFIG_XFR_SIZE(v)		((v) & 0x7fffffff)
217 #define TUSB_PROD_TEST_RESET_VAL		0xa596
218 #define TUSB_EP_FIFO(ep)			(TUSB_FIFO_BASE + (ep) * 0x20)
219 
220 #define TUSB_DIDR1_LO				(TUSB_SYS_REG_BASE + 0x1f8)
221 #define TUSB_DIDR1_HI				(TUSB_SYS_REG_BASE + 0x1fc)
222 #define		TUSB_DIDR1_HI_CHIP_REV(v)		(((v) >> 17) & 0xf)
223 #define			TUSB_DIDR1_HI_REV_20		0
224 #define			TUSB_DIDR1_HI_REV_30		1
225 #define			TUSB_DIDR1_HI_REV_31		2
226 
227 #define TUSB_REV_10	0x10
228 #define TUSB_REV_20	0x20
229 #define TUSB_REV_30	0x30
230 #define TUSB_REV_31	0x31
231 
232 #endif /* __TUSB6010_H__ */
233