1 /* 2 * Tsi721 PCIExpress-to-SRIO bridge definitions 3 * 4 * Copyright 2011, Integrated Device Technology, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the Free 8 * Software Foundation; either version 2 of the License, or (at your option) 9 * any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program; if not, write to the Free Software Foundation, Inc., 59 18 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 */ 20 21 #ifndef __TSI721_H 22 #define __TSI721_H 23 24 #define DRV_NAME "tsi721" 25 26 #define DEFAULT_HOPCOUNT 0xff 27 #define DEFAULT_DESTID 0xff 28 29 /* PCI device ID */ 30 #define PCI_DEVICE_ID_TSI721 0x80ab 31 32 #define BAR_0 0 33 #define BAR_1 1 34 #define BAR_2 2 35 #define BAR_4 4 36 37 #define TSI721_PC2SR_BARS 2 38 #define TSI721_PC2SR_WINS 8 39 #define TSI721_PC2SR_ZONES 8 40 #define TSI721_MAINT_WIN 0 /* Window for outbound maintenance requests */ 41 #define IDB_QUEUE 0 /* Inbound Doorbell Queue to use */ 42 #define IDB_QSIZE 512 /* Inbound Doorbell Queue size */ 43 44 /* Memory space sizes */ 45 #define TSI721_REG_SPACE_SIZE (512 * 1024) /* 512K */ 46 #define TSI721_DB_WIN_SIZE (16 * 1024 * 1024) /* 16MB */ 47 48 #define RIO_TT_CODE_8 0x00000000 49 #define RIO_TT_CODE_16 0x00000001 50 51 #define TSI721_DMA_MAXCH 8 52 #define TSI721_DMA_MINSTSSZ 32 53 #define TSI721_DMA_STSBLKSZ 8 54 55 #define TSI721_SRIO_MAXCH 8 56 57 #define DBELL_SID(buf) (((u8)buf[2] << 8) | (u8)buf[3]) 58 #define DBELL_TID(buf) (((u8)buf[4] << 8) | (u8)buf[5]) 59 #define DBELL_INF(buf) (((u8)buf[0] << 8) | (u8)buf[1]) 60 61 #define TSI721_RIO_PW_MSG_SIZE 16 /* Tsi721 saves only 16 bytes of PW msg */ 62 63 /* Register definitions */ 64 65 /* 66 * Registers in PCIe configuration space 67 */ 68 69 #define TSI721_PCIECFG_MSIXTBL 0x0a4 70 #define TSI721_MSIXTBL_OFFSET 0x2c000 71 #define TSI721_PCIECFG_MSIXPBA 0x0a8 72 #define TSI721_MSIXPBA_OFFSET 0x2a000 73 #define TSI721_PCIECFG_EPCTL 0x400 74 75 #define MAX_READ_REQUEST_SZ_SHIFT 12 76 77 /* 78 * Event Management Registers 79 */ 80 81 #define TSI721_RIO_EM_INT_STAT 0x10910 82 #define TSI721_RIO_EM_INT_STAT_PW_RX 0x00010000 83 84 #define TSI721_RIO_EM_INT_ENABLE 0x10914 85 #define TSI721_RIO_EM_INT_ENABLE_PW_RX 0x00010000 86 87 #define TSI721_RIO_EM_DEV_INT_EN 0x10930 88 #define TSI721_RIO_EM_DEV_INT_EN_INT 0x00000001 89 90 /* 91 * Port-Write Block Registers 92 */ 93 94 #define TSI721_RIO_PW_CTL 0x10a04 95 #define TSI721_RIO_PW_CTL_PW_TIMER 0xf0000000 96 #define TSI721_RIO_PW_CTL_PWT_DIS (0 << 28) 97 #define TSI721_RIO_PW_CTL_PWT_103 (1 << 28) 98 #define TSI721_RIO_PW_CTL_PWT_205 (1 << 29) 99 #define TSI721_RIO_PW_CTL_PWT_410 (1 << 30) 100 #define TSI721_RIO_PW_CTL_PWT_820 (1 << 31) 101 #define TSI721_RIO_PW_CTL_PWC_MODE 0x01000000 102 #define TSI721_RIO_PW_CTL_PWC_CONT 0x00000000 103 #define TSI721_RIO_PW_CTL_PWC_REL 0x01000000 104 105 #define TSI721_RIO_PW_RX_STAT 0x10a10 106 #define TSI721_RIO_PW_RX_STAT_WR_SIZE 0x0000f000 107 #define TSI_RIO_PW_RX_STAT_WDPTR 0x00000100 108 #define TSI721_RIO_PW_RX_STAT_PW_SHORT 0x00000008 109 #define TSI721_RIO_PW_RX_STAT_PW_TRUNC 0x00000004 110 #define TSI721_RIO_PW_RX_STAT_PW_DISC 0x00000002 111 #define TSI721_RIO_PW_RX_STAT_PW_VAL 0x00000001 112 113 #define TSI721_RIO_PW_RX_CAPT(x) (0x10a20 + (x)*4) 114 115 /* 116 * Inbound Doorbells 117 */ 118 119 #define TSI721_IDB_ENTRY_SIZE 64 120 121 #define TSI721_IDQ_CTL(x) (0x20000 + (x) * 0x1000) 122 #define TSI721_IDQ_SUSPEND 0x00000002 123 #define TSI721_IDQ_INIT 0x00000001 124 125 #define TSI721_IDQ_STS(x) (0x20004 + (x) * 0x1000) 126 #define TSI721_IDQ_RUN 0x00200000 127 128 #define TSI721_IDQ_MASK(x) (0x20008 + (x) * 0x1000) 129 #define TSI721_IDQ_MASK_MASK 0xffff0000 130 #define TSI721_IDQ_MASK_PATT 0x0000ffff 131 132 #define TSI721_IDQ_RP(x) (0x2000c + (x) * 0x1000) 133 #define TSI721_IDQ_RP_PTR 0x0007ffff 134 135 #define TSI721_IDQ_WP(x) (0x20010 + (x) * 0x1000) 136 #define TSI721_IDQ_WP_PTR 0x0007ffff 137 138 #define TSI721_IDQ_BASEL(x) (0x20014 + (x) * 0x1000) 139 #define TSI721_IDQ_BASEL_ADDR 0xffffffc0 140 #define TSI721_IDQ_BASEU(x) (0x20018 + (x) * 0x1000) 141 #define TSI721_IDQ_SIZE(x) (0x2001c + (x) * 0x1000) 142 #define TSI721_IDQ_SIZE_VAL(size) (__fls(size) - 4) 143 #define TSI721_IDQ_SIZE_MIN 512 144 #define TSI721_IDQ_SIZE_MAX (512 * 1024) 145 146 #define TSI721_SR_CHINT(x) (0x20040 + (x) * 0x1000) 147 #define TSI721_SR_CHINTE(x) (0x20044 + (x) * 0x1000) 148 #define TSI721_SR_CHINTSET(x) (0x20048 + (x) * 0x1000) 149 #define TSI721_SR_CHINT_ODBOK 0x00000020 150 #define TSI721_SR_CHINT_IDBQRCV 0x00000010 151 #define TSI721_SR_CHINT_SUSP 0x00000008 152 #define TSI721_SR_CHINT_ODBTO 0x00000004 153 #define TSI721_SR_CHINT_ODBRTRY 0x00000002 154 #define TSI721_SR_CHINT_ODBERR 0x00000001 155 #define TSI721_SR_CHINT_ALL 0x0000003f 156 157 #define TSI721_IBWIN_NUM 8 158 159 #define TSI721_IBWINLB(x) (0x29000 + (x) * 0x20) 160 #define TSI721_IBWINLB_BA 0xfffff000 161 #define TSI721_IBWINLB_WEN 0x00000001 162 163 #define TSI721_SR2PC_GEN_INTE 0x29800 164 #define TSI721_SR2PC_PWE 0x29804 165 #define TSI721_SR2PC_GEN_INT 0x29808 166 167 #define TSI721_DEV_INTE 0x29840 168 #define TSI721_DEV_INT 0x29844 169 #define TSI721_DEV_INTSET 0x29848 170 #define TSI721_DEV_INT_SMSG_CH 0x00000800 171 #define TSI721_DEV_INT_SMSG_NCH 0x00000400 172 #define TSI721_DEV_INT_SR2PC_CH 0x00000200 173 #define TSI721_DEV_INT_SRIO 0x00000020 174 175 #define TSI721_DEV_CHAN_INTE 0x2984c 176 #define TSI721_DEV_CHAN_INT 0x29850 177 178 #define TSI721_INT_SR2PC_CHAN_M 0xff000000 179 #define TSI721_INT_SR2PC_CHAN(x) (1 << (24 + (x))) 180 #define TSI721_INT_IMSG_CHAN_M 0x00ff0000 181 #define TSI721_INT_IMSG_CHAN(x) (1 << (16 + (x))) 182 #define TSI721_INT_OMSG_CHAN_M 0x0000ff00 183 #define TSI721_INT_OMSG_CHAN(x) (1 << (8 + (x))) 184 185 /* 186 * PC2SR block registers 187 */ 188 #define TSI721_OBWIN_NUM TSI721_PC2SR_WINS 189 190 #define TSI721_OBWINLB(x) (0x40000 + (x) * 0x20) 191 #define TSI721_OBWINLB_BA 0xffff8000 192 #define TSI721_OBWINLB_WEN 0x00000001 193 194 #define TSI721_OBWINUB(x) (0x40004 + (x) * 0x20) 195 196 #define TSI721_OBWINSZ(x) (0x40008 + (x) * 0x20) 197 #define TSI721_OBWINSZ_SIZE 0x00001f00 198 #define TSI721_OBWIN_SIZE(size) (__fls(size) - 15) 199 200 #define TSI721_ZONE_SEL 0x41300 201 #define TSI721_ZONE_SEL_RD_WRB 0x00020000 202 #define TSI721_ZONE_SEL_GO 0x00010000 203 #define TSI721_ZONE_SEL_WIN 0x00000038 204 #define TSI721_ZONE_SEL_ZONE 0x00000007 205 206 #define TSI721_LUT_DATA0 0x41304 207 #define TSI721_LUT_DATA0_ADD 0xfffff000 208 #define TSI721_LUT_DATA0_RDTYPE 0x00000f00 209 #define TSI721_LUT_DATA0_NREAD 0x00000100 210 #define TSI721_LUT_DATA0_MNTRD 0x00000200 211 #define TSI721_LUT_DATA0_RDCRF 0x00000020 212 #define TSI721_LUT_DATA0_WRCRF 0x00000010 213 #define TSI721_LUT_DATA0_WRTYPE 0x0000000f 214 #define TSI721_LUT_DATA0_NWR 0x00000001 215 #define TSI721_LUT_DATA0_MNTWR 0x00000002 216 #define TSI721_LUT_DATA0_NWR_R 0x00000004 217 218 #define TSI721_LUT_DATA1 0x41308 219 220 #define TSI721_LUT_DATA2 0x4130c 221 #define TSI721_LUT_DATA2_HC 0xff000000 222 #define TSI721_LUT_DATA2_ADD65 0x000c0000 223 #define TSI721_LUT_DATA2_TT 0x00030000 224 #define TSI721_LUT_DATA2_DSTID 0x0000ffff 225 226 #define TSI721_PC2SR_INTE 0x41310 227 228 #define TSI721_DEVCTL 0x48004 229 #define TSI721_DEVCTL_SRBOOT_CMPL 0x00000004 230 231 #define TSI721_I2C_INT_ENABLE 0x49120 232 233 /* 234 * Block DMA Engine Registers 235 * x = 0..7 236 */ 237 238 #define TSI721_DMAC_DWRCNT(x) (0x51000 + (x) * 0x1000) 239 #define TSI721_DMAC_DRDCNT(x) (0x51004 + (x) * 0x1000) 240 241 #define TSI721_DMAC_CTL(x) (0x51008 + (x) * 0x1000) 242 #define TSI721_DMAC_CTL_SUSP 0x00000002 243 #define TSI721_DMAC_CTL_INIT 0x00000001 244 245 #define TSI721_DMAC_INT(x) (0x5100c + (x) * 0x1000) 246 #define TSI721_DMAC_INT_STFULL 0x00000010 247 #define TSI721_DMAC_INT_DONE 0x00000008 248 #define TSI721_DMAC_INT_SUSP 0x00000004 249 #define TSI721_DMAC_INT_ERR 0x00000002 250 #define TSI721_DMAC_INT_IOFDONE 0x00000001 251 #define TSI721_DMAC_INT_ALL 0x0000001f 252 253 #define TSI721_DMAC_INTSET(x) (0x51010 + (x) * 0x1000) 254 255 #define TSI721_DMAC_STS(x) (0x51014 + (x) * 0x1000) 256 #define TSI721_DMAC_STS_ABORT 0x00400000 257 #define TSI721_DMAC_STS_RUN 0x00200000 258 #define TSI721_DMAC_STS_CS 0x001f0000 259 260 #define TSI721_DMAC_INTE(x) (0x51018 + (x) * 0x1000) 261 262 #define TSI721_DMAC_DPTRL(x) (0x51024 + (x) * 0x1000) 263 #define TSI721_DMAC_DPTRL_MASK 0xffffffe0 264 265 #define TSI721_DMAC_DPTRH(x) (0x51028 + (x) * 0x1000) 266 267 #define TSI721_DMAC_DSBL(x) (0x5102c + (x) * 0x1000) 268 #define TSI721_DMAC_DSBL_MASK 0xffffffc0 269 270 #define TSI721_DMAC_DSBH(x) (0x51030 + (x) * 0x1000) 271 272 #define TSI721_DMAC_DSSZ(x) (0x51034 + (x) * 0x1000) 273 #define TSI721_DMAC_DSSZ_SIZE_M 0x0000000f 274 #define TSI721_DMAC_DSSZ_SIZE(size) (__fls(size) - 4) 275 276 277 #define TSI721_DMAC_DSRP(x) (0x51038 + (x) * 0x1000) 278 #define TSI721_DMAC_DSRP_MASK 0x0007ffff 279 280 #define TSI721_DMAC_DSWP(x) (0x5103c + (x) * 0x1000) 281 #define TSI721_DMAC_DSWP_MASK 0x0007ffff 282 283 #define TSI721_BDMA_INTE 0x5f000 284 285 /* 286 * Messaging definitions 287 */ 288 #define TSI721_MSG_BUFFER_SIZE RIO_MAX_MSG_SIZE 289 #define TSI721_MSG_MAX_SIZE RIO_MAX_MSG_SIZE 290 #define TSI721_IMSG_MAXCH 8 291 #define TSI721_IMSG_CHNUM TSI721_IMSG_MAXCH 292 #define TSI721_IMSGD_MIN_RING_SIZE 32 293 #define TSI721_IMSGD_RING_SIZE 512 294 295 #define TSI721_OMSG_CHNUM 4 /* One channel per MBOX */ 296 #define TSI721_OMSGD_MIN_RING_SIZE 32 297 #define TSI721_OMSGD_RING_SIZE 512 298 299 /* 300 * Outbound Messaging Engine Registers 301 * x = 0..7 302 */ 303 304 #define TSI721_OBDMAC_DWRCNT(x) (0x61000 + (x) * 0x1000) 305 306 #define TSI721_OBDMAC_DRDCNT(x) (0x61004 + (x) * 0x1000) 307 308 #define TSI721_OBDMAC_CTL(x) (0x61008 + (x) * 0x1000) 309 #define TSI721_OBDMAC_CTL_MASK 0x00000007 310 #define TSI721_OBDMAC_CTL_RETRY_THR 0x00000004 311 #define TSI721_OBDMAC_CTL_SUSPEND 0x00000002 312 #define TSI721_OBDMAC_CTL_INIT 0x00000001 313 314 #define TSI721_OBDMAC_INT(x) (0x6100c + (x) * 0x1000) 315 #define TSI721_OBDMAC_INTSET(x) (0x61010 + (x) * 0x1000) 316 #define TSI721_OBDMAC_INTE(x) (0x61018 + (x) * 0x1000) 317 #define TSI721_OBDMAC_INT_MASK 0x0000001F 318 #define TSI721_OBDMAC_INT_ST_FULL 0x00000010 319 #define TSI721_OBDMAC_INT_DONE 0x00000008 320 #define TSI721_OBDMAC_INT_SUSPENDED 0x00000004 321 #define TSI721_OBDMAC_INT_ERROR 0x00000002 322 #define TSI721_OBDMAC_INT_IOF_DONE 0x00000001 323 #define TSI721_OBDMAC_INT_ALL TSI721_OBDMAC_INT_MASK 324 325 #define TSI721_OBDMAC_STS(x) (0x61014 + (x) * 0x1000) 326 #define TSI721_OBDMAC_STS_MASK 0x007f0000 327 #define TSI721_OBDMAC_STS_ABORT 0x00400000 328 #define TSI721_OBDMAC_STS_RUN 0x00200000 329 #define TSI721_OBDMAC_STS_CS 0x001f0000 330 331 #define TSI721_OBDMAC_PWE(x) (0x6101c + (x) * 0x1000) 332 #define TSI721_OBDMAC_PWE_MASK 0x00000002 333 #define TSI721_OBDMAC_PWE_ERROR_EN 0x00000002 334 335 #define TSI721_OBDMAC_DPTRL(x) (0x61020 + (x) * 0x1000) 336 #define TSI721_OBDMAC_DPTRL_MASK 0xfffffff0 337 338 #define TSI721_OBDMAC_DPTRH(x) (0x61024 + (x) * 0x1000) 339 #define TSI721_OBDMAC_DPTRH_MASK 0xffffffff 340 341 #define TSI721_OBDMAC_DSBL(x) (0x61040 + (x) * 0x1000) 342 #define TSI721_OBDMAC_DSBL_MASK 0xffffffc0 343 344 #define TSI721_OBDMAC_DSBH(x) (0x61044 + (x) * 0x1000) 345 #define TSI721_OBDMAC_DSBH_MASK 0xffffffff 346 347 #define TSI721_OBDMAC_DSSZ(x) (0x61048 + (x) * 0x1000) 348 #define TSI721_OBDMAC_DSSZ_MASK 0x0000000f 349 350 #define TSI721_OBDMAC_DSRP(x) (0x6104c + (x) * 0x1000) 351 #define TSI721_OBDMAC_DSRP_MASK 0x0007ffff 352 353 #define TSI721_OBDMAC_DSWP(x) (0x61050 + (x) * 0x1000) 354 #define TSI721_OBDMAC_DSWP_MASK 0x0007ffff 355 356 #define TSI721_RQRPTO 0x60010 357 #define TSI721_RQRPTO_MASK 0x00ffffff 358 #define TSI721_RQRPTO_VAL 400 /* Response TO value */ 359 360 /* 361 * Inbound Messaging Engine Registers 362 * x = 0..7 363 */ 364 365 #define TSI721_IB_DEVID_GLOBAL 0xffff 366 #define TSI721_IBDMAC_FQBL(x) (0x61200 + (x) * 0x1000) 367 #define TSI721_IBDMAC_FQBL_MASK 0xffffffc0 368 369 #define TSI721_IBDMAC_FQBH(x) (0x61204 + (x) * 0x1000) 370 #define TSI721_IBDMAC_FQBH_MASK 0xffffffff 371 372 #define TSI721_IBDMAC_FQSZ_ENTRY_INX TSI721_IMSGD_RING_SIZE 373 #define TSI721_IBDMAC_FQSZ(x) (0x61208 + (x) * 0x1000) 374 #define TSI721_IBDMAC_FQSZ_MASK 0x0000000f 375 376 #define TSI721_IBDMAC_FQRP(x) (0x6120c + (x) * 0x1000) 377 #define TSI721_IBDMAC_FQRP_MASK 0x0007ffff 378 379 #define TSI721_IBDMAC_FQWP(x) (0x61210 + (x) * 0x1000) 380 #define TSI721_IBDMAC_FQWP_MASK 0x0007ffff 381 382 #define TSI721_IBDMAC_FQTH(x) (0x61214 + (x) * 0x1000) 383 #define TSI721_IBDMAC_FQTH_MASK 0x0007ffff 384 385 #define TSI721_IB_DEVID 0x60020 386 #define TSI721_IB_DEVID_MASK 0x0000ffff 387 388 #define TSI721_IBDMAC_CTL(x) (0x61240 + (x) * 0x1000) 389 #define TSI721_IBDMAC_CTL_MASK 0x00000003 390 #define TSI721_IBDMAC_CTL_SUSPEND 0x00000002 391 #define TSI721_IBDMAC_CTL_INIT 0x00000001 392 393 #define TSI721_IBDMAC_STS(x) (0x61244 + (x) * 0x1000) 394 #define TSI721_IBDMAC_STS_MASK 0x007f0000 395 #define TSI721_IBSMAC_STS_ABORT 0x00400000 396 #define TSI721_IBSMAC_STS_RUN 0x00200000 397 #define TSI721_IBSMAC_STS_CS 0x001f0000 398 399 #define TSI721_IBDMAC_INT(x) (0x61248 + (x) * 0x1000) 400 #define TSI721_IBDMAC_INTSET(x) (0x6124c + (x) * 0x1000) 401 #define TSI721_IBDMAC_INTE(x) (0x61250 + (x) * 0x1000) 402 #define TSI721_IBDMAC_INT_MASK 0x0000100f 403 #define TSI721_IBDMAC_INT_SRTO 0x00001000 404 #define TSI721_IBDMAC_INT_SUSPENDED 0x00000008 405 #define TSI721_IBDMAC_INT_PC_ERROR 0x00000004 406 #define TSI721_IBDMAC_INT_FQ_LOW 0x00000002 407 #define TSI721_IBDMAC_INT_DQ_RCV 0x00000001 408 #define TSI721_IBDMAC_INT_ALL TSI721_IBDMAC_INT_MASK 409 410 #define TSI721_IBDMAC_PWE(x) (0x61254 + (x) * 0x1000) 411 #define TSI721_IBDMAC_PWE_MASK 0x00001700 412 #define TSI721_IBDMAC_PWE_SRTO 0x00001000 413 #define TSI721_IBDMAC_PWE_ILL_FMT 0x00000400 414 #define TSI721_IBDMAC_PWE_ILL_DEC 0x00000200 415 #define TSI721_IBDMAC_PWE_IMP_SP 0x00000100 416 417 #define TSI721_IBDMAC_DQBL(x) (0x61300 + (x) * 0x1000) 418 #define TSI721_IBDMAC_DQBL_MASK 0xffffffc0 419 #define TSI721_IBDMAC_DQBL_ADDR 0xffffffc0 420 421 #define TSI721_IBDMAC_DQBH(x) (0x61304 + (x) * 0x1000) 422 #define TSI721_IBDMAC_DQBH_MASK 0xffffffff 423 424 #define TSI721_IBDMAC_DQRP(x) (0x61308 + (x) * 0x1000) 425 #define TSI721_IBDMAC_DQRP_MASK 0x0007ffff 426 427 #define TSI721_IBDMAC_DQWR(x) (0x6130c + (x) * 0x1000) 428 #define TSI721_IBDMAC_DQWR_MASK 0x0007ffff 429 430 #define TSI721_IBDMAC_DQSZ(x) (0x61314 + (x) * 0x1000) 431 #define TSI721_IBDMAC_DQSZ_MASK 0x0000000f 432 433 /* 434 * Messaging Engine Interrupts 435 */ 436 437 #define TSI721_SMSG_PWE 0x6a004 438 439 #define TSI721_SMSG_INTE 0x6a000 440 #define TSI721_SMSG_INT 0x6a008 441 #define TSI721_SMSG_INTSET 0x6a010 442 #define TSI721_SMSG_INT_MASK 0x0086ffff 443 #define TSI721_SMSG_INT_UNS_RSP 0x00800000 444 #define TSI721_SMSG_INT_ECC_NCOR 0x00040000 445 #define TSI721_SMSG_INT_ECC_COR 0x00020000 446 #define TSI721_SMSG_INT_ECC_NCOR_CH 0x0000ff00 447 #define TSI721_SMSG_INT_ECC_COR_CH 0x000000ff 448 449 #define TSI721_SMSG_ECC_LOG 0x6a014 450 #define TSI721_SMSG_ECC_LOG_MASK 0x00070007 451 #define TSI721_SMSG_ECC_LOG_ECC_NCOR_M 0x00070000 452 #define TSI721_SMSG_ECC_LOG_ECC_COR_M 0x00000007 453 454 #define TSI721_RETRY_GEN_CNT 0x6a100 455 #define TSI721_RETRY_GEN_CNT_MASK 0xffffffff 456 457 #define TSI721_RETRY_RX_CNT 0x6a104 458 #define TSI721_RETRY_RX_CNT_MASK 0xffffffff 459 460 #define TSI721_SMSG_ECC_COR_LOG(x) (0x6a300 + (x) * 4) 461 #define TSI721_SMSG_ECC_COR_LOG_MASK 0x000000ff 462 463 #define TSI721_SMSG_ECC_NCOR(x) (0x6a340 + (x) * 4) 464 #define TSI721_SMSG_ECC_NCOR_MASK 0x000000ff 465 466 /* 467 * Block DMA Descriptors 468 */ 469 470 struct tsi721_dma_desc { 471 __le32 type_id; 472 473 #define TSI721_DMAD_DEVID 0x0000ffff 474 #define TSI721_DMAD_CRF 0x00010000 475 #define TSI721_DMAD_PRIO 0x00060000 476 #define TSI721_DMAD_RTYPE 0x00780000 477 #define TSI721_DMAD_IOF 0x08000000 478 #define TSI721_DMAD_DTYPE 0xe0000000 479 480 __le32 bcount; 481 482 #define TSI721_DMAD_BCOUNT1 0x03ffffff /* if DTYPE == 1 */ 483 #define TSI721_DMAD_BCOUNT2 0x0000000f /* if DTYPE == 2 */ 484 #define TSI721_DMAD_TT 0x0c000000 485 #define TSI721_DMAD_RADDR0 0xc0000000 486 487 union { 488 __le32 raddr_lo; /* if DTYPE == (1 || 2) */ 489 __le32 next_lo; /* if DTYPE == 3 */ 490 }; 491 492 #define TSI721_DMAD_CFGOFF 0x00ffffff 493 #define TSI721_DMAD_HOPCNT 0xff000000 494 495 union { 496 __le32 raddr_hi; /* if DTYPE == (1 || 2) */ 497 __le32 next_hi; /* if DTYPE == 3 */ 498 }; 499 500 union { 501 struct { /* if DTYPE == 1 */ 502 __le32 bufptr_lo; 503 __le32 bufptr_hi; 504 __le32 s_dist; 505 __le32 s_size; 506 } t1; 507 __le32 data[4]; /* if DTYPE == 2 */ 508 u32 reserved[4]; /* if DTYPE == 3 */ 509 }; 510 } __aligned(32); 511 512 /* 513 * Inbound Messaging Descriptor 514 */ 515 struct tsi721_imsg_desc { 516 __le32 type_id; 517 518 #define TSI721_IMD_DEVID 0x0000ffff 519 #define TSI721_IMD_CRF 0x00010000 520 #define TSI721_IMD_PRIO 0x00060000 521 #define TSI721_IMD_TT 0x00180000 522 #define TSI721_IMD_DTYPE 0xe0000000 523 524 __le32 msg_info; 525 526 #define TSI721_IMD_BCOUNT 0x00000ff8 527 #define TSI721_IMD_SSIZE 0x0000f000 528 #define TSI721_IMD_LETER 0x00030000 529 #define TSI721_IMD_XMBOX 0x003c0000 530 #define TSI721_IMD_MBOX 0x00c00000 531 #define TSI721_IMD_CS 0x78000000 532 #define TSI721_IMD_HO 0x80000000 533 534 __le32 bufptr_lo; 535 __le32 bufptr_hi; 536 u32 reserved[12]; 537 538 } __aligned(64); 539 540 /* 541 * Outbound Messaging Descriptor 542 */ 543 struct tsi721_omsg_desc { 544 __le32 type_id; 545 546 #define TSI721_OMD_DEVID 0x0000ffff 547 #define TSI721_OMD_CRF 0x00010000 548 #define TSI721_OMD_PRIO 0x00060000 549 #define TSI721_OMD_IOF 0x08000000 550 #define TSI721_OMD_DTYPE 0xe0000000 551 #define TSI721_OMD_RSRVD 0x17f80000 552 553 __le32 msg_info; 554 555 #define TSI721_OMD_BCOUNT 0x00000ff8 556 #define TSI721_OMD_SSIZE 0x0000f000 557 #define TSI721_OMD_LETER 0x00030000 558 #define TSI721_OMD_XMBOX 0x003c0000 559 #define TSI721_OMD_MBOX 0x00c00000 560 #define TSI721_OMD_TT 0x0c000000 561 562 union { 563 __le32 bufptr_lo; /* if DTYPE == 4 */ 564 __le32 next_lo; /* if DTYPE == 5 */ 565 }; 566 567 union { 568 __le32 bufptr_hi; /* if DTYPE == 4 */ 569 __le32 next_hi; /* if DTYPE == 5 */ 570 }; 571 572 } __aligned(16); 573 574 struct tsi721_dma_sts { 575 __le64 desc_sts[8]; 576 } __aligned(64); 577 578 struct tsi721_desc_sts_fifo { 579 union { 580 __le64 da64; 581 struct { 582 __le32 lo; 583 __le32 hi; 584 } da32; 585 } stat[8]; 586 } __aligned(64); 587 588 /* Descriptor types for BDMA and Messaging blocks */ 589 enum dma_dtype { 590 DTYPE1 = 1, /* Data Transfer DMA Descriptor */ 591 DTYPE2 = 2, /* Immediate Data Transfer DMA Descriptor */ 592 DTYPE3 = 3, /* Block Pointer DMA Descriptor */ 593 DTYPE4 = 4, /* Outbound Msg DMA Descriptor */ 594 DTYPE5 = 5, /* OB Messaging Block Pointer Descriptor */ 595 DTYPE6 = 6 /* Inbound Messaging Descriptor */ 596 }; 597 598 enum dma_rtype { 599 NREAD = 0, 600 LAST_NWRITE_R = 1, 601 ALL_NWRITE = 2, 602 ALL_NWRITE_R = 3, 603 MAINT_RD = 4, 604 MAINT_WR = 5 605 }; 606 607 /* 608 * mport Driver Definitions 609 */ 610 #define TSI721_DMA_CHNUM TSI721_DMA_MAXCH 611 612 #define TSI721_DMACH_MAINT 0 /* DMA channel for maint requests */ 613 #define TSI721_DMACH_MAINT_NBD 32 /* Number of BDs for maint requests */ 614 615 #define MSG_DMA_ENTRY_INX_TO_SIZE(x) ((0x10 << (x)) & 0xFFFF0) 616 617 enum tsi721_smsg_int_flag { 618 SMSG_INT_NONE = 0x00000000, 619 SMSG_INT_ECC_COR_CH = 0x000000ff, 620 SMSG_INT_ECC_NCOR_CH = 0x0000ff00, 621 SMSG_INT_ECC_COR = 0x00020000, 622 SMSG_INT_ECC_NCOR = 0x00040000, 623 SMSG_INT_UNS_RSP = 0x00800000, 624 SMSG_INT_ALL = 0x0006ffff 625 }; 626 627 /* Structures */ 628 629 struct tsi721_bdma_chan { 630 int bd_num; /* number of buffer descriptors */ 631 void *bd_base; /* start of DMA descriptors */ 632 dma_addr_t bd_phys; 633 void *sts_base; /* start of DMA BD status FIFO */ 634 dma_addr_t sts_phys; 635 int sts_size; 636 }; 637 638 struct tsi721_imsg_ring { 639 u32 size; 640 /* VA/PA of data buffers for incoming messages */ 641 void *buf_base; 642 dma_addr_t buf_phys; 643 /* VA/PA of circular free buffer list */ 644 void *imfq_base; 645 dma_addr_t imfq_phys; 646 /* VA/PA of Inbound message descriptors */ 647 void *imd_base; 648 dma_addr_t imd_phys; 649 /* Inbound Queue buffer pointers */ 650 void *imq_base[TSI721_IMSGD_RING_SIZE]; 651 652 u32 rx_slot; 653 void *dev_id; 654 u32 fq_wrptr; 655 u32 desc_rdptr; 656 spinlock_t lock; 657 }; 658 659 struct tsi721_omsg_ring { 660 u32 size; 661 /* VA/PA of OB Msg descriptors */ 662 void *omd_base; 663 dma_addr_t omd_phys; 664 /* VA/PA of OB Msg data buffers */ 665 void *omq_base[TSI721_OMSGD_RING_SIZE]; 666 dma_addr_t omq_phys[TSI721_OMSGD_RING_SIZE]; 667 /* VA/PA of OB Msg descriptor status FIFO */ 668 void *sts_base; 669 dma_addr_t sts_phys; 670 u32 sts_size; /* # of allocated status entries */ 671 u32 sts_rdptr; 672 673 u32 tx_slot; 674 void *dev_id; 675 u32 wr_count; 676 spinlock_t lock; 677 }; 678 679 enum tsi721_flags { 680 TSI721_USING_MSI = (1 << 0), 681 TSI721_USING_MSIX = (1 << 1), 682 TSI721_IMSGID_SET = (1 << 2), 683 }; 684 685 #ifdef CONFIG_PCI_MSI 686 /* 687 * MSI-X Table Entries (0 ... 69) 688 */ 689 #define TSI721_MSIX_DMACH_DONE(x) (0 + (x)) 690 #define TSI721_MSIX_DMACH_INT(x) (8 + (x)) 691 #define TSI721_MSIX_BDMA_INT 16 692 #define TSI721_MSIX_OMSG_DONE(x) (17 + (x)) 693 #define TSI721_MSIX_OMSG_INT(x) (25 + (x)) 694 #define TSI721_MSIX_IMSG_DQ_RCV(x) (33 + (x)) 695 #define TSI721_MSIX_IMSG_INT(x) (41 + (x)) 696 #define TSI721_MSIX_MSG_INT 49 697 #define TSI721_MSIX_SR2PC_IDBQ_RCV(x) (50 + (x)) 698 #define TSI721_MSIX_SR2PC_CH_INT(x) (58 + (x)) 699 #define TSI721_MSIX_SR2PC_INT 66 700 #define TSI721_MSIX_PC2SR_INT 67 701 #define TSI721_MSIX_SRIO_MAC_INT 68 702 #define TSI721_MSIX_I2C_INT 69 703 704 /* MSI-X vector and init table entry indexes */ 705 enum tsi721_msix_vect { 706 TSI721_VECT_IDB, 707 TSI721_VECT_PWRX, /* PW_RX is part of SRIO MAC Interrupt reporting */ 708 TSI721_VECT_OMB0_DONE, 709 TSI721_VECT_OMB1_DONE, 710 TSI721_VECT_OMB2_DONE, 711 TSI721_VECT_OMB3_DONE, 712 TSI721_VECT_OMB0_INT, 713 TSI721_VECT_OMB1_INT, 714 TSI721_VECT_OMB2_INT, 715 TSI721_VECT_OMB3_INT, 716 TSI721_VECT_IMB0_RCV, 717 TSI721_VECT_IMB1_RCV, 718 TSI721_VECT_IMB2_RCV, 719 TSI721_VECT_IMB3_RCV, 720 TSI721_VECT_IMB0_INT, 721 TSI721_VECT_IMB1_INT, 722 TSI721_VECT_IMB2_INT, 723 TSI721_VECT_IMB3_INT, 724 TSI721_VECT_MAX 725 }; 726 727 #define IRQ_DEVICE_NAME_MAX 64 728 729 struct msix_irq { 730 u16 vector; 731 char irq_name[IRQ_DEVICE_NAME_MAX]; 732 }; 733 #endif /* CONFIG_PCI_MSI */ 734 735 struct tsi721_device { 736 struct pci_dev *pdev; 737 struct rio_mport *mport; 738 u32 flags; 739 void __iomem *regs; 740 #ifdef CONFIG_PCI_MSI 741 struct msix_irq msix[TSI721_VECT_MAX]; 742 #endif 743 /* Doorbells */ 744 void __iomem *odb_base; 745 void *idb_base; 746 dma_addr_t idb_dma; 747 struct work_struct idb_work; 748 u32 db_discard_count; 749 750 /* Inbound Port-Write */ 751 struct work_struct pw_work; 752 struct kfifo pw_fifo; 753 spinlock_t pw_fifo_lock; 754 u32 pw_discard_count; 755 756 /* BDMA Engine */ 757 struct tsi721_bdma_chan bdma[TSI721_DMA_CHNUM]; 758 759 /* Inbound Messaging */ 760 int imsg_init[TSI721_IMSG_CHNUM]; 761 struct tsi721_imsg_ring imsg_ring[TSI721_IMSG_CHNUM]; 762 763 /* Outbound Messaging */ 764 int omsg_init[TSI721_OMSG_CHNUM]; 765 struct tsi721_omsg_ring omsg_ring[TSI721_OMSG_CHNUM]; 766 }; 767 768 #endif 769