1 /* 2 * arch/arm/mach-pnx4008/include/mach/clock.h 3 * 4 * Clock control driver for PNX4008 - header file 5 * 6 * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com> 7 * 8 * 2005 (c) MontaVista Software, Inc. This file is licensed under 9 * the terms of the GNU General Public License version 2. This program 10 * is licensed "as is" without any warranty of any kind, whether express 11 * or implied. 12 */ 13 #ifndef __PNX4008_CLOCK_H__ 14 #define __PNX4008_CLOCK_H__ 15 16 struct module; 17 struct clk; 18 19 #define PWRMAN_VA_BASE IO_ADDRESS(PNX4008_PWRMAN_BASE) 20 #define HCLKDIVCTRL_REG (PWRMAN_VA_BASE + 0x40) 21 #define PWRCTRL_REG (PWRMAN_VA_BASE + 0x44) 22 #define PLLCTRL_REG (PWRMAN_VA_BASE + 0x48) 23 #define OSC13CTRL_REG (PWRMAN_VA_BASE + 0x4c) 24 #define SYSCLKCTRL_REG (PWRMAN_VA_BASE + 0x50) 25 #define HCLKPLLCTRL_REG (PWRMAN_VA_BASE + 0x58) 26 #define USBCTRL_REG (PWRMAN_VA_BASE + 0x64) 27 #define SDRAMCLKCTRL_REG (PWRMAN_VA_BASE + 0x68) 28 #define MSCTRL_REG (PWRMAN_VA_BASE + 0x80) 29 #define BTCLKCTRL (PWRMAN_VA_BASE + 0x84) 30 #define DUMCLKCTRL_REG (PWRMAN_VA_BASE + 0x90) 31 #define I2CCLKCTRL_REG (PWRMAN_VA_BASE + 0xac) 32 #define KEYCLKCTRL_REG (PWRMAN_VA_BASE + 0xb0) 33 #define TSCLKCTRL_REG (PWRMAN_VA_BASE + 0xb4) 34 #define PWMCLKCTRL_REG (PWRMAN_VA_BASE + 0xb8) 35 #define TIMCLKCTRL_REG (PWRMAN_VA_BASE + 0xbc) 36 #define SPICTRL_REG (PWRMAN_VA_BASE + 0xc4) 37 #define FLASHCLKCTRL_REG (PWRMAN_VA_BASE + 0xc8) 38 #define UART3CLK_REG (PWRMAN_VA_BASE + 0xd0) 39 #define UARTCLKCTRL_REG (PWRMAN_VA_BASE + 0xe4) 40 #define DMACLKCTRL_REG (PWRMAN_VA_BASE + 0xe8) 41 #define AUTOCLK_CTRL (PWRMAN_VA_BASE + 0xec) 42 #define JPEGCLKCTRL_REG (PWRMAN_VA_BASE + 0xfc) 43 44 #define AUDIOCONFIG_VA_BASE IO_ADDRESS(PNX4008_AUDIOCONFIG_BASE) 45 #define DSPPLLCTRL_REG (AUDIOCONFIG_VA_BASE + 0x60) 46 #define DSPCLKCTRL_REG (AUDIOCONFIG_VA_BASE + 0x64) 47 #define AUDIOCLKCTRL_REG (AUDIOCONFIG_VA_BASE + 0x68) 48 #define AUDIOPLLCTRL_REG (AUDIOCONFIG_VA_BASE + 0x6C) 49 50 #define USB_OTG_CLKCTRL_REG IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xff4) 51 52 #define VFP9CLKCTRL_REG IO_ADDRESS(PNX4008_DEBUG_BASE) 53 54 #define CLK_RATE_13MHZ 13000 55 #define CLK_RATE_1MHZ 1000 56 #define CLK_RATE_208MHZ 208000 57 #define CLK_RATE_48MHZ 48000 58 #define CLK_RATE_32KHZ 32 59 60 #define PNX4008_UART_CLK CLK_RATE_13MHZ * 1000 /* in MHz */ 61 62 #endif 63