1 /*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23 #ifndef __LINUX_XHCI_HCD_H
24 #define __LINUX_XHCI_HCD_H
25
26 #include <linux/usb.h>
27 #include <linux/timer.h>
28 #include <linux/kernel.h>
29 #include <linux/usb/hcd.h>
30
31 /* Code sharing between pci-quirks and xhci hcd */
32 #include "xhci-ext-caps.h"
33 #include "pci-quirks.h"
34
35 /* xHCI PCI Configuration Registers */
36 #define XHCI_SBRN_OFFSET (0x60)
37
38 /* Max number of USB devices for any host controller - limit in section 6.1 */
39 #define MAX_HC_SLOTS 256
40 /* Section 5.3.3 - MaxPorts */
41 #define MAX_HC_PORTS 127
42
43 /*
44 * xHCI register interface.
45 * This corresponds to the eXtensible Host Controller Interface (xHCI)
46 * Revision 0.95 specification
47 */
48
49 /**
50 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
51 * @hc_capbase: length of the capabilities register and HC version number
52 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
53 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
54 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
55 * @hcc_params: HCCPARAMS - Capability Parameters
56 * @db_off: DBOFF - Doorbell array offset
57 * @run_regs_off: RTSOFF - Runtime register space offset
58 */
59 struct xhci_cap_regs {
60 __le32 hc_capbase;
61 __le32 hcs_params1;
62 __le32 hcs_params2;
63 __le32 hcs_params3;
64 __le32 hcc_params;
65 __le32 db_off;
66 __le32 run_regs_off;
67 /* Reserved up to (CAPLENGTH - 0x1C) */
68 };
69
70 /* hc_capbase bitmasks */
71 /* bits 7:0 - how long is the Capabilities register */
72 #define HC_LENGTH(p) XHCI_HC_LENGTH(p)
73 /* bits 31:16 */
74 #define HC_VERSION(p) (((p) >> 16) & 0xffff)
75
76 /* HCSPARAMS1 - hcs_params1 - bitmasks */
77 /* bits 0:7, Max Device Slots */
78 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
79 #define HCS_SLOTS_MASK 0xff
80 /* bits 8:18, Max Interrupters */
81 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
82 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
83 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
84
85 /* HCSPARAMS2 - hcs_params2 - bitmasks */
86 /* bits 0:3, frames or uframes that SW needs to queue transactions
87 * ahead of the HW to meet periodic deadlines */
88 #define HCS_IST(p) (((p) >> 0) & 0xf)
89 /* bits 4:7, max number of Event Ring segments */
90 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
91 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
92 /* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */
93 #define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f)
94
95 /* HCSPARAMS3 - hcs_params3 - bitmasks */
96 /* bits 0:7, Max U1 to U0 latency for the roothub ports */
97 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
98 /* bits 16:31, Max U2 to U0 latency for the roothub ports */
99 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
100
101 /* HCCPARAMS - hcc_params - bitmasks */
102 /* true: HC can use 64-bit address pointers */
103 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
104 /* true: HC can do bandwidth negotiation */
105 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
106 /* true: HC uses 64-byte Device Context structures
107 * FIXME 64-byte context structures aren't supported yet.
108 */
109 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
110 /* true: HC has port power switches */
111 #define HCC_PPC(p) ((p) & (1 << 3))
112 /* true: HC has port indicators */
113 #define HCS_INDICATOR(p) ((p) & (1 << 4))
114 /* true: HC has Light HC Reset Capability */
115 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
116 /* true: HC supports latency tolerance messaging */
117 #define HCC_LTC(p) ((p) & (1 << 6))
118 /* true: no secondary Stream ID Support */
119 #define HCC_NSS(p) ((p) & (1 << 7))
120 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
121 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
122 /* Extended Capabilities pointer from PCI base - section 5.3.6 */
123 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
124
125 /* db_off bitmask - bits 0:1 reserved */
126 #define DBOFF_MASK (~0x3)
127
128 /* run_regs_off bitmask - bits 0:4 reserved */
129 #define RTSOFF_MASK (~0x1f)
130
131
132 /* Number of registers per port */
133 #define NUM_PORT_REGS 4
134
135 /**
136 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
137 * @command: USBCMD - xHC command register
138 * @status: USBSTS - xHC status register
139 * @page_size: This indicates the page size that the host controller
140 * supports. If bit n is set, the HC supports a page size
141 * of 2^(n+12), up to a 128MB page size.
142 * 4K is the minimum page size.
143 * @cmd_ring: CRP - 64-bit Command Ring Pointer
144 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
145 * @config_reg: CONFIG - Configure Register
146 * @port_status_base: PORTSCn - base address for Port Status and Control
147 * Each port has a Port Status and Control register,
148 * followed by a Port Power Management Status and Control
149 * register, a Port Link Info register, and a reserved
150 * register.
151 * @port_power_base: PORTPMSCn - base address for
152 * Port Power Management Status and Control
153 * @port_link_base: PORTLIn - base address for Port Link Info (current
154 * Link PM state and control) for USB 2.1 and USB 3.0
155 * devices.
156 */
157 struct xhci_op_regs {
158 __le32 command;
159 __le32 status;
160 __le32 page_size;
161 __le32 reserved1;
162 __le32 reserved2;
163 __le32 dev_notification;
164 __le64 cmd_ring;
165 /* rsvd: offset 0x20-2F */
166 __le32 reserved3[4];
167 __le64 dcbaa_ptr;
168 __le32 config_reg;
169 /* rsvd: offset 0x3C-3FF */
170 __le32 reserved4[241];
171 /* port 1 registers, which serve as a base address for other ports */
172 __le32 port_status_base;
173 __le32 port_power_base;
174 __le32 port_link_base;
175 __le32 reserved5;
176 /* registers for ports 2-255 */
177 __le32 reserved6[NUM_PORT_REGS*254];
178 };
179
180 /* USBCMD - USB command - command bitmasks */
181 /* start/stop HC execution - do not write unless HC is halted*/
182 #define CMD_RUN XHCI_CMD_RUN
183 /* Reset HC - resets internal HC state machine and all registers (except
184 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
185 * The xHCI driver must reinitialize the xHC after setting this bit.
186 */
187 #define CMD_RESET (1 << 1)
188 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
189 #define CMD_EIE XHCI_CMD_EIE
190 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
191 #define CMD_HSEIE XHCI_CMD_HSEIE
192 /* bits 4:6 are reserved (and should be preserved on writes). */
193 /* light reset (port status stays unchanged) - reset completed when this is 0 */
194 #define CMD_LRESET (1 << 7)
195 /* host controller save/restore state. */
196 #define CMD_CSS (1 << 8)
197 #define CMD_CRS (1 << 9)
198 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
199 #define CMD_EWE XHCI_CMD_EWE
200 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
201 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
202 * '0' means the xHC can power it off if all ports are in the disconnect,
203 * disabled, or powered-off state.
204 */
205 #define CMD_PM_INDEX (1 << 11)
206 /* bits 12:31 are reserved (and should be preserved on writes). */
207
208 /* IMAN - Interrupt Management Register */
209 #define IMAN_IE (1 << 1)
210 #define IMAN_IP (1 << 0)
211
212 /* USBSTS - USB status - status bitmasks */
213 /* HC not running - set to 1 when run/stop bit is cleared. */
214 #define STS_HALT XHCI_STS_HALT
215 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
216 #define STS_FATAL (1 << 2)
217 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
218 #define STS_EINT (1 << 3)
219 /* port change detect */
220 #define STS_PORT (1 << 4)
221 /* bits 5:7 reserved and zeroed */
222 /* save state status - '1' means xHC is saving state */
223 #define STS_SAVE (1 << 8)
224 /* restore state status - '1' means xHC is restoring state */
225 #define STS_RESTORE (1 << 9)
226 /* true: save or restore error */
227 #define STS_SRE (1 << 10)
228 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
229 #define STS_CNR XHCI_STS_CNR
230 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
231 #define STS_HCE (1 << 12)
232 /* bits 13:31 reserved and should be preserved */
233
234 /*
235 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
236 * Generate a device notification event when the HC sees a transaction with a
237 * notification type that matches a bit set in this bit field.
238 */
239 #define DEV_NOTE_MASK (0xffff)
240 #define ENABLE_DEV_NOTE(x) (1 << (x))
241 /* Most of the device notification types should only be used for debug.
242 * SW does need to pay attention to function wake notifications.
243 */
244 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
245
246 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
247 /* bit 0 is the command ring cycle state */
248 /* stop ring operation after completion of the currently executing command */
249 #define CMD_RING_PAUSE (1 << 1)
250 /* stop ring immediately - abort the currently executing command */
251 #define CMD_RING_ABORT (1 << 2)
252 /* true: command ring is running */
253 #define CMD_RING_RUNNING (1 << 3)
254 /* bits 4:5 reserved and should be preserved */
255 /* Command Ring pointer - bit mask for the lower 32 bits. */
256 #define CMD_RING_RSVD_BITS (0x3f)
257
258 /* CONFIG - Configure Register - config_reg bitmasks */
259 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
260 #define MAX_DEVS(p) ((p) & 0xff)
261 /* bits 8:31 - reserved and should be preserved */
262
263 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
264 /* true: device connected */
265 #define PORT_CONNECT (1 << 0)
266 /* true: port enabled */
267 #define PORT_PE (1 << 1)
268 /* bit 2 reserved and zeroed */
269 /* true: port has an over-current condition */
270 #define PORT_OC (1 << 3)
271 /* true: port reset signaling asserted */
272 #define PORT_RESET (1 << 4)
273 /* Port Link State - bits 5:8
274 * A read gives the current link PM state of the port,
275 * a write with Link State Write Strobe set sets the link state.
276 */
277 #define PORT_PLS_MASK (0xf << 5)
278 #define XDEV_U0 (0x0 << 5)
279 #define XDEV_U2 (0x2 << 5)
280 #define XDEV_U3 (0x3 << 5)
281 #define XDEV_RESUME (0xf << 5)
282 /* true: port has power (see HCC_PPC) */
283 #define PORT_POWER (1 << 9)
284 /* bits 10:13 indicate device speed:
285 * 0 - undefined speed - port hasn't be initialized by a reset yet
286 * 1 - full speed
287 * 2 - low speed
288 * 3 - high speed
289 * 4 - super speed
290 * 5-15 reserved
291 */
292 #define DEV_SPEED_MASK (0xf << 10)
293 #define XDEV_FS (0x1 << 10)
294 #define XDEV_LS (0x2 << 10)
295 #define XDEV_HS (0x3 << 10)
296 #define XDEV_SS (0x4 << 10)
297 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
298 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
299 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
300 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
301 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
302 /* Bits 20:23 in the Slot Context are the speed for the device */
303 #define SLOT_SPEED_FS (XDEV_FS << 10)
304 #define SLOT_SPEED_LS (XDEV_LS << 10)
305 #define SLOT_SPEED_HS (XDEV_HS << 10)
306 #define SLOT_SPEED_SS (XDEV_SS << 10)
307 /* Port Indicator Control */
308 #define PORT_LED_OFF (0 << 14)
309 #define PORT_LED_AMBER (1 << 14)
310 #define PORT_LED_GREEN (2 << 14)
311 #define PORT_LED_MASK (3 << 14)
312 /* Port Link State Write Strobe - set this when changing link state */
313 #define PORT_LINK_STROBE (1 << 16)
314 /* true: connect status change */
315 #define PORT_CSC (1 << 17)
316 /* true: port enable change */
317 #define PORT_PEC (1 << 18)
318 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
319 * into an enabled state, and the device into the default state. A "warm" reset
320 * also resets the link, forcing the device through the link training sequence.
321 * SW can also look at the Port Reset register to see when warm reset is done.
322 */
323 #define PORT_WRC (1 << 19)
324 /* true: over-current change */
325 #define PORT_OCC (1 << 20)
326 /* true: reset change - 1 to 0 transition of PORT_RESET */
327 #define PORT_RC (1 << 21)
328 /* port link status change - set on some port link state transitions:
329 * Transition Reason
330 * ------------------------------------------------------------------------------
331 * - U3 to Resume Wakeup signaling from a device
332 * - Resume to Recovery to U0 USB 3.0 device resume
333 * - Resume to U0 USB 2.0 device resume
334 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
335 * - U3 to U0 Software resume of USB 2.0 device complete
336 * - U2 to U0 L1 resume of USB 2.1 device complete
337 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
338 * - U0 to disabled L1 entry error with USB 2.1 device
339 * - Any state to inactive Error on USB 3.0 port
340 */
341 #define PORT_PLC (1 << 22)
342 /* port configure error change - port failed to configure its link partner */
343 #define PORT_CEC (1 << 23)
344 /* Cold Attach Status - xHC can set this bit to report device attached during
345 * Sx state. Warm port reset should be perfomed to clear this bit and move port
346 * to connected state.
347 */
348 #define PORT_CAS (1 << 24)
349 /* wake on connect (enable) */
350 #define PORT_WKCONN_E (1 << 25)
351 /* wake on disconnect (enable) */
352 #define PORT_WKDISC_E (1 << 26)
353 /* wake on over-current (enable) */
354 #define PORT_WKOC_E (1 << 27)
355 /* bits 28:29 reserved */
356 /* true: device is removable - for USB 3.0 roothub emulation */
357 #define PORT_DEV_REMOVE (1 << 30)
358 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
359 #define PORT_WR (1 << 31)
360
361 /* We mark duplicate entries with -1 */
362 #define DUPLICATE_ENTRY ((u8)(-1))
363
364 /* Port Power Management Status and Control - port_power_base bitmasks */
365 /* Inactivity timer value for transitions into U1, in microseconds.
366 * Timeout can be up to 127us. 0xFF means an infinite timeout.
367 */
368 #define PORT_U1_TIMEOUT(p) ((p) & 0xff)
369 /* Inactivity timer value for transitions into U2 */
370 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
371 /* Bits 24:31 for port testing */
372
373 /* USB2 Protocol PORTSPMSC */
374 #define PORT_L1S_MASK 7
375 #define PORT_L1S_SUCCESS 1
376 #define PORT_RWE (1 << 3)
377 #define PORT_HIRD(p) (((p) & 0xf) << 4)
378 #define PORT_HIRD_MASK (0xf << 4)
379 #define PORT_L1DS(p) (((p) & 0xff) << 8)
380 #define PORT_HLE (1 << 16)
381
382 /**
383 * struct xhci_intr_reg - Interrupt Register Set
384 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
385 * interrupts and check for pending interrupts.
386 * @irq_control: IMOD - Interrupt Moderation Register.
387 * Used to throttle interrupts.
388 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
389 * @erst_base: ERST base address.
390 * @erst_dequeue: Event ring dequeue pointer.
391 *
392 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
393 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
394 * multiple segments of the same size. The HC places events on the ring and
395 * "updates the Cycle bit in the TRBs to indicate to software the current
396 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
397 * updates the dequeue pointer.
398 */
399 struct xhci_intr_reg {
400 __le32 irq_pending;
401 __le32 irq_control;
402 __le32 erst_size;
403 __le32 rsvd;
404 __le64 erst_base;
405 __le64 erst_dequeue;
406 };
407
408 /* irq_pending bitmasks */
409 #define ER_IRQ_PENDING(p) ((p) & 0x1)
410 /* bits 2:31 need to be preserved */
411 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
412 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
413 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
414 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
415
416 /* irq_control bitmasks */
417 /* Minimum interval between interrupts (in 250ns intervals). The interval
418 * between interrupts will be longer if there are no events on the event ring.
419 * Default is 4000 (1 ms).
420 */
421 #define ER_IRQ_INTERVAL_MASK (0xffff)
422 /* Counter used to count down the time to the next interrupt - HW use only */
423 #define ER_IRQ_COUNTER_MASK (0xffff << 16)
424
425 /* erst_size bitmasks */
426 /* Preserve bits 16:31 of erst_size */
427 #define ERST_SIZE_MASK (0xffff << 16)
428
429 /* erst_dequeue bitmasks */
430 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
431 * where the current dequeue pointer lies. This is an optional HW hint.
432 */
433 #define ERST_DESI_MASK (0x7)
434 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
435 * a work queue (or delayed service routine)?
436 */
437 #define ERST_EHB (1 << 3)
438 #define ERST_PTR_MASK (0xf)
439
440 /**
441 * struct xhci_run_regs
442 * @microframe_index:
443 * MFINDEX - current microframe number
444 *
445 * Section 5.5 Host Controller Runtime Registers:
446 * "Software should read and write these registers using only Dword (32 bit)
447 * or larger accesses"
448 */
449 struct xhci_run_regs {
450 __le32 microframe_index;
451 __le32 rsvd[7];
452 struct xhci_intr_reg ir_set[128];
453 };
454
455 /**
456 * struct doorbell_array
457 *
458 * Bits 0 - 7: Endpoint target
459 * Bits 8 - 15: RsvdZ
460 * Bits 16 - 31: Stream ID
461 *
462 * Section 5.6
463 */
464 struct xhci_doorbell_array {
465 __le32 doorbell[256];
466 };
467
468 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
469 #define DB_VALUE_HOST 0x00000000
470
471 /**
472 * struct xhci_protocol_caps
473 * @revision: major revision, minor revision, capability ID,
474 * and next capability pointer.
475 * @name_string: Four ASCII characters to say which spec this xHC
476 * follows, typically "USB ".
477 * @port_info: Port offset, count, and protocol-defined information.
478 */
479 struct xhci_protocol_caps {
480 u32 revision;
481 u32 name_string;
482 u32 port_info;
483 };
484
485 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
486 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
487 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
488
489 /**
490 * struct xhci_container_ctx
491 * @type: Type of context. Used to calculated offsets to contained contexts.
492 * @size: Size of the context data
493 * @bytes: The raw context data given to HW
494 * @dma: dma address of the bytes
495 *
496 * Represents either a Device or Input context. Holds a pointer to the raw
497 * memory used for the context (bytes) and dma address of it (dma).
498 */
499 struct xhci_container_ctx {
500 unsigned type;
501 #define XHCI_CTX_TYPE_DEVICE 0x1
502 #define XHCI_CTX_TYPE_INPUT 0x2
503
504 int size;
505
506 u8 *bytes;
507 dma_addr_t dma;
508 };
509
510 /**
511 * struct xhci_slot_ctx
512 * @dev_info: Route string, device speed, hub info, and last valid endpoint
513 * @dev_info2: Max exit latency for device number, root hub port number
514 * @tt_info: tt_info is used to construct split transaction tokens
515 * @dev_state: slot state and device address
516 *
517 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
518 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
519 * reserved at the end of the slot context for HC internal use.
520 */
521 struct xhci_slot_ctx {
522 __le32 dev_info;
523 __le32 dev_info2;
524 __le32 tt_info;
525 __le32 dev_state;
526 /* offset 0x10 to 0x1f reserved for HC internal use */
527 __le32 reserved[4];
528 };
529
530 /* dev_info bitmasks */
531 /* Route String - 0:19 */
532 #define ROUTE_STRING_MASK (0xfffff)
533 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
534 #define DEV_SPEED (0xf << 20)
535 /* bit 24 reserved */
536 /* Is this LS/FS device connected through a HS hub? - bit 25 */
537 #define DEV_MTT (0x1 << 25)
538 /* Set if the device is a hub - bit 26 */
539 #define DEV_HUB (0x1 << 26)
540 /* Index of the last valid endpoint context in this device context - 27:31 */
541 #define LAST_CTX_MASK (0x1f << 27)
542 #define LAST_CTX(p) ((p) << 27)
543 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
544 #define SLOT_FLAG (1 << 0)
545 #define EP0_FLAG (1 << 1)
546
547 /* dev_info2 bitmasks */
548 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
549 #define MAX_EXIT (0xffff)
550 /* Root hub port number that is needed to access the USB device */
551 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
552 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
553 /* Maximum number of ports under a hub device */
554 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
555
556 /* tt_info bitmasks */
557 /*
558 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
559 * The Slot ID of the hub that isolates the high speed signaling from
560 * this low or full-speed device. '0' if attached to root hub port.
561 */
562 #define TT_SLOT (0xff)
563 /*
564 * The number of the downstream facing port of the high-speed hub
565 * '0' if the device is not low or full speed.
566 */
567 #define TT_PORT (0xff << 8)
568 #define TT_THINK_TIME(p) (((p) & 0x3) << 16)
569
570 /* dev_state bitmasks */
571 /* USB device address - assigned by the HC */
572 #define DEV_ADDR_MASK (0xff)
573 /* bits 8:26 reserved */
574 /* Slot state */
575 #define SLOT_STATE (0x1f << 27)
576 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
577
578 #define SLOT_STATE_DISABLED 0
579 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
580 #define SLOT_STATE_DEFAULT 1
581 #define SLOT_STATE_ADDRESSED 2
582 #define SLOT_STATE_CONFIGURED 3
583
584 /**
585 * struct xhci_ep_ctx
586 * @ep_info: endpoint state, streams, mult, and interval information.
587 * @ep_info2: information on endpoint type, max packet size, max burst size,
588 * error count, and whether the HC will force an event for all
589 * transactions.
590 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
591 * defines one stream, this points to the endpoint transfer ring.
592 * Otherwise, it points to a stream context array, which has a
593 * ring pointer for each flow.
594 * @tx_info:
595 * Average TRB lengths for the endpoint ring and
596 * max payload within an Endpoint Service Interval Time (ESIT).
597 *
598 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
599 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
600 * reserved at the end of the endpoint context for HC internal use.
601 */
602 struct xhci_ep_ctx {
603 __le32 ep_info;
604 __le32 ep_info2;
605 __le64 deq;
606 __le32 tx_info;
607 /* offset 0x14 - 0x1f reserved for HC internal use */
608 __le32 reserved[3];
609 };
610
611 /* ep_info bitmasks */
612 /*
613 * Endpoint State - bits 0:2
614 * 0 - disabled
615 * 1 - running
616 * 2 - halted due to halt condition - ok to manipulate endpoint ring
617 * 3 - stopped
618 * 4 - TRB error
619 * 5-7 - reserved
620 */
621 #define EP_STATE_MASK (0xf)
622 #define EP_STATE_DISABLED 0
623 #define EP_STATE_RUNNING 1
624 #define EP_STATE_HALTED 2
625 #define EP_STATE_STOPPED 3
626 #define EP_STATE_ERROR 4
627 /* Mult - Max number of burtst within an interval, in EP companion desc. */
628 #define EP_MULT(p) (((p) & 0x3) << 8)
629 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
630 /* bits 10:14 are Max Primary Streams */
631 /* bit 15 is Linear Stream Array */
632 /* Interval - period between requests to an endpoint - 125u increments. */
633 #define EP_INTERVAL(p) (((p) & 0xff) << 16)
634 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
635 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
636 #define EP_MAXPSTREAMS_MASK (0x1f << 10)
637 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
638 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
639 #define EP_HAS_LSA (1 << 15)
640
641 /* ep_info2 bitmasks */
642 /*
643 * Force Event - generate transfer events for all TRBs for this endpoint
644 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
645 */
646 #define FORCE_EVENT (0x1)
647 #define ERROR_COUNT(p) (((p) & 0x3) << 1)
648 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
649 #define EP_TYPE(p) ((p) << 3)
650 #define ISOC_OUT_EP 1
651 #define BULK_OUT_EP 2
652 #define INT_OUT_EP 3
653 #define CTRL_EP 4
654 #define ISOC_IN_EP 5
655 #define BULK_IN_EP 6
656 #define INT_IN_EP 7
657 /* bit 6 reserved */
658 /* bit 7 is Host Initiate Disable - for disabling stream selection */
659 #define MAX_BURST(p) (((p)&0xff) << 8)
660 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
661 #define MAX_PACKET(p) (((p)&0xffff) << 16)
662 #define MAX_PACKET_MASK (0xffff << 16)
663 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
664
665 /* Get max packet size from ep desc. Bit 10..0 specify the max packet size.
666 * USB2.0 spec 9.6.6.
667 */
668 #define GET_MAX_PACKET(p) ((p) & 0x7ff)
669
670 /* tx_info bitmasks */
671 #define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff)
672 #define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16)
673 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
674
675 /* deq bitmasks */
676 #define EP_CTX_CYCLE_MASK (1 << 0)
677
678
679 /**
680 * struct xhci_input_control_context
681 * Input control context; see section 6.2.5.
682 *
683 * @drop_context: set the bit of the endpoint context you want to disable
684 * @add_context: set the bit of the endpoint context you want to enable
685 */
686 struct xhci_input_control_ctx {
687 __le32 drop_flags;
688 __le32 add_flags;
689 __le32 rsvd2[6];
690 };
691
692 #define EP_IS_ADDED(ctrl_ctx, i) \
693 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
694 #define EP_IS_DROPPED(ctrl_ctx, i) \
695 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
696
697 /* Represents everything that is needed to issue a command on the command ring.
698 * It's useful to pre-allocate these for commands that cannot fail due to
699 * out-of-memory errors, like freeing streams.
700 */
701 struct xhci_command {
702 /* Input context for changing device state */
703 struct xhci_container_ctx *in_ctx;
704 u32 status;
705 /* If completion is null, no one is waiting on this command
706 * and the structure can be freed after the command completes.
707 */
708 struct completion *completion;
709 union xhci_trb *command_trb;
710 struct list_head cmd_list;
711 };
712
713 /* drop context bitmasks */
714 #define DROP_EP(x) (0x1 << x)
715 /* add context bitmasks */
716 #define ADD_EP(x) (0x1 << x)
717
718 struct xhci_stream_ctx {
719 /* 64-bit stream ring address, cycle state, and stream type */
720 __le64 stream_ring;
721 /* offset 0x14 - 0x1f reserved for HC internal use */
722 __le32 reserved[2];
723 };
724
725 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
726 #define SCT_FOR_CTX(p) (((p) << 1) & 0x7)
727 /* Secondary stream array type, dequeue pointer is to a transfer ring */
728 #define SCT_SEC_TR 0
729 /* Primary stream array type, dequeue pointer is to a transfer ring */
730 #define SCT_PRI_TR 1
731 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
732 #define SCT_SSA_8 2
733 #define SCT_SSA_16 3
734 #define SCT_SSA_32 4
735 #define SCT_SSA_64 5
736 #define SCT_SSA_128 6
737 #define SCT_SSA_256 7
738
739 /* Assume no secondary streams for now */
740 struct xhci_stream_info {
741 struct xhci_ring **stream_rings;
742 /* Number of streams, including stream 0 (which drivers can't use) */
743 unsigned int num_streams;
744 /* The stream context array may be bigger than
745 * the number of streams the driver asked for
746 */
747 struct xhci_stream_ctx *stream_ctx_array;
748 unsigned int num_stream_ctxs;
749 dma_addr_t ctx_array_dma;
750 /* For mapping physical TRB addresses to segments in stream rings */
751 struct radix_tree_root trb_address_map;
752 struct xhci_command *free_streams_command;
753 };
754
755 #define SMALL_STREAM_ARRAY_SIZE 256
756 #define MEDIUM_STREAM_ARRAY_SIZE 1024
757
758 /* Some Intel xHCI host controllers need software to keep track of the bus
759 * bandwidth. Keep track of endpoint info here. Each root port is allocated
760 * the full bus bandwidth. We must also treat TTs (including each port under a
761 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
762 * (DMI) also limits the total bandwidth (across all domains) that can be used.
763 */
764 struct xhci_bw_info {
765 /* ep_interval is zero-based */
766 unsigned int ep_interval;
767 /* mult and num_packets are one-based */
768 unsigned int mult;
769 unsigned int num_packets;
770 unsigned int max_packet_size;
771 unsigned int max_esit_payload;
772 unsigned int type;
773 };
774
775 /* "Block" sizes in bytes the hardware uses for different device speeds.
776 * The logic in this part of the hardware limits the number of bits the hardware
777 * can use, so must represent bandwidth in a less precise manner to mimic what
778 * the scheduler hardware computes.
779 */
780 #define FS_BLOCK 1
781 #define HS_BLOCK 4
782 #define SS_BLOCK 16
783 #define DMI_BLOCK 32
784
785 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
786 * with each byte transferred. SuperSpeed devices have an initial overhead to
787 * set up bursts. These are in blocks, see above. LS overhead has already been
788 * translated into FS blocks.
789 */
790 #define DMI_OVERHEAD 8
791 #define DMI_OVERHEAD_BURST 4
792 #define SS_OVERHEAD 8
793 #define SS_OVERHEAD_BURST 32
794 #define HS_OVERHEAD 26
795 #define FS_OVERHEAD 20
796 #define LS_OVERHEAD 128
797 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per
798 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
799 * of overhead associated with split transfers crossing microframe boundaries.
800 * 31 blocks is pure protocol overhead.
801 */
802 #define TT_HS_OVERHEAD (31 + 94)
803 #define TT_DMI_OVERHEAD (25 + 12)
804
805 /* Bandwidth limits in blocks */
806 #define FS_BW_LIMIT 1285
807 #define TT_BW_LIMIT 1320
808 #define HS_BW_LIMIT 1607
809 #define SS_BW_LIMIT_IN 3906
810 #define DMI_BW_LIMIT_IN 3906
811 #define SS_BW_LIMIT_OUT 3906
812 #define DMI_BW_LIMIT_OUT 3906
813
814 /* Percentage of bus bandwidth reserved for non-periodic transfers */
815 #define FS_BW_RESERVED 10
816 #define HS_BW_RESERVED 20
817 #define SS_BW_RESERVED 10
818
819 struct xhci_virt_ep {
820 struct xhci_ring *ring;
821 /* Related to endpoints that are configured to use stream IDs only */
822 struct xhci_stream_info *stream_info;
823 /* Temporary storage in case the configure endpoint command fails and we
824 * have to restore the device state to the previous state
825 */
826 struct xhci_ring *new_ring;
827 unsigned int ep_state;
828 #define SET_DEQ_PENDING (1 << 0)
829 #define EP_HALTED (1 << 1) /* For stall handling */
830 #define EP_HALT_PENDING (1 << 2) /* For URB cancellation */
831 /* Transitioning the endpoint to using streams, don't enqueue URBs */
832 #define EP_GETTING_STREAMS (1 << 3)
833 #define EP_HAS_STREAMS (1 << 4)
834 /* Transitioning the endpoint to not using streams, don't enqueue URBs */
835 #define EP_GETTING_NO_STREAMS (1 << 5)
836 /* ---- Related to URB cancellation ---- */
837 struct list_head cancelled_td_list;
838 /* The TRB that was last reported in a stopped endpoint ring */
839 union xhci_trb *stopped_trb;
840 struct xhci_td *stopped_td;
841 unsigned int stopped_stream;
842 /* Watchdog timer for stop endpoint command to cancel URBs */
843 struct timer_list stop_cmd_timer;
844 int stop_cmds_pending;
845 struct xhci_hcd *xhci;
846 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
847 * command. We'll need to update the ring's dequeue segment and dequeue
848 * pointer after the command completes.
849 */
850 struct xhci_segment *queued_deq_seg;
851 union xhci_trb *queued_deq_ptr;
852 /*
853 * Sometimes the xHC can not process isochronous endpoint ring quickly
854 * enough, and it will miss some isoc tds on the ring and generate
855 * a Missed Service Error Event.
856 * Set skip flag when receive a Missed Service Error Event and
857 * process the missed tds on the endpoint ring.
858 */
859 bool skip;
860 /* Bandwidth checking storage */
861 struct xhci_bw_info bw_info;
862 struct list_head bw_endpoint_list;
863 };
864
865 enum xhci_overhead_type {
866 LS_OVERHEAD_TYPE = 0,
867 FS_OVERHEAD_TYPE,
868 HS_OVERHEAD_TYPE,
869 };
870
871 struct xhci_interval_bw {
872 unsigned int num_packets;
873 /* Sorted by max packet size.
874 * Head of the list is the greatest max packet size.
875 */
876 struct list_head endpoints;
877 /* How many endpoints of each speed are present. */
878 unsigned int overhead[3];
879 };
880
881 #define XHCI_MAX_INTERVAL 16
882
883 struct xhci_interval_bw_table {
884 unsigned int interval0_esit_payload;
885 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
886 /* Includes reserved bandwidth for async endpoints */
887 unsigned int bw_used;
888 unsigned int ss_bw_in;
889 unsigned int ss_bw_out;
890 };
891
892
893 struct xhci_virt_device {
894 struct usb_device *udev;
895 /*
896 * Commands to the hardware are passed an "input context" that
897 * tells the hardware what to change in its data structures.
898 * The hardware will return changes in an "output context" that
899 * software must allocate for the hardware. We need to keep
900 * track of input and output contexts separately because
901 * these commands might fail and we don't trust the hardware.
902 */
903 struct xhci_container_ctx *out_ctx;
904 /* Used for addressing devices and configuration changes */
905 struct xhci_container_ctx *in_ctx;
906 /* Rings saved to ensure old alt settings can be re-instated */
907 struct xhci_ring **ring_cache;
908 int num_rings_cached;
909 /* Store xHC assigned device address */
910 int address;
911 #define XHCI_MAX_RINGS_CACHED 31
912 struct xhci_virt_ep eps[31];
913 struct completion cmd_completion;
914 /* Status of the last command issued for this device */
915 u32 cmd_status;
916 struct list_head cmd_list;
917 u8 fake_port;
918 u8 real_port;
919 struct xhci_interval_bw_table *bw_table;
920 struct xhci_tt_bw_info *tt_info;
921 };
922
923 /*
924 * For each roothub, keep track of the bandwidth information for each periodic
925 * interval.
926 *
927 * If a high speed hub is attached to the roothub, each TT associated with that
928 * hub is a separate bandwidth domain. The interval information for the
929 * endpoints on the devices under that TT will appear in the TT structure.
930 */
931 struct xhci_root_port_bw_info {
932 struct list_head tts;
933 unsigned int num_active_tts;
934 struct xhci_interval_bw_table bw_table;
935 };
936
937 struct xhci_tt_bw_info {
938 struct list_head tt_list;
939 int slot_id;
940 int ttport;
941 struct xhci_interval_bw_table bw_table;
942 int active_eps;
943 };
944
945
946 /**
947 * struct xhci_device_context_array
948 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
949 */
950 struct xhci_device_context_array {
951 /* 64-bit device addresses; we only write 32-bit addresses */
952 __le64 dev_context_ptrs[MAX_HC_SLOTS];
953 /* private xHCD pointers */
954 dma_addr_t dma;
955 };
956 /* TODO: write function to set the 64-bit device DMA address */
957 /*
958 * TODO: change this to be dynamically sized at HC mem init time since the HC
959 * might not be able to handle the maximum number of devices possible.
960 */
961
962
963 struct xhci_transfer_event {
964 /* 64-bit buffer address, or immediate data */
965 __le64 buffer;
966 __le32 transfer_len;
967 /* This field is interpreted differently based on the type of TRB */
968 __le32 flags;
969 };
970
971 /* Transfer event TRB length bit mask */
972 /* bits 0:23 */
973 #define EVENT_TRB_LEN(p) ((p) & 0xffffff)
974
975 /** Transfer Event bit fields **/
976 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
977
978 /* Completion Code - only applicable for some types of TRBs */
979 #define COMP_CODE_MASK (0xff << 24)
980 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
981 #define COMP_SUCCESS 1
982 /* Data Buffer Error */
983 #define COMP_DB_ERR 2
984 /* Babble Detected Error */
985 #define COMP_BABBLE 3
986 /* USB Transaction Error */
987 #define COMP_TX_ERR 4
988 /* TRB Error - some TRB field is invalid */
989 #define COMP_TRB_ERR 5
990 /* Stall Error - USB device is stalled */
991 #define COMP_STALL 6
992 /* Resource Error - HC doesn't have memory for that device configuration */
993 #define COMP_ENOMEM 7
994 /* Bandwidth Error - not enough room in schedule for this dev config */
995 #define COMP_BW_ERR 8
996 /* No Slots Available Error - HC ran out of device slots */
997 #define COMP_ENOSLOTS 9
998 /* Invalid Stream Type Error */
999 #define COMP_STREAM_ERR 10
1000 /* Slot Not Enabled Error - doorbell rung for disabled device slot */
1001 #define COMP_EBADSLT 11
1002 /* Endpoint Not Enabled Error */
1003 #define COMP_EBADEP 12
1004 /* Short Packet */
1005 #define COMP_SHORT_TX 13
1006 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
1007 #define COMP_UNDERRUN 14
1008 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
1009 #define COMP_OVERRUN 15
1010 /* Virtual Function Event Ring Full Error */
1011 #define COMP_VF_FULL 16
1012 /* Parameter Error - Context parameter is invalid */
1013 #define COMP_EINVAL 17
1014 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
1015 #define COMP_BW_OVER 18
1016 /* Context State Error - illegal context state transition requested */
1017 #define COMP_CTX_STATE 19
1018 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
1019 #define COMP_PING_ERR 20
1020 /* Event Ring is full */
1021 #define COMP_ER_FULL 21
1022 /* Incompatible Device Error */
1023 #define COMP_DEV_ERR 22
1024 /* Missed Service Error - HC couldn't service an isoc ep within interval */
1025 #define COMP_MISSED_INT 23
1026 /* Successfully stopped command ring */
1027 #define COMP_CMD_STOP 24
1028 /* Successfully aborted current command and stopped command ring */
1029 #define COMP_CMD_ABORT 25
1030 /* Stopped - transfer was terminated by a stop endpoint command */
1031 #define COMP_STOP 26
1032 /* Same as COMP_EP_STOPPED, but the transferred length in the event is invalid */
1033 #define COMP_STOP_INVAL 27
1034 /* Control Abort Error - Debug Capability - control pipe aborted */
1035 #define COMP_DBG_ABORT 28
1036 /* Max Exit Latency Too Large Error */
1037 #define COMP_MEL_ERR 29
1038 /* TRB type 30 reserved */
1039 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
1040 #define COMP_BUFF_OVER 31
1041 /* Event Lost Error - xHC has an "internal event overrun condition" */
1042 #define COMP_ISSUES 32
1043 /* Undefined Error - reported when other error codes don't apply */
1044 #define COMP_UNKNOWN 33
1045 /* Invalid Stream ID Error */
1046 #define COMP_STRID_ERR 34
1047 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
1048 #define COMP_2ND_BW_ERR 35
1049 /* Split Transaction Error */
1050 #define COMP_SPLIT_ERR 36
1051
1052 struct xhci_link_trb {
1053 /* 64-bit segment pointer*/
1054 __le64 segment_ptr;
1055 __le32 intr_target;
1056 __le32 control;
1057 };
1058
1059 /* control bitfields */
1060 #define LINK_TOGGLE (0x1<<1)
1061
1062 /* Command completion event TRB */
1063 struct xhci_event_cmd {
1064 /* Pointer to command TRB, or the value passed by the event data trb */
1065 __le64 cmd_trb;
1066 __le32 status;
1067 __le32 flags;
1068 };
1069
1070 /* flags bitmasks */
1071 /* bits 16:23 are the virtual function ID */
1072 /* bits 24:31 are the slot ID */
1073 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1074 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1075
1076 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1077 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1078 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1079
1080 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1081 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1082 #define LAST_EP_INDEX 30
1083
1084 /* Set TR Dequeue Pointer command TRB fields */
1085 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1086 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1087
1088
1089 /* Port Status Change Event TRB fields */
1090 /* Port ID - bits 31:24 */
1091 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1092
1093 /* Normal TRB fields */
1094 /* transfer_len bitmasks - bits 0:16 */
1095 #define TRB_LEN(p) ((p) & 0x1ffff)
1096 /* Interrupter Target - which MSI-X vector to target the completion event at */
1097 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1098 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1099 #define TRB_TBC(p) (((p) & 0x3) << 7)
1100 #define TRB_TLBPC(p) (((p) & 0xf) << 16)
1101
1102 /* Cycle bit - indicates TRB ownership by HC or HCD */
1103 #define TRB_CYCLE (1<<0)
1104 /*
1105 * Force next event data TRB to be evaluated before task switch.
1106 * Used to pass OS data back after a TD completes.
1107 */
1108 #define TRB_ENT (1<<1)
1109 /* Interrupt on short packet */
1110 #define TRB_ISP (1<<2)
1111 /* Set PCIe no snoop attribute */
1112 #define TRB_NO_SNOOP (1<<3)
1113 /* Chain multiple TRBs into a TD */
1114 #define TRB_CHAIN (1<<4)
1115 /* Interrupt on completion */
1116 #define TRB_IOC (1<<5)
1117 /* The buffer pointer contains immediate data */
1118 #define TRB_IDT (1<<6)
1119
1120 /* Block Event Interrupt */
1121 #define TRB_BEI (1<<9)
1122
1123 /* Control transfer TRB specific fields */
1124 #define TRB_DIR_IN (1<<16)
1125 #define TRB_TX_TYPE(p) ((p) << 16)
1126 #define TRB_DATA_OUT 2
1127 #define TRB_DATA_IN 3
1128
1129 /* Isochronous TRB specific fields */
1130 #define TRB_SIA (1<<31)
1131
1132 struct xhci_generic_trb {
1133 __le32 field[4];
1134 };
1135
1136 union xhci_trb {
1137 struct xhci_link_trb link;
1138 struct xhci_transfer_event trans_event;
1139 struct xhci_event_cmd event_cmd;
1140 struct xhci_generic_trb generic;
1141 };
1142
1143 /* TRB bit mask */
1144 #define TRB_TYPE_BITMASK (0xfc00)
1145 #define TRB_TYPE(p) ((p) << 10)
1146 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1147 /* TRB type IDs */
1148 /* bulk, interrupt, isoc scatter/gather, and control data stage */
1149 #define TRB_NORMAL 1
1150 /* setup stage for control transfers */
1151 #define TRB_SETUP 2
1152 /* data stage for control transfers */
1153 #define TRB_DATA 3
1154 /* status stage for control transfers */
1155 #define TRB_STATUS 4
1156 /* isoc transfers */
1157 #define TRB_ISOC 5
1158 /* TRB for linking ring segments */
1159 #define TRB_LINK 6
1160 #define TRB_EVENT_DATA 7
1161 /* Transfer Ring No-op (not for the command ring) */
1162 #define TRB_TR_NOOP 8
1163 /* Command TRBs */
1164 /* Enable Slot Command */
1165 #define TRB_ENABLE_SLOT 9
1166 /* Disable Slot Command */
1167 #define TRB_DISABLE_SLOT 10
1168 /* Address Device Command */
1169 #define TRB_ADDR_DEV 11
1170 /* Configure Endpoint Command */
1171 #define TRB_CONFIG_EP 12
1172 /* Evaluate Context Command */
1173 #define TRB_EVAL_CONTEXT 13
1174 /* Reset Endpoint Command */
1175 #define TRB_RESET_EP 14
1176 /* Stop Transfer Ring Command */
1177 #define TRB_STOP_RING 15
1178 /* Set Transfer Ring Dequeue Pointer Command */
1179 #define TRB_SET_DEQ 16
1180 /* Reset Device Command */
1181 #define TRB_RESET_DEV 17
1182 /* Force Event Command (opt) */
1183 #define TRB_FORCE_EVENT 18
1184 /* Negotiate Bandwidth Command (opt) */
1185 #define TRB_NEG_BANDWIDTH 19
1186 /* Set Latency Tolerance Value Command (opt) */
1187 #define TRB_SET_LT 20
1188 /* Get port bandwidth Command */
1189 #define TRB_GET_BW 21
1190 /* Force Header Command - generate a transaction or link management packet */
1191 #define TRB_FORCE_HEADER 22
1192 /* No-op Command - not for transfer rings */
1193 #define TRB_CMD_NOOP 23
1194 /* TRB IDs 24-31 reserved */
1195 /* Event TRBS */
1196 /* Transfer Event */
1197 #define TRB_TRANSFER 32
1198 /* Command Completion Event */
1199 #define TRB_COMPLETION 33
1200 /* Port Status Change Event */
1201 #define TRB_PORT_STATUS 34
1202 /* Bandwidth Request Event (opt) */
1203 #define TRB_BANDWIDTH_EVENT 35
1204 /* Doorbell Event (opt) */
1205 #define TRB_DOORBELL 36
1206 /* Host Controller Event */
1207 #define TRB_HC_EVENT 37
1208 /* Device Notification Event - device sent function wake notification */
1209 #define TRB_DEV_NOTE 38
1210 /* MFINDEX Wrap Event - microframe counter wrapped */
1211 #define TRB_MFINDEX_WRAP 39
1212 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1213
1214 /* Nec vendor-specific command completion event. */
1215 #define TRB_NEC_CMD_COMP 48
1216 /* Get NEC firmware revision. */
1217 #define TRB_NEC_GET_FW 49
1218
1219 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1220 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1221 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1222 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1223 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1224 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1225
1226 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1227 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1228
1229 /*
1230 * TRBS_PER_SEGMENT must be a multiple of 4,
1231 * since the command ring is 64-byte aligned.
1232 * It must also be greater than 16.
1233 */
1234 #define TRBS_PER_SEGMENT 64
1235 /* Allow two commands + a link TRB, along with any reserved command TRBs */
1236 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1237 #define SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1238 #define SEGMENT_SHIFT (__ffs(SEGMENT_SIZE))
1239 /* TRB buffer pointers can't cross 64KB boundaries */
1240 #define TRB_MAX_BUFF_SHIFT 16
1241 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1242
1243 struct xhci_segment {
1244 union xhci_trb *trbs;
1245 /* private to HCD */
1246 struct xhci_segment *next;
1247 dma_addr_t dma;
1248 };
1249
1250 struct xhci_td {
1251 struct list_head td_list;
1252 struct list_head cancelled_td_list;
1253 struct urb *urb;
1254 struct xhci_segment *start_seg;
1255 union xhci_trb *first_trb;
1256 union xhci_trb *last_trb;
1257 };
1258
1259 /* xHCI command default timeout value */
1260 #define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ)
1261
1262 /* command descriptor */
1263 struct xhci_cd {
1264 struct list_head cancel_cmd_list;
1265 struct xhci_command *command;
1266 union xhci_trb *cmd_trb;
1267 };
1268
1269 struct xhci_dequeue_state {
1270 struct xhci_segment *new_deq_seg;
1271 union xhci_trb *new_deq_ptr;
1272 int new_cycle_state;
1273 };
1274
1275 enum xhci_ring_type {
1276 TYPE_CTRL = 0,
1277 TYPE_ISOC,
1278 TYPE_BULK,
1279 TYPE_INTR,
1280 TYPE_STREAM,
1281 TYPE_COMMAND,
1282 TYPE_EVENT,
1283 };
1284
1285 struct xhci_ring {
1286 struct xhci_segment *first_seg;
1287 struct xhci_segment *last_seg;
1288 union xhci_trb *enqueue;
1289 struct xhci_segment *enq_seg;
1290 unsigned int enq_updates;
1291 union xhci_trb *dequeue;
1292 struct xhci_segment *deq_seg;
1293 unsigned int deq_updates;
1294 struct list_head td_list;
1295 /*
1296 * Write the cycle state into the TRB cycle field to give ownership of
1297 * the TRB to the host controller (if we are the producer), or to check
1298 * if we own the TRB (if we are the consumer). See section 4.9.1.
1299 */
1300 u32 cycle_state;
1301 unsigned int stream_id;
1302 unsigned int num_segs;
1303 unsigned int num_trbs_free;
1304 unsigned int num_trbs_free_temp;
1305 enum xhci_ring_type type;
1306 bool last_td_was_short;
1307 };
1308
1309 struct xhci_erst_entry {
1310 /* 64-bit event ring segment address */
1311 __le64 seg_addr;
1312 __le32 seg_size;
1313 /* Set to zero */
1314 __le32 rsvd;
1315 };
1316
1317 struct xhci_erst {
1318 struct xhci_erst_entry *entries;
1319 unsigned int num_entries;
1320 /* xhci->event_ring keeps track of segment dma addresses */
1321 dma_addr_t erst_dma_addr;
1322 /* Num entries the ERST can contain */
1323 unsigned int erst_size;
1324 };
1325
1326 struct xhci_scratchpad {
1327 u64 *sp_array;
1328 dma_addr_t sp_dma;
1329 void **sp_buffers;
1330 dma_addr_t *sp_dma_buffers;
1331 };
1332
1333 struct urb_priv {
1334 int length;
1335 int td_cnt;
1336 struct xhci_td *td[0];
1337 };
1338
1339 /*
1340 * Each segment table entry is 4*32bits long. 1K seems like an ok size:
1341 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1342 * meaning 64 ring segments.
1343 * Initial allocated size of the ERST, in number of entries */
1344 #define ERST_NUM_SEGS 1
1345 /* Initial allocated size of the ERST, in number of entries */
1346 #define ERST_SIZE 64
1347 /* Initial number of event segment rings allocated */
1348 #define ERST_ENTRIES 1
1349 /* Poll every 60 seconds */
1350 #define POLL_TIMEOUT 60
1351 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1352 #define XHCI_STOP_EP_CMD_TIMEOUT 5
1353 /* XXX: Make these module parameters */
1354
1355 struct s3_save {
1356 u32 command;
1357 u32 dev_nt;
1358 u64 dcbaa_ptr;
1359 u32 config_reg;
1360 u32 irq_pending;
1361 u32 irq_control;
1362 u32 erst_size;
1363 u64 erst_base;
1364 u64 erst_dequeue;
1365 };
1366
1367 /* Use for lpm */
1368 struct dev_info {
1369 u32 dev_id;
1370 struct list_head list;
1371 };
1372
1373 struct xhci_bus_state {
1374 unsigned long bus_suspended;
1375 unsigned long next_statechange;
1376
1377 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1378 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1379 u32 port_c_suspend;
1380 u32 suspended_ports;
1381 u32 port_remote_wakeup;
1382 unsigned long resume_done[USB_MAXCHILDREN];
1383 /* which ports have started to resume */
1384 unsigned long resuming_ports;
1385 };
1386
hcd_index(struct usb_hcd * hcd)1387 static inline unsigned int hcd_index(struct usb_hcd *hcd)
1388 {
1389 if (hcd->speed == HCD_USB3)
1390 return 0;
1391 else
1392 return 1;
1393 }
1394
1395 /* There is one xhci_hcd structure per controller */
1396 struct xhci_hcd {
1397 struct usb_hcd *main_hcd;
1398 struct usb_hcd *shared_hcd;
1399 /* glue to PCI and HCD framework */
1400 struct xhci_cap_regs __iomem *cap_regs;
1401 struct xhci_op_regs __iomem *op_regs;
1402 struct xhci_run_regs __iomem *run_regs;
1403 struct xhci_doorbell_array __iomem *dba;
1404 /* Our HCD's current interrupter register set */
1405 struct xhci_intr_reg __iomem *ir_set;
1406
1407 /* Cached register copies of read-only HC data */
1408 __u32 hcs_params1;
1409 __u32 hcs_params2;
1410 __u32 hcs_params3;
1411 __u32 hcc_params;
1412
1413 spinlock_t lock;
1414
1415 /* packed release number */
1416 u8 sbrn;
1417 u16 hci_version;
1418 u8 max_slots;
1419 u8 max_interrupters;
1420 u8 max_ports;
1421 u8 isoc_threshold;
1422 int event_ring_max;
1423 int addr_64;
1424 /* 4KB min, 128MB max */
1425 int page_size;
1426 /* Valid values are 12 to 20, inclusive */
1427 int page_shift;
1428 /* msi-x vectors */
1429 int msix_count;
1430 struct msix_entry *msix_entries;
1431 /* data structures */
1432 struct xhci_device_context_array *dcbaa;
1433 struct xhci_ring *cmd_ring;
1434 unsigned int cmd_ring_state;
1435 #define CMD_RING_STATE_RUNNING (1 << 0)
1436 #define CMD_RING_STATE_ABORTED (1 << 1)
1437 #define CMD_RING_STATE_STOPPED (1 << 2)
1438 struct list_head cancel_cmd_list;
1439 unsigned int cmd_ring_reserved_trbs;
1440 struct xhci_ring *event_ring;
1441 struct xhci_erst erst;
1442 /* Scratchpad */
1443 struct xhci_scratchpad *scratchpad;
1444 /* Store LPM test failed devices' information */
1445 struct list_head lpm_failed_devs;
1446
1447 /* slot enabling and address device helpers */
1448 struct completion addr_dev;
1449 int slot_id;
1450 /* Internal mirror of the HW's dcbaa */
1451 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1452 /* For keeping track of bandwidth domains per roothub. */
1453 struct xhci_root_port_bw_info *rh_bw;
1454
1455 /* DMA pools */
1456 struct dma_pool *device_pool;
1457 struct dma_pool *segment_pool;
1458 struct dma_pool *small_streams_pool;
1459 struct dma_pool *medium_streams_pool;
1460
1461 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1462 /* Poll the rings - for debugging */
1463 struct timer_list event_ring_timer;
1464 int zombie;
1465 #endif
1466 /* Host controller watchdog timer structures */
1467 unsigned int xhc_state;
1468
1469 u32 command;
1470 struct s3_save s3;
1471 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1472 *
1473 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1474 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1475 * that sees this status (other than the timer that set it) should stop touching
1476 * hardware immediately. Interrupt handlers should return immediately when
1477 * they see this status (any time they drop and re-acquire xhci->lock).
1478 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1479 * putting the TD on the canceled list, etc.
1480 *
1481 * There are no reports of xHCI host controllers that display this issue.
1482 */
1483 #define XHCI_STATE_DYING (1 << 0)
1484 #define XHCI_STATE_HALTED (1 << 1)
1485 /* Statistics */
1486 int error_bitmask;
1487 unsigned int quirks;
1488 #define XHCI_LINK_TRB_QUIRK (1 << 0)
1489 #define XHCI_RESET_EP_QUIRK (1 << 1)
1490 #define XHCI_NEC_HOST (1 << 2)
1491 #define XHCI_AMD_PLL_FIX (1 << 3)
1492 #define XHCI_SPURIOUS_SUCCESS (1 << 4)
1493 /*
1494 * Certain Intel host controllers have a limit to the number of endpoint
1495 * contexts they can handle. Ideally, they would signal that they can't handle
1496 * anymore endpoint contexts by returning a Resource Error for the Configure
1497 * Endpoint command, but they don't. Instead they expect software to keep track
1498 * of the number of active endpoints for them, across configure endpoint
1499 * commands, reset device commands, disable slot commands, and address device
1500 * commands.
1501 */
1502 #define XHCI_EP_LIMIT_QUIRK (1 << 5)
1503 #define XHCI_BROKEN_MSI (1 << 6)
1504 #define XHCI_RESET_ON_RESUME (1 << 7)
1505 #define XHCI_SW_BW_CHECKING (1 << 8)
1506 #define XHCI_AMD_0x96_HOST (1 << 9)
1507 #define XHCI_TRUST_TX_LENGTH (1 << 10)
1508 #define XHCI_SPURIOUS_REBOOT (1 << 13)
1509 #define XHCI_COMP_MODE_QUIRK (1 << 14)
1510 #define XHCI_AVOID_BEI (1 << 15)
1511 #define XHCI_PLAT (1 << 16)
1512 #define XHCI_SLOW_SUSPEND (1 << 17)
1513 #define XHCI_SPURIOUS_WAKEUP (1 << 18)
1514 unsigned int num_active_eps;
1515 unsigned int limit_active_eps;
1516 /* There are two roothubs to keep track of bus suspend info for */
1517 struct xhci_bus_state bus_state[2];
1518 /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */
1519 u8 *port_array;
1520 /* Array of pointers to USB 3.0 PORTSC registers */
1521 __le32 __iomem **usb3_ports;
1522 unsigned int num_usb3_ports;
1523 /* Array of pointers to USB 2.0 PORTSC registers */
1524 __le32 __iomem **usb2_ports;
1525 unsigned int num_usb2_ports;
1526 /* support xHCI 0.96 spec USB2 software LPM */
1527 unsigned sw_lpm_support:1;
1528 /* support xHCI 1.0 spec USB2 hardware LPM */
1529 unsigned hw_lpm_support:1;
1530 /* Compliance Mode Recovery Data */
1531 struct timer_list comp_mode_recovery_timer;
1532 u32 port_status_u0;
1533 /* Compliance Mode Timer Triggered every 2 seconds */
1534 #define COMP_MODE_RCVRY_MSECS 2000
1535 };
1536
1537 /* convert between an HCD pointer and the corresponding EHCI_HCD */
hcd_to_xhci(struct usb_hcd * hcd)1538 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1539 {
1540 return *((struct xhci_hcd **) (hcd->hcd_priv));
1541 }
1542
xhci_to_hcd(struct xhci_hcd * xhci)1543 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1544 {
1545 return xhci->main_hcd;
1546 }
1547
1548 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1549 #define XHCI_DEBUG 1
1550 #else
1551 #define XHCI_DEBUG 0
1552 #endif
1553
1554 #define xhci_dbg(xhci, fmt, args...) \
1555 do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1556 #define xhci_info(xhci, fmt, args...) \
1557 do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1558 #define xhci_err(xhci, fmt, args...) \
1559 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1560 #define xhci_warn(xhci, fmt, args...) \
1561 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1562
1563 /* TODO: copied from ehci.h - can be refactored? */
1564 /* xHCI spec says all registers are little endian */
xhci_readl(const struct xhci_hcd * xhci,__le32 __iomem * regs)1565 static inline unsigned int xhci_readl(const struct xhci_hcd *xhci,
1566 __le32 __iomem *regs)
1567 {
1568 return readl(regs);
1569 }
xhci_writel(struct xhci_hcd * xhci,const unsigned int val,__le32 __iomem * regs)1570 static inline void xhci_writel(struct xhci_hcd *xhci,
1571 const unsigned int val, __le32 __iomem *regs)
1572 {
1573 writel(val, regs);
1574 }
1575
1576 /*
1577 * Registers should always be accessed with double word or quad word accesses.
1578 *
1579 * Some xHCI implementations may support 64-bit address pointers. Registers
1580 * with 64-bit address pointers should be written to with dword accesses by
1581 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1582 * xHCI implementations that do not support 64-bit address pointers will ignore
1583 * the high dword, and write order is irrelevant.
1584 */
xhci_read_64(const struct xhci_hcd * xhci,__le64 __iomem * regs)1585 static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1586 __le64 __iomem *regs)
1587 {
1588 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1589 u64 val_lo = readl(ptr);
1590 u64 val_hi = readl(ptr + 1);
1591 return val_lo + (val_hi << 32);
1592 }
xhci_write_64(struct xhci_hcd * xhci,const u64 val,__le64 __iomem * regs)1593 static inline void xhci_write_64(struct xhci_hcd *xhci,
1594 const u64 val, __le64 __iomem *regs)
1595 {
1596 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1597 u32 val_lo = lower_32_bits(val);
1598 u32 val_hi = upper_32_bits(val);
1599
1600 writel(val_lo, ptr);
1601 writel(val_hi, ptr + 1);
1602 }
1603
xhci_link_trb_quirk(struct xhci_hcd * xhci)1604 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1605 {
1606 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
1607 }
1608
1609 /* xHCI debugging */
1610 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num);
1611 void xhci_print_registers(struct xhci_hcd *xhci);
1612 void xhci_dbg_regs(struct xhci_hcd *xhci);
1613 void xhci_print_run_regs(struct xhci_hcd *xhci);
1614 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb);
1615 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb);
1616 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg);
1617 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring);
1618 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1619 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
1620 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring);
1621 void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep);
1622 char *xhci_get_slot_state(struct xhci_hcd *xhci,
1623 struct xhci_container_ctx *ctx);
1624 void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
1625 unsigned int slot_id, unsigned int ep_index,
1626 struct xhci_virt_ep *ep);
1627
1628 /* xHCI memory management */
1629 void xhci_mem_cleanup(struct xhci_hcd *xhci);
1630 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1631 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1632 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1633 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1634 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1635 struct usb_device *udev);
1636 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1637 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
1638 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index);
1639 unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1640 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1641 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
1642 struct xhci_bw_info *ep_bw,
1643 struct xhci_interval_bw_table *bw_table,
1644 struct usb_device *udev,
1645 struct xhci_virt_ep *virt_ep,
1646 struct xhci_tt_bw_info *tt_info);
1647 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1648 struct xhci_virt_device *virt_dev,
1649 int old_active_eps);
1650 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1651 void xhci_update_bw_info(struct xhci_hcd *xhci,
1652 struct xhci_container_ctx *in_ctx,
1653 struct xhci_input_control_ctx *ctrl_ctx,
1654 struct xhci_virt_device *virt_dev);
1655 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1656 struct xhci_container_ctx *in_ctx,
1657 struct xhci_container_ctx *out_ctx,
1658 unsigned int ep_index);
1659 void xhci_slot_copy(struct xhci_hcd *xhci,
1660 struct xhci_container_ctx *in_ctx,
1661 struct xhci_container_ctx *out_ctx);
1662 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1663 struct usb_device *udev, struct usb_host_endpoint *ep,
1664 gfp_t mem_flags);
1665 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1666 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
1667 unsigned int num_trbs, gfp_t flags);
1668 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
1669 struct xhci_virt_device *virt_dev,
1670 unsigned int ep_index);
1671 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1672 unsigned int num_stream_ctxs,
1673 unsigned int num_streams, gfp_t flags);
1674 void xhci_free_stream_info(struct xhci_hcd *xhci,
1675 struct xhci_stream_info *stream_info);
1676 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1677 struct xhci_ep_ctx *ep_ctx,
1678 struct xhci_stream_info *stream_info);
1679 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
1680 struct xhci_ep_ctx *ep_ctx,
1681 struct xhci_virt_ep *ep);
1682 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
1683 struct xhci_virt_device *virt_dev, bool drop_control_ep);
1684 struct xhci_ring *xhci_dma_to_transfer_ring(
1685 struct xhci_virt_ep *ep,
1686 u64 address);
1687 struct xhci_ring *xhci_stream_id_to_ring(
1688 struct xhci_virt_device *dev,
1689 unsigned int ep_index,
1690 unsigned int stream_id);
1691 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1692 bool allocate_in_ctx, bool allocate_completion,
1693 gfp_t mem_flags);
1694 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv);
1695 void xhci_free_command(struct xhci_hcd *xhci,
1696 struct xhci_command *command);
1697
1698 #ifdef CONFIG_PCI
1699 /* xHCI PCI glue */
1700 int xhci_register_pci(void);
1701 void xhci_unregister_pci(void);
1702 #else
xhci_register_pci(void)1703 static inline int xhci_register_pci(void) { return 0; }
xhci_unregister_pci(void)1704 static inline void xhci_unregister_pci(void) {}
1705 #endif
1706
1707 #if defined(CONFIG_USB_XHCI_PLATFORM) \
1708 || defined(CONFIG_USB_XHCI_PLATFORM_MODULE)
1709 int xhci_register_plat(void);
1710 void xhci_unregister_plat(void);
1711 #else
xhci_register_plat(void)1712 static inline int xhci_register_plat(void)
1713 { return 0; }
xhci_unregister_plat(void)1714 static inline void xhci_unregister_plat(void)
1715 { }
1716 #endif
1717
1718 /* xHCI host controller glue */
1719 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
1720 int handshake(struct xhci_hcd *xhci, void __iomem *ptr,
1721 u32 mask, u32 done, int usec);
1722 void xhci_quiesce(struct xhci_hcd *xhci);
1723 int xhci_halt(struct xhci_hcd *xhci);
1724 int xhci_reset(struct xhci_hcd *xhci);
1725 int xhci_init(struct usb_hcd *hcd);
1726 int xhci_run(struct usb_hcd *hcd);
1727 void xhci_stop(struct usb_hcd *hcd);
1728 void xhci_shutdown(struct usb_hcd *hcd);
1729 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
1730
1731 #ifdef CONFIG_PM
1732 int xhci_suspend(struct xhci_hcd *xhci);
1733 int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
1734 #else
1735 #define xhci_suspend NULL
1736 #define xhci_resume NULL
1737 #endif
1738
1739 int xhci_get_frame(struct usb_hcd *hcd);
1740 irqreturn_t xhci_irq(struct usb_hcd *hcd);
1741 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd);
1742 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1743 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
1744 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
1745 struct xhci_virt_device *virt_dev,
1746 struct usb_device *hdev,
1747 struct usb_tt *tt, gfp_t mem_flags);
1748 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
1749 struct usb_host_endpoint **eps, unsigned int num_eps,
1750 unsigned int num_streams, gfp_t mem_flags);
1751 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
1752 struct usb_host_endpoint **eps, unsigned int num_eps,
1753 gfp_t mem_flags);
1754 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
1755 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev);
1756 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
1757 struct usb_device *udev, int enable);
1758 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1759 struct usb_tt *tt, gfp_t mem_flags);
1760 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
1761 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
1762 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1763 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1764 void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
1765 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev);
1766 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1767 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1768
1769 /* xHCI ring, segment, TRB, and TD functions */
1770 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
1771 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1772 union xhci_trb *start_trb, union xhci_trb *end_trb,
1773 dma_addr_t suspect_dma);
1774 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
1775 void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1776 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id);
1777 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1778 u32 slot_id);
1779 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
1780 u32 field1, u32 field2, u32 field3, u32 field4);
1781 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
1782 unsigned int ep_index, int suspend);
1783 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1784 int slot_id, unsigned int ep_index);
1785 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1786 int slot_id, unsigned int ep_index);
1787 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1788 int slot_id, unsigned int ep_index);
1789 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
1790 struct urb *urb, int slot_id, unsigned int ep_index);
1791 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1792 u32 slot_id, bool command_must_succeed);
1793 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1794 u32 slot_id);
1795 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
1796 unsigned int ep_index);
1797 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id);
1798 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
1799 unsigned int slot_id, unsigned int ep_index,
1800 unsigned int stream_id, struct xhci_td *cur_td,
1801 struct xhci_dequeue_state *state);
1802 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
1803 unsigned int slot_id, unsigned int ep_index,
1804 unsigned int stream_id,
1805 struct xhci_dequeue_state *deq_state);
1806 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
1807 struct usb_device *udev, unsigned int ep_index);
1808 void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci,
1809 unsigned int slot_id, unsigned int ep_index,
1810 struct xhci_dequeue_state *deq_state);
1811 void xhci_stop_endpoint_command_watchdog(unsigned long arg);
1812 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
1813 union xhci_trb *cmd_trb);
1814 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
1815 unsigned int ep_index, unsigned int stream_id);
1816 union xhci_trb *xhci_find_next_enqueue(struct xhci_ring *ring);
1817
1818 /* xHCI roothub code */
1819 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1820 int port_id, u32 link_state);
1821 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1822 int port_id, u32 port_bit);
1823 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1824 char *buf, u16 wLength);
1825 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1826
1827 #ifdef CONFIG_PM
1828 int xhci_bus_suspend(struct usb_hcd *hcd);
1829 int xhci_bus_resume(struct usb_hcd *hcd);
1830 #else
1831 #define xhci_bus_suspend NULL
1832 #define xhci_bus_resume NULL
1833 #endif /* CONFIG_PM */
1834
1835 u32 xhci_port_state_to_neutral(u32 state);
1836 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
1837 u16 port);
1838 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
1839
1840 /* xHCI contexts */
1841 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1842 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1843 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1844
1845 #endif /* __LINUX_XHCI_HCD_H */
1846