1 /* 2 * bfin_sport.h - interface to Blackfin SPORTs 3 * 4 * Copyright 2004-2009 Analog Devices Inc. 5 * 6 * Licensed under the GPL-2 or later. 7 */ 8 9 #ifndef __BFIN_SPORT_H__ 10 #define __BFIN_SPORT_H__ 11 12 /* Sport mode: it can be set to TDM, i2s or others */ 13 #define NORM_MODE 0x0 14 #define TDM_MODE 0x1 15 #define I2S_MODE 0x2 16 #define NDSO_MODE 0x3 17 18 /* Data format, normal, a-law or u-law */ 19 #define NORM_FORMAT 0x0 20 #define ALAW_FORMAT 0x2 21 #define ULAW_FORMAT 0x3 22 23 /* Function driver which use sport must initialize the structure */ 24 struct sport_config { 25 /* TDM (multichannels), I2S or other mode */ 26 unsigned int mode:3; 27 28 /* if TDM mode is selected, channels must be set */ 29 int channels; /* Must be in 8 units */ 30 unsigned int frame_delay:4; /* Delay between frame sync pulse and first bit */ 31 32 /* I2S mode */ 33 unsigned int right_first:1; /* Right stereo channel first */ 34 35 /* In mormal mode, the following item need to be set */ 36 unsigned int lsb_first:1; /* order of transmit or receive data */ 37 unsigned int fsync:1; /* Frame sync required */ 38 unsigned int data_indep:1; /* data independent frame sync generated */ 39 unsigned int act_low:1; /* Active low TFS */ 40 unsigned int late_fsync:1; /* Late frame sync */ 41 unsigned int tckfe:1; 42 unsigned int sec_en:1; /* Secondary side enabled */ 43 44 /* Choose clock source */ 45 unsigned int int_clk:1; /* Internal or external clock */ 46 47 /* If external clock is used, the following fields are ignored */ 48 int serial_clk; 49 int fsync_clk; 50 51 unsigned int data_format:2; /* Normal, u-law or a-law */ 52 53 int word_len; /* How length of the word in bits, 3-32 bits */ 54 int dma_enabled; 55 }; 56 57 /* Userspace interface */ 58 #define SPORT_IOC_MAGIC 'P' 59 #define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config) 60 #define SPORT_IOC_GET_SYSTEMCLOCK _IOR('P', 0x02, unsigned long) 61 #define SPORT_IOC_SET_BAUDRATE _IOW('P', 0x03, unsigned long) 62 63 #ifdef __KERNEL__ 64 65 #include <linux/types.h> 66 67 /* 68 * All Blackfin system MMRs are padded to 32bits even if the register 69 * itself is only 16bits. So use a helper macro to streamline this. 70 */ 71 #define __BFP(m) u16 m; u16 __pad_##m 72 struct sport_register { 73 __BFP(tcr1); 74 __BFP(tcr2); 75 __BFP(tclkdiv); 76 __BFP(tfsdiv); 77 union { 78 u32 tx32; 79 u16 tx16; 80 }; 81 u32 __pad_tx; 82 union { 83 u32 rx32; /* use the anomaly wrapper below */ 84 u16 rx16; 85 }; 86 u32 __pad_rx; 87 __BFP(rcr1); 88 __BFP(rcr2); 89 __BFP(rclkdiv); 90 __BFP(rfsdiv); 91 __BFP(stat); 92 __BFP(chnl); 93 __BFP(mcmc1); 94 __BFP(mcmc2); 95 u32 mtcs0; 96 u32 mtcs1; 97 u32 mtcs2; 98 u32 mtcs3; 99 u32 mrcs0; 100 u32 mrcs1; 101 u32 mrcs2; 102 u32 mrcs3; 103 }; 104 #undef __BFP 105 106 struct bfin_snd_platform_data { 107 const unsigned short *pin_req; 108 }; 109 110 #define bfin_read_sport_rx32(base) \ 111 ({ \ 112 struct sport_register *__mmrs = (void *)base; \ 113 u32 __ret; \ 114 unsigned long flags; \ 115 if (ANOMALY_05000473) \ 116 local_irq_save(flags); \ 117 __ret = __mmrs->rx32; \ 118 if (ANOMALY_05000473) \ 119 local_irq_restore(flags); \ 120 __ret; \ 121 }) 122 123 #endif 124 125 /* SPORT_TCR1 Masks */ 126 #define TSPEN 0x0001 /* TX enable */ 127 #define ITCLK 0x0002 /* Internal TX Clock Select */ 128 #define TDTYPE 0x000C /* TX Data Formatting Select */ 129 #define DTYPE_NORM 0x0000 /* Data Format Normal */ 130 #define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ 131 #define DTYPE_ALAW 0x000C /* Compand Using A-Law */ 132 #define TLSBIT 0x0010 /* TX Bit Order */ 133 #define ITFS 0x0200 /* Internal TX Frame Sync Select */ 134 #define TFSR 0x0400 /* TX Frame Sync Required Select */ 135 #define DITFS 0x0800 /* Data Independent TX Frame Sync Select */ 136 #define LTFS 0x1000 /* Low TX Frame Sync Select */ 137 #define LATFS 0x2000 /* Late TX Frame Sync Select */ 138 #define TCKFE 0x4000 /* TX Clock Falling Edge Select */ 139 140 /* SPORT_TCR2 Masks */ 141 #define SLEN 0x001F /* SPORT TX Word Length (2 - 31) */ 142 #define DP_SLEN(x) BFIN_DEPOSIT(SLEN, x) 143 #define EX_SLEN(x) BFIN_EXTRACT(SLEN, x) 144 #define TXSE 0x0100 /* TX Secondary Enable */ 145 #define TSFSE 0x0200 /* TX Stereo Frame Sync Enable */ 146 #define TRFST 0x0400 /* TX Right-First Data Order */ 147 148 /* SPORT_RCR1 Masks */ 149 #define RSPEN 0x0001 /* RX enable */ 150 #define IRCLK 0x0002 /* Internal RX Clock Select */ 151 #define RDTYPE 0x000C /* RX Data Formatting Select */ 152 /* DTYPE_* defined above */ 153 #define RLSBIT 0x0010 /* RX Bit Order */ 154 #define IRFS 0x0200 /* Internal RX Frame Sync Select */ 155 #define RFSR 0x0400 /* RX Frame Sync Required Select */ 156 #define LRFS 0x1000 /* Low RX Frame Sync Select */ 157 #define LARFS 0x2000 /* Late RX Frame Sync Select */ 158 #define RCKFE 0x4000 /* RX Clock Falling Edge Select */ 159 160 /* SPORT_RCR2 Masks */ 161 /* SLEN defined above */ 162 #define RXSE 0x0100 /* RX Secondary Enable */ 163 #define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */ 164 #define RRFST 0x0400 /* Right-First Data Order */ 165 166 /* SPORT_STAT Masks */ 167 #define RXNE 0x0001 /* RX FIFO Not Empty Status */ 168 #define RUVF 0x0002 /* RX Underflow Status */ 169 #define ROVF 0x0004 /* RX Overflow Status */ 170 #define TXF 0x0008 /* TX FIFO Full Status */ 171 #define TUVF 0x0010 /* TX Underflow Status */ 172 #define TOVF 0x0020 /* TX Overflow Status */ 173 #define TXHRE 0x0040 /* TX Hold Register Empty */ 174 175 /* SPORT_MCMC1 Masks */ 176 #define SP_WOFF 0x03FF /* Multichannel Window Offset Field */ 177 #define DP_SP_WOFF(x) BFIN_DEPOSIT(SP_WOFF, x) 178 #define EX_SP_WOFF(x) BFIN_EXTRACT(SP_WOFF, x) 179 #define SP_WSIZE 0xF000 /* Multichannel Window Size Field */ 180 #define DP_SP_WSIZE(x) BFIN_DEPOSIT(SP_WSIZE, x) 181 #define EX_SP_WSIZE(x) BFIN_EXTRACT(SP_WSIZE, x) 182 183 /* SPORT_MCMC2 Masks */ 184 #define MCCRM 0x0003 /* Multichannel Clock Recovery Mode */ 185 #define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */ 186 #define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */ 187 #define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */ 188 #define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */ 189 #define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */ 190 #define MCMEN 0x0010 /* Multichannel Frame Mode Enable */ 191 #define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */ 192 #define MFD 0xF000 /* Multichannel Frame Delay */ 193 #define DP_MFD(x) BFIN_DEPOSIT(MFD, x) 194 #define EX_MFD(x) BFIN_EXTRACT(MFD, x) 195 196 #endif 197