1 #ifndef _TITAN_GE_H_
2 #define _TITAN_GE_H_
3
4 #include <linux/config.h>
5 #include <linux/version.h>
6 #include <linux/module.h>
7 #include <linux/kernel.h>
8 #include <linux/config.h>
9 #include <linux/spinlock.h>
10 #include <asm/addrspace.h> /* For KSEG1ADDR() */
11
12 /*
13 * These functions should be later moved to a more generic location since there
14 * will be others accessing it also
15 */
16
17 /*
18 * This is the way it works: LKB5 Base is at 0x0128. TITAN_BASE is defined in
19 * include/asm/titan_dep.h. TITAN_GE_BASE is the value in the TITAN_GE_LKB5
20 * register.
21 */
22
23 #ifdef CONFIG_MIPS64
24 #define TITAN_GE_BASE 0xfffffffffe000000
25 #else
26 #define TITAN_GE_BASE 0xfe000000
27 #endif
28
29 #define TITAN_GE_WRITE(offset, data) \
30 *(volatile u32 *)(TITAN_GE_BASE + offset) = data
31
32 #define TITAN_GE_READ(offset) *(volatile u32 *)(TITAN_GE_BASE + offset)
33
34 #ifndef msec_delay
35 #define msec_delay(x) do { if(in_interrupt()) { \
36 /* Don't mdelay in interrupt context! */ \
37 BUG(); \
38 } else { \
39 set_current_state(TASK_UNINTERRUPTIBLE); \
40 schedule_timeout((x * HZ)/1000); \
41 } } while(0)
42 #endif
43
44 #define TITAN_GE_PORT_0
45
46 #define TITAN_GE_SRAM_BASE_VIRTUAL 0xf4000000
47 #define TITAN_GE_SRAM_BASE_PHYSICAL 0xf4000000
48
49 #ifdef CONFIG_NET_FASTROUTE
50
51 #include <linux/if_arp.h>
52 #include <net/ip.h>
53
titan_accept_fastpath(struct net_device * dev,struct dst_entry * dst)54 static int titan_accept_fastpath(struct net_device *dev, struct dst_entry *dst)
55 {
56 struct net_device *odev = dst->dev;
57
58 if (dst->ops->protocol != __constant_htons(ETH_P_IP))
59 return -1;
60 if (odev->type != ARPHRD_ETHER || odev->accept_fastpath == NULL)
61 return -1;
62
63 return 0;
64 }
65 #endif
66
67
68 /*
69 * We may need these constants
70 */
71 #define TITAN_BIT0 0x00000001
72 #define TITAN_BIT1 0x00000002
73 #define TITAN_BIT2 0x00000004
74 #define TITAN_BIT3 0x00000008
75 #define TITAN_BIT4 0x00000010
76 #define TITAN_BIT5 0x00000020
77 #define TITAN_BIT6 0x00000040
78 #define TITAN_BIT7 0x00000080
79 #define TITAN_BIT8 0x00000100
80 #define TITAN_BIT9 0x00000200
81 #define TITAN_BIT10 0x00000400
82 #define TITAN_BIT11 0x00000800
83 #define TITAN_BIT12 0x00001000
84 #define TITAN_BIT13 0x00002000
85 #define TITAN_BIT14 0x00004000
86 #define TITAN_BIT15 0x00008000
87 #define TITAN_BIT16 0x00010000
88 #define TITAN_BIT17 0x00020000
89 #define TITAN_BIT18 0x00040000
90 #define TITAN_BIT19 0x00080000
91 #define TITAN_BIT20 0x00100000
92 #define TITAN_BIT21 0x00200000
93 #define TITAN_BIT22 0x00400000
94 #define TITAN_BIT23 0x00800000
95 #define TITAN_BIT24 0x01000000
96 #define TITAN_BIT25 0x02000000
97 #define TITAN_BIT26 0x04000000
98 #define TITAN_BIT27 0x08000000
99 #define TITAN_BIT28 0x10000000
100 #define TITAN_BIT29 0x20000000
101 #define TITAN_BIT30 0x40000000
102 #define TITAN_BIT31 0x80000000
103
104 /* Flow Control */
105 #define TITAN_GE_FC_NONE 0x0
106 #define TITAN_GE_FC_FULL 0x1
107 #define TITAN_GE_FC_TX_PAUSE 0x2
108 #define TITAN_GE_FC_RX_PAUSE 0x3
109
110 /* Duplex Settings */
111 #define TITAN_GE_FULL_DUPLEX 0x1
112 #define TITAN_GE_HALF_DUPLEX 0x2
113
114 /* Speed settings */
115 #define TITAN_GE_SPEED_1000 0x1
116 #define TITAN_GE_SPEED_100 0x2
117 #define TITAN_GE_SPEED_10 0x3
118
119 /* Debugging info only */
120 #undef TITAN_DEBUG
121
122 /* Support for Rx side NAPI */
123 #define TITAN_RX_NAPI
124
125 #ifdef CONFIG_MIPS64
126 #define TITAN_GE_IE_MASK 0xfffffffffb001b64
127 #define TITAN_GE_IE_STATUS 0xfffffffffb001b60
128 #else
129 #define TITAN_GE_IE_MASK 0xfb001b64
130 #define TITAN_GE_IE_STATUS 0xfb001b60
131 #endif
132
133 /* Support for Jumbo Frames */
134 #undef TITAN_GE_JUMBO_FRAMES
135
136 /* Rx buffer size */
137 #ifdef TITAN_GE_JUMBO_FRAMES
138 #define TITAN_GE_JUMBO_BUFSIZE 9080
139 #else
140 #define TITAN_GE_STD_BUFSIZE 1580
141 #endif
142
143 /* Default Tx Queue Size */
144 #define TITAN_GE_TX_QUEUE 128
145
146 /* Default Rx Queue Size */
147 #define TITAN_GE_RX_QUEUE 64
148
149 /*
150 * Tx and Rx Interrupt Coalescing parameter. These values are
151 * for 1 Ghz processor. Rx coalescing can be taken care of
152 * by NAPI. NAPI is adaptive and hence useful. Tx coalescing
153 * is not adaptive. Hence, these values need to be adjusted
154 * based on load, CPU speed etc.
155 */
156 #define TITAN_GE_RX_COAL 150
157 #define TITAN_GE_TX_COAL 300
158
159 #if defined(__BIG_ENDIAN)
160
161 /* Define the Rx descriptor */
162 typedef struct _eth_rx_desc {
163 u32 reserved; /* Unused */
164 u32 buffer_addr; /* CPU buffer address */
165 u32 cmd_sts; /* Command and Status */
166 u32 buffer; /* XDMA buffer address */
167 } titan_ge_rx_desc;
168
169 /* Define the Tx descriptor */
170 typedef struct _eth_tx_desc {
171 u16 cmd_sts; /* Command, Status and Buffer count */
172 u16 buffer_len; /* Length of the buffer */
173 u32 buffer_addr; /* Physical address of the buffer */
174 } titan_ge_tx_desc;
175
176 #elif defined(__LITTLE_ENDIAN)
177
178 /* Define the Rx descriptor */
179 typedef struct _eth_rx_desc {
180 u32 buffer_addr; /* Buffer address inclusive of checksum */
181 u32 cmd_sts; /* Command and Status info */
182 } titan_ge_rx_desc;
183
184 /* Define the Tx descriptor */
185 typedef struct _eth_tx_desc {
186 u32 buffer_addr; /* Physical address of the buffer */
187 u16 buffer_len; /* Length of the buffer */
188 u16 cmd_sts; /* Command, Status and Buffer count */
189 } titan_ge_tx_desc;
190 #else
191 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
192 #endif
193
194 /* Packet Structure */
195 typedef struct _pkt_info {
196 unsigned int len;
197 unsigned int cmd_sts;
198 unsigned int buffer;
199 struct sk_buff *skb;
200 unsigned int checksum;
201 } titan_ge_packet;
202
203
204 #define PHYS_CNT 2
205
206 /* Titan Port specific data structure */
207 typedef struct _eth_port_ctrl {
208 unsigned int port_num;
209 u8 port_mac_addr[6];
210
211 /* Rx descriptor pointers */
212 int rx_curr_desc_q, rx_used_desc_q;
213
214 /* Tx descriptor pointers */
215 int tx_curr_desc_q, tx_used_desc_q;
216
217 /* Rx descriptor area */
218 volatile titan_ge_rx_desc *rx_desc_area;
219 unsigned int rx_desc_area_size;
220 struct sk_buff* rx_skb[TITAN_GE_RX_QUEUE];
221
222 /* Tx Descriptor area */
223 volatile titan_ge_tx_desc *tx_desc_area;
224 unsigned int tx_desc_area_size;
225 struct sk_buff* tx_skb[TITAN_GE_TX_QUEUE];
226
227 /* Timeout task */
228 struct tq_struct tx_timeout_task;
229
230 /* DMA structures and handles */
231 dma_addr_t tx_dma;
232 dma_addr_t rx_dma;
233 dma_addr_t tx_dma_array[TITAN_GE_TX_QUEUE];
234
235 /* Device lock */
236 spinlock_t lock;
237
238 unsigned int tx_ring_skbs;
239 unsigned int rx_ring_size;
240 unsigned int tx_ring_size;
241 unsigned int rx_ring_skbs;
242
243 struct net_device_stats stats;
244
245 /* Tx and Rx coalescing */
246 unsigned long rx_int_coal;
247 unsigned long tx_int_coal;
248
249 /* Threshold for replenishing the Rx and Tx rings */
250 unsigned int tx_threshold;
251 unsigned int rx_threshold;
252
253 /* NAPI work limit */
254 unsigned int rx_work_limit;
255 } titan_ge_port_info;
256
257 /* Titan specific constants */
258 #define TITAN_ETH_PORT_IRQ 4
259
260 /* Max Rx buffer */
261 #define TITAN_GE_MAX_RX_BUFFER 65536
262
263 /* Tx and Rx Error */
264 #define TITAN_GE_ERROR
265
266 /* Rx Descriptor Command and Status */
267
268 #define TITAN_GE_RX_CRC_ERROR TITAN_BIT27 /* crc error */
269 #define TITAN_GE_RX_OVERFLOW_ERROR TITAN_BIT15 /* overflow */
270 #define TITAN_GE_RX_BUFFER_OWNED TITAN_BIT21 /* buffer ownership */
271 #define TITAN_GE_RX_STP TITAN_BIT31 /* start of packet */
272 #define TITAN_GE_RX_BAM TITAN_BIT30 /* broadcast address match */
273 #define TITAN_GE_RX_PAM TITAN_BIT28 /* physical address match */
274 #define TITAN_GE_RX_LAFM TITAN_BIT29 /* logical address filter match */
275 #define TITAN_GE_RX_VLAN TITAN_BIT26 /* virtual lans */
276 #define TITAN_GE_RX_PERR TITAN_BIT19 /* packet error */
277 #define TITAN_GE_RX_TRUNC TITAN_BIT20 /* packet size greater than 32 buffers */
278
279 /* Tx Descriptor Command */
280 #define TITAN_GE_TX_BUFFER_OWNED TITAN_BIT5 /* buffer ownership */
281 #define TITAN_GE_TX_ENABLE_INTERRUPT TITAN_BIT15 /* Interrupt Enable */
282
283 /* Return Status */
284 #define TITAN_OK 0x1 /* Good Status */
285 #define TITAN_ERROR 0x2 /* Error Status */
286
287 /* MIB specific register offset */
288 #define TITAN_GE_MSTATX_STATS_BASE_LOW 0x0800 /* MSTATX COUNTL[15:0] */
289 #define TITAN_GE_MSTATX_STATS_BASE_MID 0x0804 /* MSTATX COUNTM[15:0] */
290 #define TITAN_GE_MSTATX_STATS_BASE_HI 0x0808 /* MSTATX COUNTH[7:0] */
291 #define TITAN_GE_MSTATX_CONTROL 0x0828 /* MSTATX Control */
292 #define TITAN_GE_MSTATX_VARIABLE_SELECT 0x082C /* MSTATX Variable Select */
293
294 /* MIB counter offsets, add to the TITAN_GE_MSTATX_STATS_BASE_XXX */
295 #define TITAN_GE_MSTATX_RXFRAMESOK 0x0040
296 #define TITAN_GE_MSTATX_RXOCTETSOK 0x0050
297 #define TITAN_GE_MSTATX_RXFRAMES 0x0060
298 #define TITAN_GE_MSTATX_RXOCTETS 0x0070
299 #define TITAN_GE_MSTATX_RXUNICASTFRAMESOK 0x0080
300 #define TITAN_GE_MSTATX_RXBROADCASTFRAMESOK 0x0090
301 #define TITAN_GE_MSTATX_RXMULTICASTFRAMESOK 0x00A0
302 #define TITAN_GE_MSTATX_RXTAGGEDFRAMESOK 0x00B0
303 #define TITAN_GE_MSTATX_RXMACPAUSECONTROLFRAMESOK 0x00C0
304 #define TITAN_GE_MSTATX_RXMACCONTROLFRAMESOK 0x00D0
305 #define TITAN_GE_MSTATX_RXFCSERROR 0x00E0
306 #define TITAN_GE_MSTATX_RXALIGNMENTERROR 0x00F0
307 #define TITAN_GE_MSTATX_RXSYMBOLERROR 0x0100
308 #define TITAN_GE_MSTATX_RXLAYER1ERROR 0x0110
309 #define TITAN_GE_MSTATX_RXINRANGELENGTHERROR 0x0120
310 #define TITAN_GE_MSTATX_RXLONGLENGTHERROR 0x0130
311 #define TITAN_GE_MSTATX_RXLONGLENGTHCRCERROR 0x0140
312 #define TITAN_GE_MSTATX_RXSHORTLENGTHERROR 0x0150
313 #define TITAN_GE_MSTATX_RXSHORTLLENGTHCRCERROR 0x0160
314 #define TITAN_GE_MSTATX_RXFRAMES64OCTETS 0x0170
315 #define TITAN_GE_MSTATX_RXFRAMES65TO127OCTETS 0x0180
316 #define TITAN_GE_MSTATX_RXFRAMES128TO255OCTETS 0x0190
317 #define TITAN_GE_MSTATX_RXFRAMES256TO511OCTETS 0x01A0
318 #define TITAN_GE_MSTATX_RXFRAMES512TO1023OCTETS 0x01B0
319 #define TITAN_GE_MSTATX_RXFRAMES1024TO1518OCTETS 0x01C0
320 #define TITAN_GE_MSTATX_RXFRAMES1519TOMAXSIZE 0x01D0
321 #define TITAN_GE_MSTATX_RXSTATIONADDRESSFILTERED 0x01E0
322 #define TITAN_GE_MSTATX_RXVARIABLE 0x01F0
323 #define TITAN_GE_MSTATX_GENERICADDRESSFILTERED 0x0200
324 #define TITAN_GE_MSTATX_UNICASTFILTERED 0x0210
325 #define TITAN_GE_MSTATX_MULTICASTFILTERED 0x0220
326 #define TITAN_GE_MSTATX_BROADCASTFILTERED 0x0230
327 #define TITAN_GE_MSTATX_HASHFILTERED 0x0240
328 #define TITAN_GE_MSTATX_TXFRAMESOK 0x0250
329 #define TITAN_GE_MSTATX_TXOCTETSOK 0x0260
330 #define TITAN_GE_MSTATX_TXOCTETS 0x0270
331 #define TITAN_GE_MSTATX_TXTAGGEDFRAMESOK 0x0280
332 #define TITAN_GE_MSTATX_TXMACPAUSECONTROLFRAMESOK 0x0290
333 #define TITAN_GE_MSTATX_TXFCSERROR 0x02A0
334 #define TITAN_GE_MSTATX_TXSHORTLENGTHERROR 0x02B0
335 #define TITAN_GE_MSTATX_TXLONGLENGTHERROR 0x02C0
336 #define TITAN_GE_MSTATX_TXSYSTEMERROR 0x02D0
337 #define TITAN_GE_MSTATX_TXMACERROR 0x02E0
338 #define TITAN_GE_MSTATX_TXCARRIERSENSEERROR 0x02F0
339 #define TITAN_GE_MSTATX_TXSQETESTERROR 0x0300
340 #define TITAN_GE_MSTATX_TXUNICASTFRAMESOK 0x0310
341 #define TITAN_GE_MSTATX_TXBROADCASTFRAMESOK 0x0320
342 #define TITAN_GE_MSTATX_TXMULTICASTFRAMESOK 0x0330
343 #define TITAN_GE_MSTATX_TXUNICASTFRAMESATTEMPTED 0x0340
344 #define TITAN_GE_MSTATX_TXBROADCASTFRAMESATTEMPTED 0x0350
345 #define TITAN_GE_MSTATX_TXMULTICASTFRAMESATTEMPTED 0x0360
346 #define TITAN_GE_MSTATX_TXFRAMES64OCTETS 0x0370
347 #define TITAN_GE_MSTATX_TXFRAMES65TO127OCTETS 0x0380
348 #define TITAN_GE_MSTATX_TXFRAMES128TO255OCTETS 0x0390
349 #define TITAN_GE_MSTATX_TXFRAMES256TO511OCTETS 0x03A0
350 #define TITAN_GE_MSTATX_TXFRAMES512TO1023OCTETS 0x03B0
351 #define TITAN_GE_MSTATX_TXFRAMES1024TO1518OCTETS 0x03C0
352 #define TITAN_GE_MSTATX_TXFRAMES1519TOMAXSIZE 0x03D0
353 #define TITAN_GE_MSTATX_TXVARIABLE 0x03E0
354 #define TITAN_GE_MSTATX_RXSYSTEMERROR 0x03F0
355 #define TITAN_GE_MSTATX_SINGLECOLLISION 0x0400
356 #define TITAN_GE_MSTATX_MULTIPLECOLLISION 0x0410
357 #define TITAN_GE_MSTATX_DEFERREDXMISSIONS 0x0420
358 #define TITAN_GE_MSTATX_LATECOLLISIONS 0x0430
359 #define TITAN_GE_MSTATX_ABORTEDDUETOXSCOLLS 0x0440
360
361 /* Interrupt specific defines */
362 #define TITAN_GE_DEVICE_ID 0x0000 /* Device ID */
363 #define TITAN_GE_RESET 0x0004 /* Reset reg */
364 #define TITAN_GE_TSB_CTRL_0 0x000C /* TSB Control reg 0 */
365 #define TITAN_GE_TSB_CTRL_1 0x0010 /* TSB Control reg 1 */
366 #define TITAN_GE_INTR_GRP0_STATUS 0x0040 /* General Interrupt Group 0 Status */
367 #define TITAN_GE_INTR_XDMA_CORE_A 0x0048 /* XDMA Channel Interrupt Status, Core A*/
368 #define TITAN_GE_INTR_XDMA_CORE_B 0x004C /* XDMA Channel Interrupt Status, Core B*/
369 #define TITAN_GE_INTR_XDMA_IE 0x0058 /* XDMA Channel Interrupt Enable */
370 #define TITAN_GE_SDQPF_ECC_INTR 0x480C /* SDQPF ECC Interrupt Status */
371 #define TITAN_GE_SDQPF_RXFIFO_CTL 0x4828 /* SDQPF RxFifo Control and Interrupt Enb*/
372 #define TITAN_GE_SDQPF_RXFIFO_INTR 0x482C /* SDQPF RxFifo Interrupt Status */
373 #define TITAN_GE_SDQPF_TXFIFO_CTL 0x4928 /* SDQPF TxFifo Control and Interrupt Enb*/
374 #define TITAN_GE_SDQPF_TXFIFO_INTR 0x492C /* SDQPF TxFifo Interrupt Status */
375 #define TITAN_GE_SDQPF_RXFIFO_0 0x4840 /* SDQPF RxFIFO Enable */
376 #define TITAN_GE_SDQPF_TXFIFO_0 0x4940 /* SDQPF TxFIFO Enable */
377 #define TITAN_GE_XDMA_CONFIG 0x5000 /* XDMA Global Configuration */
378 #define TITAN_GE_XDMA_INTR_SUMMARY 0x5010 /* XDMA Interrupt Summary */
379 #define TITAN_GE_XDMA_BUFADDRPRE 0x5018 /* XDMA Buffer Address Prefix */
380 #define TITAN_GE_XDMA_DESCADDRPRE 0x501C /* XDMA Descriptor Address Prefix */
381 #define TITAN_GE_XDMA_PORTWEIGHT 0x502C /* XDMA Port Weight Configuration */
382
383 /* Rx MAC defines */
384 #define TITAN_GE_RMAC_CONFIG_1 0x1200 /* RMAC Configuration 1 */
385 #define TITAN_GE_RMAC_CONFIG_2 0x1204 /* RMAC Configuration 2 */
386 #define TITAN_GE_RMAC_MAX_FRAME_LEN 0x1208 /* RMAC Max Frame Length */
387 #define TITAN_GE_RMAC_STATION_HI 0x120C /* Rx Station Address High */
388 #define TITAN_GE_RMAC_STATION_MID 0x1210 /* Rx Station Address Middle */
389 #define TITAN_GE_RMAC_STATION_LOW 0x1214 /* Rx Station Address Low */
390 #define TITAN_GE_RMAC_LINK_CONFIG 0x1218 /* RMAC Link Configuration */
391
392 /* Tx MAC defines */
393 #define TITAN_GE_TMAC_CONFIG_1 0x1240 /* TMAC Configuration 1 */
394 #define TITAN_GE_TMAC_CONFIG_2 0x1244 /* TMAC Configuration 2 */
395 #define TITAN_GE_TMAC_IPG 0x1248 /* TMAC Inter-Packet Gap */
396 #define TITAN_GE_TMAC_STATION_HI 0x124C /* Tx Station Address High */
397 #define TITAN_GE_TMAC_STATION_MID 0x1250 /* Tx Station Address Middle */
398 #define TITAN_GE_TMAC_STATION_LOW 0x1254 /* Tx Station Address Low */
399 #define TITAN_GE_TMAC_MAX_FRAME_LEN 0x1258 /* TMAC Max Frame Length */
400 #define TITAN_GE_TMAC_MIN_FRAME_LEN 0x125C /* TMAC Min Frame Length */
401 #define TITAN_GE_TMAC_PAUSE_FRAME_TIME 0x1260 /* TMAC Pause Frame Time */
402 #define TITAN_GE_TMAC_PAUSE_FRAME_INTERVAL 0x1264 /* TMAC Pause Frame Interval */
403
404 /* GMII register */
405 #define TITAN_GE_GMII_INTERRUPT_STATUS 0x1348 /* GMII Interrupt Status */
406 #define TITAN_GE_GMII_CONFIG_GENERAL 0x134C /* GMII Configuration General */
407 #define TITAN_GE_GMII_CONFIG_MODE 0x1350 /* GMII Configuration Mode */
408
409 /* Tx and Rx XDMA defines */
410 #define TITAN_GE_INT_COALESCING 0x5030 /* Interrupt Coalescing */
411 #define TITAN_GE_CHANNEL0_CONFIG 0x5040 /* Channel 0 XDMA config */
412 #define TITAN_GE_CHANNEL0_INTERRUPT 0x504c /* Channel 0 Interrupt Status */
413 #define TITAN_GE_GDI_INTERRUPT_ENABLE 0x5050 /* IE for the GDI Errors */
414 #define TITAN_GE_CHANNEL0_PACKET 0x5060 /* Channel 0 Packet count */
415 #define TITAN_GE_CHANNEL0_BYTE 0x5064 /* Channel 0 Byte count */
416 #define TITAN_GE_CHANNEL0_TX_DESC 0x5054 /* Channel 0 Tx first desc */
417 #define TITAN_GE_CHANNEL0_RX_DESC 0x5058 /* Channel 0 Rx first desc */
418
419 /* AFX (Address Filter Exact) register offsets for Slice 0 */
420 #define TITAN_GE_AFX_EXACT_MATCH_LOW 0x1100 /* AFX Exact Match Address Low*/
421 #define TITAN_GE_AFX_EXACT_MATCH_MID 0x1104 /* AFX Exact Match Address Mid*/
422 #define TITAN_GE_AFX_EXACT_MATCH_HIGH 0x1108 /* AFX Exact Match Address Hi */
423 #define TITAN_GE_AFX_EXACT_MATCH_VID 0x110C /* AFX Exact Match VID */
424 #define TITAN_GE_AFX_MULTICAST_HASH_LOW 0x1110 /* AFX Multicast HASH Low */
425 #define TITAN_GE_AFX_MULTICAST_HASH_MIDLOW 0x1114 /* AFX Multicast HASH MidLow */
426 #define TITAN_GE_AFX_MULTICAST_HASH_MIDHI 0x1118 /* AFX Multicast HASH MidHi */
427 #define TITAN_GE_AFX_MULTICAST_HASH_HI 0x111C /* AFX Multicast HASH Hi */
428 #define TITAN_GE_AFX_ADDRS_FILTER_CTRL_0 0x1120 /* AFX Address Filter Ctrl 0 */
429 #define TITAN_GE_AFX_ADDRS_FILTER_CTRL_1 0x1124 /* AFX Address Filter Ctrl 1 */
430 #define TITAN_GE_AFX_ADDRS_FILTER_CTRL_2 0x1128 /* AFX Address Filter Ctrl 2 */
431
432 /* Traffic Groomer block */
433 #define TITAN_GE_TRTG_CONFIG 0x1000 /* TRTG Config */
434
435 #endif /* _TITAN_GE_H_ */
436
437