1 /* 2 * linux/arch/arm/mach-tegra/include/mach/pinmux.h 3 * 4 * Copyright (C) 2010 Google, Inc. 5 * 6 * This software is licensed under the terms of the GNU General Public 7 * License version 2, as published by the Free Software Foundation, and 8 * may be copied, distributed, and modified under those terms. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 */ 16 17 #ifndef __MACH_TEGRA_PINMUX_H 18 #define __MACH_TEGRA_PINMUX_H 19 20 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) 21 #include "pinmux-t2.h" 22 #else 23 #error "Undefined Tegra architecture" 24 #endif 25 26 enum tegra_mux_func { 27 TEGRA_MUX_RSVD = 0x8000, 28 TEGRA_MUX_RSVD1 = 0x8000, 29 TEGRA_MUX_RSVD2 = 0x8001, 30 TEGRA_MUX_RSVD3 = 0x8002, 31 TEGRA_MUX_RSVD4 = 0x8003, 32 TEGRA_MUX_NONE = -1, 33 TEGRA_MUX_AHB_CLK, 34 TEGRA_MUX_APB_CLK, 35 TEGRA_MUX_AUDIO_SYNC, 36 TEGRA_MUX_CRT, 37 TEGRA_MUX_DAP1, 38 TEGRA_MUX_DAP2, 39 TEGRA_MUX_DAP3, 40 TEGRA_MUX_DAP4, 41 TEGRA_MUX_DAP5, 42 TEGRA_MUX_DISPLAYA, 43 TEGRA_MUX_DISPLAYB, 44 TEGRA_MUX_EMC_TEST0_DLL, 45 TEGRA_MUX_EMC_TEST1_DLL, 46 TEGRA_MUX_GMI, 47 TEGRA_MUX_GMI_INT, 48 TEGRA_MUX_HDMI, 49 TEGRA_MUX_I2C, 50 TEGRA_MUX_I2C2, 51 TEGRA_MUX_I2C3, 52 TEGRA_MUX_IDE, 53 TEGRA_MUX_IRDA, 54 TEGRA_MUX_KBC, 55 TEGRA_MUX_MIO, 56 TEGRA_MUX_MIPI_HS, 57 TEGRA_MUX_NAND, 58 TEGRA_MUX_OSC, 59 TEGRA_MUX_OWR, 60 TEGRA_MUX_PCIE, 61 TEGRA_MUX_PLLA_OUT, 62 TEGRA_MUX_PLLC_OUT1, 63 TEGRA_MUX_PLLM_OUT1, 64 TEGRA_MUX_PLLP_OUT2, 65 TEGRA_MUX_PLLP_OUT3, 66 TEGRA_MUX_PLLP_OUT4, 67 TEGRA_MUX_PWM, 68 TEGRA_MUX_PWR_INTR, 69 TEGRA_MUX_PWR_ON, 70 TEGRA_MUX_RTCK, 71 TEGRA_MUX_SDIO1, 72 TEGRA_MUX_SDIO2, 73 TEGRA_MUX_SDIO3, 74 TEGRA_MUX_SDIO4, 75 TEGRA_MUX_SFLASH, 76 TEGRA_MUX_SPDIF, 77 TEGRA_MUX_SPI1, 78 TEGRA_MUX_SPI2, 79 TEGRA_MUX_SPI2_ALT, 80 TEGRA_MUX_SPI3, 81 TEGRA_MUX_SPI4, 82 TEGRA_MUX_TRACE, 83 TEGRA_MUX_TWC, 84 TEGRA_MUX_UARTA, 85 TEGRA_MUX_UARTB, 86 TEGRA_MUX_UARTC, 87 TEGRA_MUX_UARTD, 88 TEGRA_MUX_UARTE, 89 TEGRA_MUX_ULPI, 90 TEGRA_MUX_VI, 91 TEGRA_MUX_VI_SENSOR_CLK, 92 TEGRA_MUX_XIO, 93 TEGRA_MUX_SAFE, 94 TEGRA_MAX_MUX, 95 }; 96 97 enum tegra_pullupdown { 98 TEGRA_PUPD_NORMAL = 0, 99 TEGRA_PUPD_PULL_DOWN, 100 TEGRA_PUPD_PULL_UP, 101 }; 102 103 enum tegra_tristate { 104 TEGRA_TRI_NORMAL = 0, 105 TEGRA_TRI_TRISTATE = 1, 106 }; 107 108 enum tegra_vddio { 109 TEGRA_VDDIO_BB = 0, 110 TEGRA_VDDIO_LCD, 111 TEGRA_VDDIO_VI, 112 TEGRA_VDDIO_UART, 113 TEGRA_VDDIO_DDR, 114 TEGRA_VDDIO_NAND, 115 TEGRA_VDDIO_SYS, 116 TEGRA_VDDIO_AUDIO, 117 TEGRA_VDDIO_SD, 118 }; 119 120 struct tegra_pingroup_config { 121 enum tegra_pingroup pingroup; 122 enum tegra_mux_func func; 123 enum tegra_pullupdown pupd; 124 enum tegra_tristate tristate; 125 }; 126 127 enum tegra_slew { 128 TEGRA_SLEW_FASTEST = 0, 129 TEGRA_SLEW_FAST, 130 TEGRA_SLEW_SLOW, 131 TEGRA_SLEW_SLOWEST, 132 TEGRA_MAX_SLEW, 133 }; 134 135 enum tegra_pull_strength { 136 TEGRA_PULL_0 = 0, 137 TEGRA_PULL_1, 138 TEGRA_PULL_2, 139 TEGRA_PULL_3, 140 TEGRA_PULL_4, 141 TEGRA_PULL_5, 142 TEGRA_PULL_6, 143 TEGRA_PULL_7, 144 TEGRA_PULL_8, 145 TEGRA_PULL_9, 146 TEGRA_PULL_10, 147 TEGRA_PULL_11, 148 TEGRA_PULL_12, 149 TEGRA_PULL_13, 150 TEGRA_PULL_14, 151 TEGRA_PULL_15, 152 TEGRA_PULL_16, 153 TEGRA_PULL_17, 154 TEGRA_PULL_18, 155 TEGRA_PULL_19, 156 TEGRA_PULL_20, 157 TEGRA_PULL_21, 158 TEGRA_PULL_22, 159 TEGRA_PULL_23, 160 TEGRA_PULL_24, 161 TEGRA_PULL_25, 162 TEGRA_PULL_26, 163 TEGRA_PULL_27, 164 TEGRA_PULL_28, 165 TEGRA_PULL_29, 166 TEGRA_PULL_30, 167 TEGRA_PULL_31, 168 TEGRA_MAX_PULL, 169 }; 170 171 enum tegra_drive { 172 TEGRA_DRIVE_DIV_8 = 0, 173 TEGRA_DRIVE_DIV_4, 174 TEGRA_DRIVE_DIV_2, 175 TEGRA_DRIVE_DIV_1, 176 TEGRA_MAX_DRIVE, 177 }; 178 179 enum tegra_hsm { 180 TEGRA_HSM_DISABLE = 0, 181 TEGRA_HSM_ENABLE, 182 }; 183 184 enum tegra_schmitt { 185 TEGRA_SCHMITT_DISABLE = 0, 186 TEGRA_SCHMITT_ENABLE, 187 }; 188 189 struct tegra_drive_pingroup_config { 190 enum tegra_drive_pingroup pingroup; 191 enum tegra_hsm hsm; 192 enum tegra_schmitt schmitt; 193 enum tegra_drive drive; 194 enum tegra_pull_strength pull_down; 195 enum tegra_pull_strength pull_up; 196 enum tegra_slew slew_rising; 197 enum tegra_slew slew_falling; 198 }; 199 200 struct tegra_drive_pingroup_desc { 201 const char *name; 202 s16 reg; 203 }; 204 205 struct tegra_pingroup_desc { 206 const char *name; 207 int funcs[4]; 208 int func_safe; 209 int vddio; 210 s16 tri_reg; /* offset into the TRISTATE_REG_* register bank */ 211 s16 mux_reg; /* offset into the PIN_MUX_CTL_* register bank */ 212 s16 pupd_reg; /* offset into the PULL_UPDOWN_REG_* register bank */ 213 s8 tri_bit; /* offset into the TRISTATE_REG_* register bit */ 214 s8 mux_bit; /* offset into the PIN_MUX_CTL_* register bit */ 215 s8 pupd_bit; /* offset into the PULL_UPDOWN_REG_* register bit */ 216 }; 217 218 extern const struct tegra_pingroup_desc tegra_soc_pingroups[]; 219 extern const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[]; 220 221 int tegra_pinmux_set_tristate(enum tegra_pingroup pg, 222 enum tegra_tristate tristate); 223 int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg, 224 enum tegra_pullupdown pupd); 225 226 void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, 227 int len); 228 229 void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config, 230 int len); 231 void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config, 232 int len); 233 void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config, 234 int len); 235 void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config, 236 int len, enum tegra_tristate tristate); 237 void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config, 238 int len, enum tegra_pullupdown pupd); 239 #endif 240 241