1 /*
2 * OHCI HCD (Host Controller Driver) for USB.
3 *
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
6 *
7 * This file is licenced under the GPL.
8 */
9
10 /*
11 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
12 * __leXX (normally) or __beXX (given OHCI_BIG_ENDIAN), depending on the
13 * host controller implementation.
14 */
15 typedef __u32 __bitwise __hc32;
16 typedef __u16 __bitwise __hc16;
17
18 /*
19 * OHCI Endpoint Descriptor (ED) ... holds TD queue
20 * See OHCI spec, section 4.2
21 *
22 * This is a "Queue Head" for those transfers, which is why
23 * both EHCI and UHCI call similar structures a "QH".
24 */
25 struct ed {
26 /* first fields are hardware-specified */
27 __hc32 hwINFO; /* endpoint config bitmap */
28 /* info bits defined by hcd */
29 #define ED_DEQUEUE (1 << 27)
30 /* info bits defined by the hardware */
31 #define ED_ISO (1 << 15)
32 #define ED_SKIP (1 << 14)
33 #define ED_LOWSPEED (1 << 13)
34 #define ED_OUT (0x01 << 11)
35 #define ED_IN (0x02 << 11)
36 __hc32 hwTailP; /* tail of TD list */
37 __hc32 hwHeadP; /* head of TD list (hc r/w) */
38 #define ED_C (0x02) /* toggle carry */
39 #define ED_H (0x01) /* halted */
40 __hc32 hwNextED; /* next ED in list */
41
42 /* rest are purely for the driver's use */
43 dma_addr_t dma; /* addr of ED */
44 struct td *dummy; /* next TD to activate */
45
46 /* host's view of schedule */
47 struct ed *ed_next; /* on schedule or rm_list */
48 struct ed *ed_prev; /* for non-interrupt EDs */
49 struct list_head td_list; /* "shadow list" of our TDs */
50
51 /* create --> IDLE --> OPER --> ... --> IDLE --> destroy
52 * usually: OPER --> UNLINK --> (IDLE | OPER) --> ...
53 */
54 u8 state; /* ED_{IDLE,UNLINK,OPER} */
55 #define ED_IDLE 0x00 /* NOT linked to HC */
56 #define ED_UNLINK 0x01 /* being unlinked from hc */
57 #define ED_OPER 0x02 /* IS linked to hc */
58
59 u8 type; /* PIPE_{BULK,...} */
60
61 /* periodic scheduling params (for intr and iso) */
62 u8 branch;
63 u16 interval;
64 u16 load;
65 u16 last_iso; /* iso only */
66
67 /* HC may see EDs on rm_list until next frame (frame_no == tick) */
68 u16 tick;
69 } __attribute__ ((aligned(16)));
70
71 #define ED_MASK ((u32)~0x0f) /* strip hw status in low addr bits */
72
73
74 /*
75 * OHCI Transfer Descriptor (TD) ... one per transfer segment
76 * See OHCI spec, sections 4.3.1 (general = control/bulk/interrupt)
77 * and 4.3.2 (iso)
78 */
79 struct td {
80 /* first fields are hardware-specified */
81 __hc32 hwINFO; /* transfer info bitmask */
82
83 /* hwINFO bits for both general and iso tds: */
84 #define TD_CC 0xf0000000 /* condition code */
85 #define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
86 //#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
87 #define TD_DI 0x00E00000 /* frames before interrupt */
88 #define TD_DI_SET(X) (((X) & 0x07)<< 21)
89 /* these two bits are available for definition/use by HCDs in both
90 * general and iso tds ... others are available for only one type
91 */
92 #define TD_DONE 0x00020000 /* retired to donelist */
93 #define TD_ISO 0x00010000 /* copy of ED_ISO */
94
95 /* hwINFO bits for general tds: */
96 #define TD_EC 0x0C000000 /* error count */
97 #define TD_T 0x03000000 /* data toggle state */
98 #define TD_T_DATA0 0x02000000 /* DATA0 */
99 #define TD_T_DATA1 0x03000000 /* DATA1 */
100 #define TD_T_TOGGLE 0x00000000 /* uses ED_C */
101 #define TD_DP 0x00180000 /* direction/pid */
102 #define TD_DP_SETUP 0x00000000 /* SETUP pid */
103 #define TD_DP_IN 0x00100000 /* IN pid */
104 #define TD_DP_OUT 0x00080000 /* OUT pid */
105 /* 0x00180000 rsvd */
106 #define TD_R 0x00040000 /* round: short packets OK? */
107
108 /* (no hwINFO #defines yet for iso tds) */
109
110 __hc32 hwCBP; /* Current Buffer Pointer (or 0) */
111 __hc32 hwNextTD; /* Next TD Pointer */
112 __hc32 hwBE; /* Memory Buffer End Pointer */
113
114 /* PSW is only for ISO. Only 1 PSW entry is used, but on
115 * big-endian PPC hardware that's the second entry.
116 */
117 #define MAXPSW 2
118 __hc16 hwPSW [MAXPSW];
119
120 /* rest are purely for the driver's use */
121 __u8 index;
122 struct ed *ed;
123 struct td *td_hash; /* dma-->td hashtable */
124 struct td *next_dl_td;
125 struct urb *urb;
126
127 dma_addr_t td_dma; /* addr of this TD */
128 dma_addr_t data_dma; /* addr of data it points to */
129
130 struct list_head td_list; /* "shadow list", TDs on same ED */
131 } __attribute__ ((aligned(32))); /* c/b/i need 16; only iso needs 32 */
132
133 #define TD_MASK ((u32)~0x1f) /* strip hw status in low addr bits */
134
135 /*
136 * Hardware transfer status codes -- CC from td->hwINFO or td->hwPSW
137 */
138 #define TD_CC_NOERROR 0x00
139 #define TD_CC_CRC 0x01
140 #define TD_CC_BITSTUFFING 0x02
141 #define TD_CC_DATATOGGLEM 0x03
142 #define TD_CC_STALL 0x04
143 #define TD_DEVNOTRESP 0x05
144 #define TD_PIDCHECKFAIL 0x06
145 #define TD_UNEXPECTEDPID 0x07
146 #define TD_DATAOVERRUN 0x08
147 #define TD_DATAUNDERRUN 0x09
148 /* 0x0A, 0x0B reserved for hardware */
149 #define TD_BUFFEROVERRUN 0x0C
150 #define TD_BUFFERUNDERRUN 0x0D
151 /* 0x0E, 0x0F reserved for HCD */
152 #define TD_NOTACCESSED 0x0F
153
154
155 /* map OHCI TD status codes (CC) to errno values */
156 static const int cc_to_error [16] = {
157 /* No Error */ 0,
158 /* CRC Error */ -EILSEQ,
159 /* Bit Stuff */ -EPROTO,
160 /* Data Togg */ -EILSEQ,
161 /* Stall */ -EPIPE,
162 /* DevNotResp */ -ETIME,
163 /* PIDCheck */ -EPROTO,
164 /* UnExpPID */ -EPROTO,
165 /* DataOver */ -EOVERFLOW,
166 /* DataUnder */ -EREMOTEIO,
167 /* (for hw) */ -EIO,
168 /* (for hw) */ -EIO,
169 /* BufferOver */ -ECOMM,
170 /* BuffUnder */ -ENOSR,
171 /* (for HCD) */ -EALREADY,
172 /* (for HCD) */ -EALREADY
173 };
174
175
176 /*
177 * The HCCA (Host Controller Communications Area) is a 256 byte
178 * structure defined section 4.4.1 of the OHCI spec. The HC is
179 * told the base address of it. It must be 256-byte aligned.
180 */
181 struct ohci_hcca {
182 #define NUM_INTS 32
183 __hc32 int_table [NUM_INTS]; /* periodic schedule */
184
185 /*
186 * OHCI defines u16 frame_no, followed by u16 zero pad.
187 * Since some processors can't do 16 bit bus accesses,
188 * portable access must be a 32 bits wide.
189 */
190 __hc32 frame_no; /* current frame number */
191 __hc32 done_head; /* info returned for an interrupt */
192 u8 reserved_for_hc [116];
193 u8 what [4]; /* spec only identifies 252 bytes :) */
194 } __attribute__ ((aligned(256)));
195
196 /*
197 * This is the structure of the OHCI controller's memory mapped I/O region.
198 * You must use readl() and writel() (in <asm/io.h>) to access these fields!!
199 * Layout is in section 7 (and appendix B) of the spec.
200 */
201 struct ohci_regs {
202 /* control and status registers (section 7.1) */
203 __hc32 revision;
204 __hc32 control;
205 __hc32 cmdstatus;
206 __hc32 intrstatus;
207 __hc32 intrenable;
208 __hc32 intrdisable;
209
210 /* memory pointers (section 7.2) */
211 __hc32 hcca;
212 __hc32 ed_periodcurrent;
213 __hc32 ed_controlhead;
214 __hc32 ed_controlcurrent;
215 __hc32 ed_bulkhead;
216 __hc32 ed_bulkcurrent;
217 __hc32 donehead;
218
219 /* frame counters (section 7.3) */
220 __hc32 fminterval;
221 __hc32 fmremaining;
222 __hc32 fmnumber;
223 __hc32 periodicstart;
224 __hc32 lsthresh;
225
226 /* Root hub ports (section 7.4) */
227 struct ohci_roothub_regs {
228 __hc32 a;
229 __hc32 b;
230 __hc32 status;
231 #define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports (RH_A_NDP) */
232 __hc32 portstatus [MAX_ROOT_PORTS];
233 } roothub;
234
235 /* and optional "legacy support" registers (appendix B) at 0x0100 */
236
237 } __attribute__ ((aligned(32)));
238
239
240 /* OHCI CONTROL AND STATUS REGISTER MASKS */
241
242 /*
243 * HcControl (control) register masks
244 */
245 #define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
246 #define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
247 #define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
248 #define OHCI_CTRL_CLE (1 << 4) /* control list enable */
249 #define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
250 #define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
251 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
252 #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
253 #define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
254
255 /* pre-shifted values for HCFS */
256 # define OHCI_USB_RESET (0 << 6)
257 # define OHCI_USB_RESUME (1 << 6)
258 # define OHCI_USB_OPER (2 << 6)
259 # define OHCI_USB_SUSPEND (3 << 6)
260
261 /*
262 * HcCommandStatus (cmdstatus) register masks
263 */
264 #define OHCI_HCR (1 << 0) /* host controller reset */
265 #define OHCI_CLF (1 << 1) /* control list filled */
266 #define OHCI_BLF (1 << 2) /* bulk list filled */
267 #define OHCI_OCR (1 << 3) /* ownership change request */
268 #define OHCI_SOC (3 << 16) /* scheduling overrun count */
269
270 /*
271 * masks used with interrupt registers:
272 * HcInterruptStatus (intrstatus)
273 * HcInterruptEnable (intrenable)
274 * HcInterruptDisable (intrdisable)
275 */
276 #define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
277 #define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
278 #define OHCI_INTR_SF (1 << 2) /* start frame */
279 #define OHCI_INTR_RD (1 << 3) /* resume detect */
280 #define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
281 #define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
282 #define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
283 #define OHCI_INTR_OC (1 << 30) /* ownership change */
284 #define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
285
286
287 /* OHCI ROOT HUB REGISTER MASKS */
288
289 /* roothub.portstatus [i] bits */
290 #define RH_PS_CCS 0x00000001 /* current connect status */
291 #define RH_PS_PES 0x00000002 /* port enable status*/
292 #define RH_PS_PSS 0x00000004 /* port suspend status */
293 #define RH_PS_POCI 0x00000008 /* port over current indicator */
294 #define RH_PS_PRS 0x00000010 /* port reset status */
295 #define RH_PS_PPS 0x00000100 /* port power status */
296 #define RH_PS_LSDA 0x00000200 /* low speed device attached */
297 #define RH_PS_CSC 0x00010000 /* connect status change */
298 #define RH_PS_PESC 0x00020000 /* port enable status change */
299 #define RH_PS_PSSC 0x00040000 /* port suspend status change */
300 #define RH_PS_OCIC 0x00080000 /* over current indicator change */
301 #define RH_PS_PRSC 0x00100000 /* port reset status change */
302
303 /* roothub.status bits */
304 #define RH_HS_LPS 0x00000001 /* local power status */
305 #define RH_HS_OCI 0x00000002 /* over current indicator */
306 #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
307 #define RH_HS_LPSC 0x00010000 /* local power status change */
308 #define RH_HS_OCIC 0x00020000 /* over current indicator change */
309 #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
310
311 /* roothub.b masks */
312 #define RH_B_DR 0x0000ffff /* device removable flags */
313 #define RH_B_PPCM 0xffff0000 /* port power control mask */
314
315 /* roothub.a masks */
316 #define RH_A_NDP (0xff << 0) /* number of downstream ports */
317 #define RH_A_PSM (1 << 8) /* power switching mode */
318 #define RH_A_NPS (1 << 9) /* no power switching */
319 #define RH_A_DT (1 << 10) /* device type (mbz) */
320 #define RH_A_OCPM (1 << 11) /* over current protection mode */
321 #define RH_A_NOCP (1 << 12) /* no over current protection */
322 #define RH_A_POTPGT (0xff << 24) /* power on to power good time */
323
324
325 /* hcd-private per-urb state */
326 typedef struct urb_priv {
327 struct ed *ed;
328 u16 length; // # tds in this request
329 u16 td_cnt; // tds already serviced
330 struct list_head pending;
331 struct td *td [0]; // all TDs in this request
332
333 } urb_priv_t;
334
335 #define TD_HASH_SIZE 64 /* power'o'two */
336 // sizeof (struct td) ~= 64 == 2^6 ...
337 #define TD_HASH_FUNC(td_dma) ((td_dma ^ (td_dma >> 6)) % TD_HASH_SIZE)
338
339
340 /*
341 * This is the full ohci controller description
342 *
343 * Note how the "proper" USB information is just
344 * a subset of what the full implementation needs. (Linus)
345 */
346
347 struct ohci_hcd {
348 spinlock_t lock;
349
350 /*
351 * I/O memory used to communicate with the HC (dma-consistent)
352 */
353 struct ohci_regs __iomem *regs;
354
355 /*
356 * main memory used to communicate with the HC (dma-consistent).
357 * hcd adds to schedule for a live hc any time, but removals finish
358 * only at the start of the next frame.
359 */
360 struct ohci_hcca *hcca;
361 dma_addr_t hcca_dma;
362
363 struct ed *ed_rm_list; /* to be removed */
364
365 struct ed *ed_bulktail; /* last in bulk list */
366 struct ed *ed_controltail; /* last in ctrl list */
367 struct ed *periodic [NUM_INTS]; /* shadow int_table */
368
369 /*
370 * OTG controllers and transceivers need software interaction;
371 * other external transceivers should be software-transparent
372 */
373 struct otg_transceiver *transceiver;
374 void (*start_hnp)(struct ohci_hcd *ohci);
375
376 /*
377 * memory management for queue data structures
378 */
379 struct dma_pool *td_cache;
380 struct dma_pool *ed_cache;
381 struct td *td_hash [TD_HASH_SIZE];
382 struct list_head pending;
383
384 /*
385 * driver state
386 */
387 int num_ports;
388 int load [NUM_INTS];
389 u32 hc_control; /* copy of hc control reg */
390 unsigned long next_statechange; /* suspend/resume */
391 u32 fminterval; /* saved register */
392 unsigned autostop:1; /* rh auto stopping/stopped */
393
394 unsigned long flags; /* for HC bugs */
395 #define OHCI_QUIRK_AMD756 0x01 /* erratum #4 */
396 #define OHCI_QUIRK_SUPERIO 0x02 /* natsemi */
397 #define OHCI_QUIRK_INITRESET 0x04 /* SiS, OPTi, ... */
398 #define OHCI_QUIRK_BE_DESC 0x08 /* BE descriptors */
399 #define OHCI_QUIRK_BE_MMIO 0x10 /* BE registers */
400 #define OHCI_QUIRK_ZFMICRO 0x20 /* Compaq ZFMicro chipset*/
401 #define OHCI_QUIRK_NEC 0x40 /* lost interrupts */
402 #define OHCI_QUIRK_FRAME_NO 0x80 /* no big endian frame_no shift */
403 #define OHCI_QUIRK_HUB_POWER 0x100 /* distrust firmware power/oc setup */
404 #define OHCI_QUIRK_AMD_PLL 0x200 /* AMD PLL quirk*/
405 #define OHCI_QUIRK_AMD_PREFETCH 0x400 /* pre-fetch for ISO transfer */
406 #define OHCI_QUIRK_SHUTDOWN 0x800 /* nVidia power bug */
407 // there are also chip quirks/bugs in init logic
408
409 struct work_struct nec_work; /* Worker for NEC quirk */
410
411 /* Needed for ZF Micro quirk */
412 struct timer_list unlink_watchdog;
413 unsigned eds_scheduled;
414 struct ed *ed_to_check;
415 unsigned zf_delay;
416
417 #ifdef DEBUG
418 struct dentry *debug_dir;
419 struct dentry *debug_async;
420 struct dentry *debug_periodic;
421 struct dentry *debug_registers;
422 #endif
423 };
424
425 #ifdef CONFIG_PCI
quirk_nec(struct ohci_hcd * ohci)426 static inline int quirk_nec(struct ohci_hcd *ohci)
427 {
428 return ohci->flags & OHCI_QUIRK_NEC;
429 }
quirk_zfmicro(struct ohci_hcd * ohci)430 static inline int quirk_zfmicro(struct ohci_hcd *ohci)
431 {
432 return ohci->flags & OHCI_QUIRK_ZFMICRO;
433 }
quirk_amdiso(struct ohci_hcd * ohci)434 static inline int quirk_amdiso(struct ohci_hcd *ohci)
435 {
436 return ohci->flags & OHCI_QUIRK_AMD_PLL;
437 }
quirk_amdprefetch(struct ohci_hcd * ohci)438 static inline int quirk_amdprefetch(struct ohci_hcd *ohci)
439 {
440 return ohci->flags & OHCI_QUIRK_AMD_PREFETCH;
441 }
442 #else
quirk_nec(struct ohci_hcd * ohci)443 static inline int quirk_nec(struct ohci_hcd *ohci)
444 {
445 return 0;
446 }
quirk_zfmicro(struct ohci_hcd * ohci)447 static inline int quirk_zfmicro(struct ohci_hcd *ohci)
448 {
449 return 0;
450 }
quirk_amdiso(struct ohci_hcd * ohci)451 static inline int quirk_amdiso(struct ohci_hcd *ohci)
452 {
453 return 0;
454 }
quirk_amdprefetch(struct ohci_hcd * ohci)455 static inline int quirk_amdprefetch(struct ohci_hcd *ohci)
456 {
457 return 0;
458 }
459 #endif
460
461 /* convert between an hcd pointer and the corresponding ohci_hcd */
hcd_to_ohci(struct usb_hcd * hcd)462 static inline struct ohci_hcd *hcd_to_ohci (struct usb_hcd *hcd)
463 {
464 return (struct ohci_hcd *) (hcd->hcd_priv);
465 }
ohci_to_hcd(const struct ohci_hcd * ohci)466 static inline struct usb_hcd *ohci_to_hcd (const struct ohci_hcd *ohci)
467 {
468 return container_of ((void *) ohci, struct usb_hcd, hcd_priv);
469 }
470
471 /*-------------------------------------------------------------------------*/
472
473 #ifndef DEBUG
474 #define STUB_DEBUG_FILES
475 #endif /* DEBUG */
476
477 #define ohci_dbg(ohci, fmt, args...) \
478 dev_dbg (ohci_to_hcd(ohci)->self.controller , fmt , ## args )
479 #define ohci_err(ohci, fmt, args...) \
480 dev_err (ohci_to_hcd(ohci)->self.controller , fmt , ## args )
481 #define ohci_info(ohci, fmt, args...) \
482 dev_info (ohci_to_hcd(ohci)->self.controller , fmt , ## args )
483 #define ohci_warn(ohci, fmt, args...) \
484 dev_warn (ohci_to_hcd(ohci)->self.controller , fmt , ## args )
485
486 #ifdef OHCI_VERBOSE_DEBUG
487 # define ohci_vdbg ohci_dbg
488 #else
489 # define ohci_vdbg(ohci, fmt, args...) do { } while (0)
490 #endif
491
492 /*-------------------------------------------------------------------------*/
493
494 /*
495 * While most USB host controllers implement their registers and
496 * in-memory communication descriptors in little-endian format,
497 * a minority (notably the IBM STB04XXX and the Motorola MPC5200
498 * processors) implement them in big endian format.
499 *
500 * In addition some more exotic implementations like the Toshiba
501 * Spider (aka SCC) cell southbridge are "mixed" endian, that is,
502 * they have a different endianness for registers vs. in-memory
503 * descriptors.
504 *
505 * This attempts to support either format at compile time without a
506 * runtime penalty, or both formats with the additional overhead
507 * of checking a flag bit.
508 *
509 * That leads to some tricky Kconfig rules howevber. There are
510 * different defaults based on some arch/ppc platforms, though
511 * the basic rules are:
512 *
513 * Controller type Kconfig options needed
514 * --------------- ----------------------
515 * little endian CONFIG_USB_OHCI_LITTLE_ENDIAN
516 *
517 * fully big endian CONFIG_USB_OHCI_BIG_ENDIAN_DESC _and_
518 * CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
519 *
520 * mixed endian CONFIG_USB_OHCI_LITTLE_ENDIAN _and_
521 * CONFIG_USB_OHCI_BIG_ENDIAN_{MMIO,DESC}
522 *
523 * (If you have a mixed endian controller, you -must- also define
524 * CONFIG_USB_OHCI_LITTLE_ENDIAN or things will not work when building
525 * both your mixed endian and a fully big endian controller support in
526 * the same kernel image).
527 */
528
529 #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_DESC
530 #ifdef CONFIG_USB_OHCI_LITTLE_ENDIAN
531 #define big_endian_desc(ohci) (ohci->flags & OHCI_QUIRK_BE_DESC)
532 #else
533 #define big_endian_desc(ohci) 1 /* only big endian */
534 #endif
535 #else
536 #define big_endian_desc(ohci) 0 /* only little endian */
537 #endif
538
539 #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
540 #ifdef CONFIG_USB_OHCI_LITTLE_ENDIAN
541 #define big_endian_mmio(ohci) (ohci->flags & OHCI_QUIRK_BE_MMIO)
542 #else
543 #define big_endian_mmio(ohci) 1 /* only big endian */
544 #endif
545 #else
546 #define big_endian_mmio(ohci) 0 /* only little endian */
547 #endif
548
549 /*
550 * Big-endian read/write functions are arch-specific.
551 * Other arches can be added if/when they're needed.
552 *
553 */
_ohci_readl(const struct ohci_hcd * ohci,__hc32 __iomem * regs)554 static inline unsigned int _ohci_readl (const struct ohci_hcd *ohci,
555 __hc32 __iomem * regs)
556 {
557 #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
558 return big_endian_mmio(ohci) ?
559 readl_be (regs) :
560 readl (regs);
561 #else
562 return readl (regs);
563 #endif
564 }
565
_ohci_writel(const struct ohci_hcd * ohci,const unsigned int val,__hc32 __iomem * regs)566 static inline void _ohci_writel (const struct ohci_hcd *ohci,
567 const unsigned int val, __hc32 __iomem *regs)
568 {
569 #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
570 big_endian_mmio(ohci) ?
571 writel_be (val, regs) :
572 writel (val, regs);
573 #else
574 writel (val, regs);
575 #endif
576 }
577
578 #define ohci_readl(o,r) _ohci_readl(o,r)
579 #define ohci_writel(o,v,r) _ohci_writel(o,v,r)
580
581
582 /*-------------------------------------------------------------------------*/
583
584 /* cpu to ohci */
cpu_to_hc16(const struct ohci_hcd * ohci,const u16 x)585 static inline __hc16 cpu_to_hc16 (const struct ohci_hcd *ohci, const u16 x)
586 {
587 return big_endian_desc(ohci) ?
588 (__force __hc16)cpu_to_be16(x) :
589 (__force __hc16)cpu_to_le16(x);
590 }
591
cpu_to_hc16p(const struct ohci_hcd * ohci,const u16 * x)592 static inline __hc16 cpu_to_hc16p (const struct ohci_hcd *ohci, const u16 *x)
593 {
594 return big_endian_desc(ohci) ?
595 cpu_to_be16p(x) :
596 cpu_to_le16p(x);
597 }
598
cpu_to_hc32(const struct ohci_hcd * ohci,const u32 x)599 static inline __hc32 cpu_to_hc32 (const struct ohci_hcd *ohci, const u32 x)
600 {
601 return big_endian_desc(ohci) ?
602 (__force __hc32)cpu_to_be32(x) :
603 (__force __hc32)cpu_to_le32(x);
604 }
605
cpu_to_hc32p(const struct ohci_hcd * ohci,const u32 * x)606 static inline __hc32 cpu_to_hc32p (const struct ohci_hcd *ohci, const u32 *x)
607 {
608 return big_endian_desc(ohci) ?
609 cpu_to_be32p(x) :
610 cpu_to_le32p(x);
611 }
612
613 /* ohci to cpu */
hc16_to_cpu(const struct ohci_hcd * ohci,const __hc16 x)614 static inline u16 hc16_to_cpu (const struct ohci_hcd *ohci, const __hc16 x)
615 {
616 return big_endian_desc(ohci) ?
617 be16_to_cpu((__force __be16)x) :
618 le16_to_cpu((__force __le16)x);
619 }
620
hc16_to_cpup(const struct ohci_hcd * ohci,const __hc16 * x)621 static inline u16 hc16_to_cpup (const struct ohci_hcd *ohci, const __hc16 *x)
622 {
623 return big_endian_desc(ohci) ?
624 be16_to_cpup((__force __be16 *)x) :
625 le16_to_cpup((__force __le16 *)x);
626 }
627
hc32_to_cpu(const struct ohci_hcd * ohci,const __hc32 x)628 static inline u32 hc32_to_cpu (const struct ohci_hcd *ohci, const __hc32 x)
629 {
630 return big_endian_desc(ohci) ?
631 be32_to_cpu((__force __be32)x) :
632 le32_to_cpu((__force __le32)x);
633 }
634
hc32_to_cpup(const struct ohci_hcd * ohci,const __hc32 * x)635 static inline u32 hc32_to_cpup (const struct ohci_hcd *ohci, const __hc32 *x)
636 {
637 return big_endian_desc(ohci) ?
638 be32_to_cpup((__force __be32 *)x) :
639 le32_to_cpup((__force __le32 *)x);
640 }
641
642 /*-------------------------------------------------------------------------*/
643
644 /* HCCA frame number is 16 bits, but is accessed as 32 bits since not all
645 * hardware handles 16 bit reads. That creates a different confusion on
646 * some big-endian SOC implementations. Same thing happens with PSW access.
647 */
648
649 #ifdef CONFIG_PPC_MPC52xx
650 #define big_endian_frame_no_quirk(ohci) (ohci->flags & OHCI_QUIRK_FRAME_NO)
651 #else
652 #define big_endian_frame_no_quirk(ohci) 0
653 #endif
654
ohci_frame_no(const struct ohci_hcd * ohci)655 static inline u16 ohci_frame_no(const struct ohci_hcd *ohci)
656 {
657 u32 tmp;
658 if (big_endian_desc(ohci)) {
659 tmp = be32_to_cpup((__force __be32 *)&ohci->hcca->frame_no);
660 if (!big_endian_frame_no_quirk(ohci))
661 tmp >>= 16;
662 } else
663 tmp = le32_to_cpup((__force __le32 *)&ohci->hcca->frame_no);
664
665 return (u16)tmp;
666 }
667
ohci_hwPSWp(const struct ohci_hcd * ohci,const struct td * td,int index)668 static inline __hc16 *ohci_hwPSWp(const struct ohci_hcd *ohci,
669 const struct td *td, int index)
670 {
671 return (__hc16 *)(big_endian_desc(ohci) ?
672 &td->hwPSW[index ^ 1] : &td->hwPSW[index]);
673 }
674
ohci_hwPSW(const struct ohci_hcd * ohci,const struct td * td,int index)675 static inline u16 ohci_hwPSW(const struct ohci_hcd *ohci,
676 const struct td *td, int index)
677 {
678 return hc16_to_cpup(ohci, ohci_hwPSWp(ohci, td, index));
679 }
680
681 /*-------------------------------------------------------------------------*/
682
disable(struct ohci_hcd * ohci)683 static inline void disable (struct ohci_hcd *ohci)
684 {
685 ohci_to_hcd(ohci)->state = HC_STATE_HALT;
686 }
687
688 #define FI 0x2edf /* 12000 bits per frame (-1) */
689 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
690 #define FIT (1 << 31)
691 #define LSTHRESH 0x628 /* lowspeed bit threshold */
692
periodic_reinit(struct ohci_hcd * ohci)693 static inline void periodic_reinit (struct ohci_hcd *ohci)
694 {
695 u32 fi = ohci->fminterval & 0x03fff;
696 u32 fit = ohci_readl(ohci, &ohci->regs->fminterval) & FIT;
697
698 ohci_writel (ohci, (fit ^ FIT) | ohci->fminterval,
699 &ohci->regs->fminterval);
700 ohci_writel (ohci, ((9 * fi) / 10) & 0x3fff,
701 &ohci->regs->periodicstart);
702 }
703
704 /* AMD-756 (D2 rev) reports corrupt register contents in some cases.
705 * The erratum (#4) description is incorrect. AMD's workaround waits
706 * till some bits (mostly reserved) are clear; ok for all revs.
707 */
708 #define read_roothub(hc, register, mask) ({ \
709 u32 temp = ohci_readl (hc, &hc->regs->roothub.register); \
710 if (temp == -1) \
711 disable (hc); \
712 else if (hc->flags & OHCI_QUIRK_AMD756) \
713 while (temp & mask) \
714 temp = ohci_readl (hc, &hc->regs->roothub.register); \
715 temp; })
716
roothub_a(struct ohci_hcd * hc)717 static inline u32 roothub_a (struct ohci_hcd *hc)
718 { return read_roothub (hc, a, 0xfc0fe000); }
roothub_b(struct ohci_hcd * hc)719 static inline u32 roothub_b (struct ohci_hcd *hc)
720 { return ohci_readl (hc, &hc->regs->roothub.b); }
roothub_status(struct ohci_hcd * hc)721 static inline u32 roothub_status (struct ohci_hcd *hc)
722 { return ohci_readl (hc, &hc->regs->roothub.status); }
roothub_portstatus(struct ohci_hcd * hc,int i)723 static inline u32 roothub_portstatus (struct ohci_hcd *hc, int i)
724 { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
725