1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #ifndef __DML2_DISPLAY_MODE_VBA_H__ 28 #define __DML2_DISPLAY_MODE_VBA_H__ 29 30 struct display_mode_lib; 31 32 void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib); 33 34 #define dml_get_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes) 35 36 dml_get_attr_decl(clk_dcf_deepsleep); 37 dml_get_attr_decl(wm_urgent); 38 dml_get_attr_decl(wm_memory_trip); 39 dml_get_attr_decl(wm_writeback_urgent); 40 dml_get_attr_decl(wm_stutter_exit); 41 dml_get_attr_decl(wm_stutter_enter_exit); 42 dml_get_attr_decl(wm_z8_stutter_exit); 43 dml_get_attr_decl(wm_z8_stutter_enter_exit); 44 dml_get_attr_decl(stutter_efficiency_z8); 45 dml_get_attr_decl(stutter_num_bursts_z8); 46 dml_get_attr_decl(wm_dram_clock_change); 47 dml_get_attr_decl(wm_writeback_dram_clock_change); 48 dml_get_attr_decl(stutter_efficiency_no_vblank); 49 dml_get_attr_decl(stutter_efficiency); 50 dml_get_attr_decl(stutter_period); 51 dml_get_attr_decl(urgent_latency); 52 dml_get_attr_decl(urgent_extra_latency); 53 dml_get_attr_decl(nonurgent_latency); 54 dml_get_attr_decl(dram_clock_change_latency); 55 dml_get_attr_decl(dispclk_calculated); 56 dml_get_attr_decl(total_data_read_bw); 57 dml_get_attr_decl(return_bw); 58 dml_get_attr_decl(tcalc); 59 dml_get_attr_decl(fraction_of_urgent_bandwidth); 60 dml_get_attr_decl(fraction_of_urgent_bandwidth_imm_flip); 61 62 #define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe) 63 64 dml_get_pipe_attr_decl(dsc_delay); 65 dml_get_pipe_attr_decl(dppclk_calculated); 66 dml_get_pipe_attr_decl(dscclk_calculated); 67 dml_get_pipe_attr_decl(min_ttu_vblank); 68 dml_get_pipe_attr_decl(min_ttu_vblank_in_us); 69 dml_get_pipe_attr_decl(vratio_prefetch_l); 70 dml_get_pipe_attr_decl(vratio_prefetch_c); 71 dml_get_pipe_attr_decl(dst_x_after_scaler); 72 dml_get_pipe_attr_decl(dst_y_after_scaler); 73 dml_get_pipe_attr_decl(dst_y_per_vm_vblank); 74 dml_get_pipe_attr_decl(dst_y_per_row_vblank); 75 dml_get_pipe_attr_decl(dst_y_prefetch); 76 dml_get_pipe_attr_decl(dst_y_per_vm_flip); 77 dml_get_pipe_attr_decl(dst_y_per_row_flip); 78 dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank); 79 dml_get_pipe_attr_decl(refcyc_per_vm_group_flip); 80 dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank); 81 dml_get_pipe_attr_decl(refcyc_per_vm_req_flip); 82 dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank_in_us); 83 dml_get_pipe_attr_decl(refcyc_per_vm_group_flip_in_us); 84 dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank_in_us); 85 dml_get_pipe_attr_decl(refcyc_per_vm_req_flip_in_us); 86 dml_get_pipe_attr_decl(refcyc_per_vm_dmdata_in_us); 87 dml_get_pipe_attr_decl(dmdata_dl_delta_in_us); 88 dml_get_pipe_attr_decl(refcyc_per_line_delivery_l_in_us); 89 dml_get_pipe_attr_decl(refcyc_per_line_delivery_c_in_us); 90 dml_get_pipe_attr_decl(refcyc_per_line_delivery_pre_l_in_us); 91 dml_get_pipe_attr_decl(refcyc_per_line_delivery_pre_c_in_us); 92 dml_get_pipe_attr_decl(refcyc_per_req_delivery_l_in_us); 93 dml_get_pipe_attr_decl(refcyc_per_req_delivery_c_in_us); 94 dml_get_pipe_attr_decl(refcyc_per_req_delivery_pre_l_in_us); 95 dml_get_pipe_attr_decl(refcyc_per_req_delivery_pre_c_in_us); 96 dml_get_pipe_attr_decl(refcyc_per_cursor_req_delivery_in_us); 97 dml_get_pipe_attr_decl(refcyc_per_cursor_req_delivery_pre_in_us); 98 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_nom_l_in_us); 99 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_nom_c_in_us); 100 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_vblank_l_in_us); 101 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_vblank_c_in_us); 102 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_flip_l_in_us); 103 dml_get_pipe_attr_decl(refcyc_per_meta_chunk_flip_c_in_us); 104 105 dml_get_pipe_attr_decl(vstartup); 106 dml_get_pipe_attr_decl(vupdate_offset); 107 dml_get_pipe_attr_decl(vupdate_width); 108 dml_get_pipe_attr_decl(vready_offset); 109 dml_get_pipe_attr_decl(vready_at_or_after_vsync); 110 dml_get_pipe_attr_decl(min_dst_y_next_start); 111 112 double get_total_immediate_flip_bytes( 113 struct display_mode_lib *mode_lib, 114 const display_e2e_pipe_params_st *pipes, 115 unsigned int num_pipes); 116 double get_total_immediate_flip_bw( 117 struct display_mode_lib *mode_lib, 118 const display_e2e_pipe_params_st *pipes, 119 unsigned int num_pipes); 120 double get_total_prefetch_bw( 121 struct display_mode_lib *mode_lib, 122 const display_e2e_pipe_params_st *pipes, 123 unsigned int num_pipes); 124 unsigned int dml_get_voltage_level( 125 struct display_mode_lib *mode_lib, 126 const display_e2e_pipe_params_st *pipes, 127 unsigned int num_pipes); 128 129 void PixelClockAdjustmentForProgressiveToInterlaceUnit(struct display_mode_lib *mode_lib); 130 131 bool Calculate256BBlockSizes( 132 enum source_format_class SourcePixelFormat, 133 enum dm_swizzle_mode SurfaceTiling, 134 unsigned int BytePerPixelY, 135 unsigned int BytePerPixelC, 136 unsigned int *BlockHeight256BytesY, 137 unsigned int *BlockHeight256BytesC, 138 unsigned int *BlockWidth256BytesY, 139 unsigned int *BlockWidth256BytesC); 140 141 struct vba_vars_st { 142 ip_params_st ip; 143 soc_bounding_box_st soc; 144 145 int maxMpcComb; 146 bool UseMaximumVStartup; 147 148 double WritebackDISPCLK; 149 double DPPCLKUsingSingleDPPLuma; 150 double DPPCLKUsingSingleDPPChroma; 151 double DISPCLKWithRamping; 152 double DISPCLKWithoutRamping; 153 double GlobalDPPCLK; 154 double DISPCLKWithRampingRoundedToDFSGranularity; 155 double DISPCLKWithoutRampingRoundedToDFSGranularity; 156 double MaxDispclkRoundedToDFSGranularity; 157 bool DCCEnabledAnyPlane; 158 double ReturnBandwidthToDCN; 159 unsigned int TotalActiveDPP; 160 unsigned int TotalDCCActiveDPP; 161 double UrgentRoundTripAndOutOfOrderLatency; 162 double StutterPeriod; 163 double FrameTimeForMinFullDETBufferingTime; 164 double AverageReadBandwidth; 165 double TotalRowReadBandwidth; 166 double PartOfBurstThatFitsInROB; 167 double StutterBurstTime; 168 unsigned int NextPrefetchMode; 169 double NextMaxVStartup; 170 double VBlankTime; 171 double SmallestVBlank; 172 double DCFCLKDeepSleepPerPlane[DC__NUM_DPP__MAX]; 173 double EffectiveDETPlusLBLinesLuma; 174 double EffectiveDETPlusLBLinesChroma; 175 double UrgentLatencySupportUsLuma; 176 double UrgentLatencySupportUsChroma; 177 unsigned int DSCFormatFactor; 178 179 bool DummyPStateCheck; 180 bool DRAMClockChangeSupportsVActive; 181 bool PrefetchModeSupported; 182 bool PrefetchAndImmediateFlipSupported; 183 enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank; // Mode Support only 184 double XFCRemoteSurfaceFlipDelay; 185 double TInitXFill; 186 double TslvChk; 187 double SrcActiveDrainRate; 188 bool ImmediateFlipSupported; 189 enum mpc_combine_affinity WhenToDoMPCCombine; // Mode Support only 190 191 bool PrefetchERROR; 192 193 unsigned int VStartupLines; 194 unsigned int ActiveDPPs; 195 unsigned int LBLatencyHidingSourceLinesY; 196 unsigned int LBLatencyHidingSourceLinesC; 197 double ActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX]; 198 double CachedActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX]; // Cache in dml_get_voltage_level for debug purposes only 199 double MinActiveDRAMClockChangeMargin; 200 double InitFillLevel; 201 double FinalFillMargin; 202 double FinalFillLevel; 203 double RemainingFillLevel; 204 double TFinalxFill; 205 206 // 207 // SOC Bounding Box Parameters 208 // 209 double SRExitTime; 210 double SREnterPlusExitTime; 211 double UrgentLatencyPixelDataOnly; 212 double UrgentLatencyPixelMixedWithVMData; 213 double UrgentLatencyVMDataOnly; 214 double UrgentLatency; // max of the above three 215 double WritebackLatency; 216 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly; // Mode Support 217 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData; // Mode Support 218 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly; // Mode Support 219 double MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation; // Mode Support 220 double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation; // Mode Support 221 double NumberOfChannels; 222 double DRAMChannelWidth; 223 double FabricDatapathToDCNDataReturn; 224 double ReturnBusWidth; 225 double Downspreading; 226 double DISPCLKDPPCLKDSCCLKDownSpreading; 227 double DISPCLKDPPCLKVCOSpeed; 228 double RoundTripPingLatencyCycles; 229 double UrgentOutOfOrderReturnPerChannel; 230 double UrgentOutOfOrderReturnPerChannelPixelDataOnly; 231 double UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData; 232 double UrgentOutOfOrderReturnPerChannelVMDataOnly; 233 unsigned int VMMPageSize; 234 double DRAMClockChangeLatency; 235 double XFCBusTransportTime; 236 bool UseUrgentBurstBandwidth; 237 double XFCXBUFLatencyTolerance; 238 239 // 240 // IP Parameters 241 // 242 unsigned int ROBBufferSizeInKByte; 243 unsigned int DETBufferSizeInKByte[DC__NUM_DPP__MAX]; 244 double DETBufferSizeInTime; 245 unsigned int DPPOutputBufferPixels; 246 unsigned int OPPOutputBufferLines; 247 unsigned int PixelChunkSizeInKByte; 248 double ReturnBW; 249 bool GPUVMEnable; 250 bool HostVMEnable; 251 unsigned int GPUVMMaxPageTableLevels; 252 unsigned int HostVMMaxPageTableLevels; 253 unsigned int HostVMCachedPageTableLevels; 254 unsigned int OverrideGPUVMPageTableLevels; 255 unsigned int OverrideHostVMPageTableLevels; 256 unsigned int MetaChunkSize; 257 unsigned int MinMetaChunkSizeBytes; 258 unsigned int WritebackChunkSize; 259 bool ODMCapability; 260 unsigned int NumberOfDSC; 261 unsigned int LineBufferSize; 262 unsigned int MaxLineBufferLines; 263 unsigned int WritebackInterfaceLumaBufferSize; 264 unsigned int WritebackInterfaceChromaBufferSize; 265 unsigned int WritebackChromaLineBufferWidth; 266 enum writeback_config WritebackConfiguration; 267 double MaxDCHUBToPSCLThroughput; 268 double MaxPSCLToLBThroughput; 269 unsigned int PTEBufferSizeInRequestsLuma; 270 unsigned int PTEBufferSizeInRequestsChroma; 271 double DISPCLKRampingMargin; 272 unsigned int MaxInterDCNTileRepeaters; 273 bool XFCSupported; 274 double XFCSlvChunkSize; 275 double XFCFillBWOverhead; 276 double XFCFillConstant; 277 double XFCTSlvVupdateOffset; 278 double XFCTSlvVupdateWidth; 279 double XFCTSlvVreadyOffset; 280 double DPPCLKDelaySubtotal; 281 double DPPCLKDelaySCL; 282 double DPPCLKDelaySCLLBOnly; 283 double DPPCLKDelayCNVCFormater; 284 double DPPCLKDelayCNVCCursor; 285 double DISPCLKDelaySubtotal; 286 bool ProgressiveToInterlaceUnitInOPP; 287 // Pipe/Plane Parameters 288 int VoltageLevel; 289 double FabricClock; 290 double DRAMSpeed; 291 double DISPCLK; 292 double SOCCLK; 293 double DCFCLK; 294 295 unsigned int NumberOfActivePlanes; 296 unsigned int NumberOfDSCSlices[DC__NUM_DPP__MAX]; 297 unsigned int ViewportWidth[DC__NUM_DPP__MAX]; 298 unsigned int ViewportHeight[DC__NUM_DPP__MAX]; 299 unsigned int ViewportYStartY[DC__NUM_DPP__MAX]; 300 unsigned int ViewportYStartC[DC__NUM_DPP__MAX]; 301 unsigned int PitchY[DC__NUM_DPP__MAX]; 302 unsigned int PitchC[DC__NUM_DPP__MAX]; 303 double HRatio[DC__NUM_DPP__MAX]; 304 double VRatio[DC__NUM_DPP__MAX]; 305 unsigned int htaps[DC__NUM_DPP__MAX]; 306 unsigned int vtaps[DC__NUM_DPP__MAX]; 307 unsigned int HTAPsChroma[DC__NUM_DPP__MAX]; 308 unsigned int VTAPsChroma[DC__NUM_DPP__MAX]; 309 unsigned int HTotal[DC__NUM_DPP__MAX]; 310 unsigned int VTotal[DC__NUM_DPP__MAX]; 311 unsigned int VTotal_Max[DC__NUM_DPP__MAX]; 312 unsigned int VTotal_Min[DC__NUM_DPP__MAX]; 313 int DPPPerPlane[DC__NUM_DPP__MAX]; 314 double PixelClock[DC__NUM_DPP__MAX]; 315 double PixelClockBackEnd[DC__NUM_DPP__MAX]; 316 bool DCCEnable[DC__NUM_DPP__MAX]; 317 bool FECEnable[DC__NUM_DPP__MAX]; 318 unsigned int DCCMetaPitchY[DC__NUM_DPP__MAX]; 319 unsigned int DCCMetaPitchC[DC__NUM_DPP__MAX]; 320 enum scan_direction_class SourceScan[DC__NUM_DPP__MAX]; 321 enum source_format_class SourcePixelFormat[DC__NUM_DPP__MAX]; 322 bool WritebackEnable[DC__NUM_DPP__MAX]; 323 unsigned int ActiveWritebacksPerPlane[DC__NUM_DPP__MAX]; 324 double WritebackDestinationWidth[DC__NUM_DPP__MAX]; 325 double WritebackDestinationHeight[DC__NUM_DPP__MAX]; 326 double WritebackSourceHeight[DC__NUM_DPP__MAX]; 327 enum source_format_class WritebackPixelFormat[DC__NUM_DPP__MAX]; 328 unsigned int WritebackLumaHTaps[DC__NUM_DPP__MAX]; 329 unsigned int WritebackLumaVTaps[DC__NUM_DPP__MAX]; 330 unsigned int WritebackChromaHTaps[DC__NUM_DPP__MAX]; 331 unsigned int WritebackChromaVTaps[DC__NUM_DPP__MAX]; 332 double WritebackHRatio[DC__NUM_DPP__MAX]; 333 double WritebackVRatio[DC__NUM_DPP__MAX]; 334 unsigned int HActive[DC__NUM_DPP__MAX]; 335 unsigned int VActive[DC__NUM_DPP__MAX]; 336 bool Interlace[DC__NUM_DPP__MAX]; 337 enum dm_swizzle_mode SurfaceTiling[DC__NUM_DPP__MAX]; 338 unsigned int ScalerRecoutWidth[DC__NUM_DPP__MAX]; 339 bool DynamicMetadataEnable[DC__NUM_DPP__MAX]; 340 int DynamicMetadataLinesBeforeActiveRequired[DC__NUM_DPP__MAX]; 341 unsigned int DynamicMetadataTransmittedBytes[DC__NUM_DPP__MAX]; 342 double DCCRate[DC__NUM_DPP__MAX]; 343 double AverageDCCCompressionRate; 344 enum odm_combine_mode ODMCombineEnabled[DC__NUM_DPP__MAX]; 345 double OutputBpp[DC__NUM_DPP__MAX]; 346 bool DSCEnabled[DC__NUM_DPP__MAX]; 347 unsigned int DSCInputBitPerComponent[DC__NUM_DPP__MAX]; 348 enum output_format_class OutputFormat[DC__NUM_DPP__MAX]; 349 enum output_encoder_class Output[DC__NUM_DPP__MAX]; 350 bool skip_dio_check[DC__NUM_DPP__MAX]; 351 unsigned int BlendingAndTiming[DC__NUM_DPP__MAX]; 352 bool SynchronizedVBlank; 353 unsigned int NumberOfCursors[DC__NUM_DPP__MAX]; 354 unsigned int CursorWidth[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX]; 355 unsigned int CursorBPP[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX]; 356 bool XFCEnabled[DC__NUM_DPP__MAX]; 357 bool ScalerEnabled[DC__NUM_DPP__MAX]; 358 359 // Intermediates/Informational 360 bool ImmediateFlipSupport; 361 unsigned int DETBufferSizeY[DC__NUM_DPP__MAX]; 362 unsigned int DETBufferSizeC[DC__NUM_DPP__MAX]; 363 unsigned int SwathHeightY[DC__NUM_DPP__MAX]; 364 unsigned int SwathHeightC[DC__NUM_DPP__MAX]; 365 unsigned int LBBitPerPixel[DC__NUM_DPP__MAX]; 366 double LastPixelOfLineExtraWatermark; 367 double TotalDataReadBandwidth; 368 unsigned int TotalActiveWriteback; 369 unsigned int EffectiveLBLatencyHidingSourceLinesLuma; 370 unsigned int EffectiveLBLatencyHidingSourceLinesChroma; 371 double BandwidthAvailableForImmediateFlip; 372 unsigned int PrefetchMode[DC__VOLTAGE_STATES][2]; 373 unsigned int PrefetchModePerState[DC__VOLTAGE_STATES][2]; 374 unsigned int MinPrefetchMode; 375 unsigned int MaxPrefetchMode; 376 bool AnyLinesForVMOrRowTooLarge; 377 double MaxVStartup; 378 bool IgnoreViewportPositioning; 379 bool ErrorResult[DC__NUM_DPP__MAX]; 380 // 381 // Calculated dml_ml->vba.Outputs 382 // 383 double DCFCLKDeepSleep; 384 double UrgentWatermark; 385 double UrgentExtraLatency; 386 double WritebackUrgentWatermark; 387 double StutterExitWatermark; 388 double StutterEnterPlusExitWatermark; 389 double DRAMClockChangeWatermark; 390 double WritebackDRAMClockChangeWatermark; 391 double StutterEfficiency; 392 double StutterEfficiencyNotIncludingVBlank; 393 double NonUrgentLatencyTolerance; 394 double MinActiveDRAMClockChangeLatencySupported; 395 396 // These are the clocks calcuated by the library but they are not actually 397 // used explicitly. They are fetched by tests and then possibly used. The 398 // ultimate values to use are the ones specified by the parameters to DML 399 double DISPCLK_calculated; 400 double DPPCLK_calculated[DC__NUM_DPP__MAX]; 401 402 unsigned int VUpdateOffsetPix[DC__NUM_DPP__MAX]; 403 double VUpdateWidthPix[DC__NUM_DPP__MAX]; 404 double VReadyOffsetPix[DC__NUM_DPP__MAX]; 405 406 unsigned int TotImmediateFlipBytes; 407 double TCalc; 408 409 display_e2e_pipe_params_st cache_pipes[DC__NUM_DPP__MAX]; 410 unsigned int cache_num_pipes; 411 unsigned int pipe_plane[DC__NUM_DPP__MAX]; 412 413 /* vba mode support */ 414 /*inputs*/ 415 bool SupportGFX7CompatibleTilingIn32bppAnd64bpp; 416 double MaxHSCLRatio; 417 double MaxVSCLRatio; 418 unsigned int MaxNumWriteback; 419 bool WritebackLumaAndChromaScalingSupported; 420 bool Cursor64BppSupport; 421 double DCFCLKPerState[DC__VOLTAGE_STATES]; 422 double DCFCLKState[DC__VOLTAGE_STATES][2]; 423 double FabricClockPerState[DC__VOLTAGE_STATES]; 424 double SOCCLKPerState[DC__VOLTAGE_STATES]; 425 double PHYCLKPerState[DC__VOLTAGE_STATES]; 426 double DTBCLKPerState[DC__VOLTAGE_STATES]; 427 double MaxDppclk[DC__VOLTAGE_STATES]; 428 double MaxDSCCLK[DC__VOLTAGE_STATES]; 429 double DRAMSpeedPerState[DC__VOLTAGE_STATES]; 430 double MaxDispclk[DC__VOLTAGE_STATES]; 431 int VoltageOverrideLevel; 432 433 /*outputs*/ 434 bool ScaleRatioAndTapsSupport; 435 bool SourceFormatPixelAndScanSupport; 436 double TotalBandwidthConsumedGBytePerSecond; 437 bool DCCEnabledInAnyPlane; 438 bool WritebackLatencySupport; 439 bool WritebackModeSupport; 440 bool Writeback10bpc420Supported; 441 bool BandwidthSupport[DC__VOLTAGE_STATES]; 442 unsigned int TotalNumberOfActiveWriteback; 443 double CriticalPoint; 444 double ReturnBWToDCNPerState; 445 bool IsErrorResult[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 446 bool prefetch_vm_bw_valid; 447 bool prefetch_row_bw_valid; 448 bool NumberOfOTGSupport; 449 bool NonsupportedDSCInputBPC; 450 bool WritebackScaleRatioAndTapsSupport; 451 bool CursorSupport; 452 bool PitchSupport; 453 enum dm_validation_status ValidationStatus[DC__VOLTAGE_STATES]; 454 455 double WritebackLineBufferLumaBufferSize; 456 double WritebackLineBufferChromaBufferSize; 457 double WritebackMinHSCLRatio; 458 double WritebackMinVSCLRatio; 459 double WritebackMaxHSCLRatio; 460 double WritebackMaxVSCLRatio; 461 double WritebackMaxHSCLTaps; 462 double WritebackMaxVSCLTaps; 463 unsigned int MaxNumDPP; 464 unsigned int MaxNumOTG; 465 double CursorBufferSize; 466 double CursorChunkSize; 467 unsigned int Mode; 468 double OutputLinkDPLanes[DC__NUM_DPP__MAX]; 469 double ForcedOutputLinkBPP[DC__NUM_DPP__MAX]; // Mode Support only 470 double ImmediateFlipBW[DC__NUM_DPP__MAX]; 471 double MaxMaxVStartup[DC__VOLTAGE_STATES][2]; 472 473 double WritebackLumaVExtra; 474 double WritebackChromaVExtra; 475 double WritebackRequiredDISPCLK; 476 double MaximumSwathWidthSupport; 477 double MaximumSwathWidthInDETBuffer; 478 double MaximumSwathWidthInLineBuffer; 479 double MaxDispclkRoundedDownToDFSGranularity; 480 double MaxDppclkRoundedDownToDFSGranularity; 481 double PlaneRequiredDISPCLKWithoutODMCombine; 482 double PlaneRequiredDISPCLKWithODMCombine; 483 double PlaneRequiredDISPCLK; 484 double TotalNumberOfActiveOTG; 485 double FECOverhead; 486 double EffectiveFECOverhead; 487 double Outbpp; 488 unsigned int OutbppDSC; 489 double TotalDSCUnitsRequired; 490 double bpp; 491 unsigned int slices; 492 double SwathWidthGranularityY; 493 double RoundedUpMaxSwathSizeBytesY; 494 double SwathWidthGranularityC; 495 double RoundedUpMaxSwathSizeBytesC; 496 double EffectiveDETLBLinesLuma; 497 double EffectiveDETLBLinesChroma; 498 double ProjectedDCFCLKDeepSleep[DC__VOLTAGE_STATES][2]; 499 double PDEAndMetaPTEBytesPerFrameY; 500 double PDEAndMetaPTEBytesPerFrameC; 501 unsigned int MetaRowBytesY; 502 unsigned int MetaRowBytesC; 503 unsigned int DPTEBytesPerRowC; 504 unsigned int DPTEBytesPerRowY; 505 double ExtraLatency; 506 double TimeCalc; 507 double TWait; 508 double MaximumReadBandwidthWithPrefetch; 509 double MaximumReadBandwidthWithoutPrefetch; 510 double total_dcn_read_bw_with_flip; 511 double total_dcn_read_bw_with_flip_no_urgent_burst; 512 double FractionOfUrgentBandwidth; 513 double FractionOfUrgentBandwidthImmediateFlip; // Mode Support debugging output 514 515 /* ms locals */ 516 double IdealSDPPortBandwidthPerState[DC__VOLTAGE_STATES][2]; 517 unsigned int NoOfDPP[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 518 int NoOfDPPThisState[DC__NUM_DPP__MAX]; 519 enum odm_combine_mode ODMCombineEnablePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 520 double SwathWidthYThisState[DC__NUM_DPP__MAX]; 521 unsigned int SwathHeightCPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 522 unsigned int SwathHeightYThisState[DC__NUM_DPP__MAX]; 523 unsigned int SwathHeightCThisState[DC__NUM_DPP__MAX]; 524 double VRatioPreY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 525 double VRatioPreC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 526 double RequiredPrefetchPixelDataBWLuma[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 527 double RequiredPrefetchPixelDataBWChroma[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 528 double RequiredDPPCLK[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 529 double RequiredDPPCLKThisState[DC__NUM_DPP__MAX]; 530 bool PTEBufferSizeNotExceededY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 531 bool PTEBufferSizeNotExceededC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 532 bool BandwidthWithoutPrefetchSupported[DC__VOLTAGE_STATES][2]; 533 bool PrefetchSupported[DC__VOLTAGE_STATES][2]; 534 bool VRatioInPrefetchSupported[DC__VOLTAGE_STATES][2]; 535 double RequiredDISPCLK[DC__VOLTAGE_STATES][2]; 536 bool DISPCLK_DPPCLK_Support[DC__VOLTAGE_STATES][2]; 537 bool TotalAvailablePipesSupport[DC__VOLTAGE_STATES][2]; 538 unsigned int TotalNumberOfActiveDPP[DC__VOLTAGE_STATES][2]; 539 unsigned int TotalNumberOfDCCActiveDPP[DC__VOLTAGE_STATES][2]; 540 bool ModeSupport[DC__VOLTAGE_STATES][2]; 541 double ReturnBWPerState[DC__VOLTAGE_STATES][2]; 542 bool DIOSupport[DC__VOLTAGE_STATES]; 543 bool NotEnoughDSCUnits[DC__VOLTAGE_STATES]; 544 bool DSCCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES]; 545 bool DTBCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES]; 546 double UrgentRoundTripAndOutOfOrderLatencyPerState[DC__VOLTAGE_STATES]; 547 bool ROBSupport[DC__VOLTAGE_STATES][2]; 548 //based on rev 99: Dim DCCMetaBufferSizeSupport(NumberOfStates, 1) As Boolean 549 bool DCCMetaBufferSizeSupport[DC__VOLTAGE_STATES][2]; 550 bool PTEBufferSizeNotExceeded[DC__VOLTAGE_STATES][2]; 551 bool TotalVerticalActiveBandwidthSupport[DC__VOLTAGE_STATES][2]; 552 double MaxTotalVerticalActiveAvailableBandwidth[DC__VOLTAGE_STATES][2]; 553 double PrefetchBW[DC__NUM_DPP__MAX]; 554 double PDEAndMetaPTEBytesPerFrame[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 555 double MetaRowBytes[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 556 double DPTEBytesPerRow[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 557 double PrefetchLinesY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 558 double PrefetchLinesC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 559 unsigned int MaxNumSwY[DC__NUM_DPP__MAX]; 560 unsigned int MaxNumSwC[DC__NUM_DPP__MAX]; 561 double PrefillY[DC__NUM_DPP__MAX]; 562 double PrefillC[DC__NUM_DPP__MAX]; 563 double LineTimesForPrefetch[DC__NUM_DPP__MAX]; 564 double LinesForMetaPTE[DC__NUM_DPP__MAX]; 565 double LinesForMetaAndDPTERow[DC__NUM_DPP__MAX]; 566 double MinDPPCLKUsingSingleDPP[DC__NUM_DPP__MAX]; 567 double SwathWidthYSingleDPP[DC__NUM_DPP__MAX]; 568 double BytePerPixelInDETY[DC__NUM_DPP__MAX]; 569 double BytePerPixelInDETC[DC__NUM_DPP__MAX]; 570 bool RequiresDSC[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 571 unsigned int NumberOfDSCSlice[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 572 double RequiresFEC[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 573 double OutputBppPerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 574 double DSCDelayPerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 575 bool ViewportSizeSupport[DC__VOLTAGE_STATES][2]; 576 unsigned int Read256BlockHeightY[DC__NUM_DPP__MAX]; 577 unsigned int Read256BlockWidthY[DC__NUM_DPP__MAX]; 578 unsigned int Read256BlockHeightC[DC__NUM_DPP__MAX]; 579 unsigned int Read256BlockWidthC[DC__NUM_DPP__MAX]; 580 double MaxSwathHeightY[DC__NUM_DPP__MAX]; 581 double MaxSwathHeightC[DC__NUM_DPP__MAX]; 582 double MinSwathHeightY[DC__NUM_DPP__MAX]; 583 double MinSwathHeightC[DC__NUM_DPP__MAX]; 584 double ReadBandwidthLuma[DC__NUM_DPP__MAX]; 585 double ReadBandwidthChroma[DC__NUM_DPP__MAX]; 586 double ReadBandwidth[DC__NUM_DPP__MAX]; 587 double WriteBandwidth[DC__NUM_DPP__MAX]; 588 double PSCL_FACTOR[DC__NUM_DPP__MAX]; 589 double PSCL_FACTOR_CHROMA[DC__NUM_DPP__MAX]; 590 double MaximumVStartup[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 591 unsigned int MacroTileWidthY[DC__NUM_DPP__MAX]; 592 unsigned int MacroTileWidthC[DC__NUM_DPP__MAX]; 593 double AlignedDCCMetaPitch[DC__NUM_DPP__MAX]; 594 double AlignedYPitch[DC__NUM_DPP__MAX]; 595 double AlignedCPitch[DC__NUM_DPP__MAX]; 596 double MaximumSwathWidth[DC__NUM_DPP__MAX]; 597 double cursor_bw[DC__NUM_DPP__MAX]; 598 double cursor_bw_pre[DC__NUM_DPP__MAX]; 599 double Tno_bw[DC__NUM_DPP__MAX]; 600 double prefetch_vmrow_bw[DC__NUM_DPP__MAX]; 601 double DestinationLinesToRequestVMInImmediateFlip[DC__NUM_DPP__MAX]; 602 double DestinationLinesToRequestRowInImmediateFlip[DC__NUM_DPP__MAX]; 603 double final_flip_bw[DC__NUM_DPP__MAX]; 604 bool ImmediateFlipSupportedForState[DC__VOLTAGE_STATES][2]; 605 double WritebackDelay[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; 606 unsigned int vm_group_bytes[DC__NUM_DPP__MAX]; 607 unsigned int dpte_group_bytes[DC__NUM_DPP__MAX]; 608 unsigned int dpte_row_height[DC__NUM_DPP__MAX]; 609 unsigned int meta_req_height[DC__NUM_DPP__MAX]; 610 unsigned int meta_req_width[DC__NUM_DPP__MAX]; 611 unsigned int meta_row_height[DC__NUM_DPP__MAX]; 612 unsigned int meta_row_width[DC__NUM_DPP__MAX]; 613 unsigned int dpte_row_height_chroma[DC__NUM_DPP__MAX]; 614 unsigned int meta_req_height_chroma[DC__NUM_DPP__MAX]; 615 unsigned int meta_req_width_chroma[DC__NUM_DPP__MAX]; 616 unsigned int meta_row_height_chroma[DC__NUM_DPP__MAX]; 617 unsigned int meta_row_width_chroma[DC__NUM_DPP__MAX]; 618 bool ImmediateFlipSupportedForPipe[DC__NUM_DPP__MAX]; 619 double meta_row_bw[DC__NUM_DPP__MAX]; 620 double dpte_row_bw[DC__NUM_DPP__MAX]; 621 double DisplayPipeLineDeliveryTimeLuma[DC__NUM_DPP__MAX]; // WM 622 double DisplayPipeLineDeliveryTimeChroma[DC__NUM_DPP__MAX]; // WM 623 double DisplayPipeRequestDeliveryTimeLuma[DC__NUM_DPP__MAX]; 624 double DisplayPipeRequestDeliveryTimeChroma[DC__NUM_DPP__MAX]; 625 enum clock_change_support DRAMClockChangeSupport[DC__VOLTAGE_STATES][2]; 626 double UrgentBurstFactorCursor[DC__NUM_DPP__MAX]; 627 double UrgentBurstFactorCursorPre[DC__NUM_DPP__MAX]; 628 double UrgentBurstFactorLuma[DC__NUM_DPP__MAX]; 629 double UrgentBurstFactorLumaPre[DC__NUM_DPP__MAX]; 630 double UrgentBurstFactorChroma[DC__NUM_DPP__MAX]; 631 double UrgentBurstFactorChromaPre[DC__NUM_DPP__MAX]; 632 633 634 bool MPCCombine[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 635 double SwathWidthCSingleDPP[DC__NUM_DPP__MAX]; 636 double MaximumSwathWidthInLineBufferLuma; 637 double MaximumSwathWidthInLineBufferChroma; 638 double MaximumSwathWidthLuma[DC__NUM_DPP__MAX]; 639 double MaximumSwathWidthChroma[DC__NUM_DPP__MAX]; 640 enum odm_combine_mode odm_combine_dummy[DC__NUM_DPP__MAX]; 641 double dummy1[DC__NUM_DPP__MAX]; 642 double dummy2[DC__NUM_DPP__MAX]; 643 unsigned int dummy3[DC__NUM_DPP__MAX]; 644 unsigned int dummy4[DC__NUM_DPP__MAX]; 645 double dummy5; 646 double dummy6; 647 double dummy7[DC__NUM_DPP__MAX]; 648 double dummy8[DC__NUM_DPP__MAX]; 649 double dummy13[DC__NUM_DPP__MAX]; 650 unsigned int dummyinteger1ms[DC__NUM_DPP__MAX]; 651 double dummyinteger2ms[DC__NUM_DPP__MAX]; 652 unsigned int dummyinteger3[DC__NUM_DPP__MAX]; 653 unsigned int dummyinteger4[DC__NUM_DPP__MAX]; 654 unsigned int dummyinteger5; 655 unsigned int dummyinteger6; 656 unsigned int dummyinteger7; 657 unsigned int dummyinteger8; 658 unsigned int dummyinteger9; 659 unsigned int dummyinteger10; 660 unsigned int dummyinteger11; 661 unsigned int dummyinteger12; 662 unsigned int dummyinteger30; 663 unsigned int dummyinteger31; 664 unsigned int dummyinteger32; 665 unsigned int dummyintegerarr1[DC__NUM_DPP__MAX]; 666 unsigned int dummyintegerarr2[DC__NUM_DPP__MAX]; 667 unsigned int dummyintegerarr3[DC__NUM_DPP__MAX]; 668 unsigned int dummyintegerarr4[DC__NUM_DPP__MAX]; 669 bool dummysinglestring; 670 bool SingleDPPViewportSizeSupportPerPlane[DC__NUM_DPP__MAX]; 671 double PlaneRequiredDISPCLKWithODMCombine2To1; 672 double PlaneRequiredDISPCLKWithODMCombine4To1; 673 unsigned int TotalNumberOfSingleDPPPlanes[DC__VOLTAGE_STATES][2]; 674 bool LinkDSCEnable; 675 bool ODMCombine4To1SupportCheckOK[DC__VOLTAGE_STATES]; 676 enum odm_combine_mode ODMCombineEnableThisState[DC__NUM_DPP__MAX]; 677 double SwathWidthCThisState[DC__NUM_DPP__MAX]; 678 bool ViewportSizeSupportPerPlane[DC__NUM_DPP__MAX]; 679 double AlignedDCCMetaPitchY[DC__NUM_DPP__MAX]; 680 double AlignedDCCMetaPitchC[DC__NUM_DPP__MAX]; 681 682 unsigned int NotEnoughUrgentLatencyHiding[DC__VOLTAGE_STATES][2]; 683 unsigned int NotEnoughUrgentLatencyHidingPre; 684 int PTEBufferSizeInRequestsForLuma; 685 int PTEBufferSizeInRequestsForChroma; 686 687 // Missing from VBA 688 int dpte_group_bytes_chroma; 689 unsigned int vm_group_bytes_chroma; 690 double dst_x_after_scaler; 691 double dst_y_after_scaler; 692 unsigned int VStartupRequiredWhenNotEnoughTimeForDynamicMetadata; 693 694 /* perf locals*/ 695 double PrefetchBandwidth[DC__NUM_DPP__MAX]; 696 double VInitPreFillY[DC__NUM_DPP__MAX]; 697 double VInitPreFillC[DC__NUM_DPP__MAX]; 698 unsigned int MaxNumSwathY[DC__NUM_DPP__MAX]; 699 unsigned int MaxNumSwathC[DC__NUM_DPP__MAX]; 700 unsigned int VStartup[DC__NUM_DPP__MAX]; 701 double DSTYAfterScaler[DC__NUM_DPP__MAX]; 702 double DSTXAfterScaler[DC__NUM_DPP__MAX]; 703 bool AllowDRAMClockChangeDuringVBlank[DC__NUM_DPP__MAX]; 704 bool AllowDRAMSelfRefreshDuringVBlank[DC__NUM_DPP__MAX]; 705 double VRatioPrefetchY[DC__NUM_DPP__MAX]; 706 double VRatioPrefetchC[DC__NUM_DPP__MAX]; 707 double DestinationLinesForPrefetch[DC__NUM_DPP__MAX]; 708 double DestinationLinesToRequestVMInVBlank[DC__NUM_DPP__MAX]; 709 double DestinationLinesToRequestRowInVBlank[DC__NUM_DPP__MAX]; 710 double MinTTUVBlank[DC__NUM_DPP__MAX]; 711 double BytePerPixelDETY[DC__NUM_DPP__MAX]; 712 double BytePerPixelDETC[DC__NUM_DPP__MAX]; 713 double SwathWidthY[DC__NUM_DPP__MAX]; 714 double SwathWidthSingleDPPY[DC__NUM_DPP__MAX]; 715 double CursorRequestDeliveryTime[DC__NUM_DPP__MAX]; 716 double CursorRequestDeliveryTimePrefetch[DC__NUM_DPP__MAX]; 717 double ReadBandwidthPlaneLuma[DC__NUM_DPP__MAX]; 718 double ReadBandwidthPlaneChroma[DC__NUM_DPP__MAX]; 719 double DisplayPipeLineDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX]; 720 double DisplayPipeLineDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX]; 721 double DisplayPipeRequestDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX]; 722 double DisplayPipeRequestDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX]; 723 double PixelPTEBytesPerRow[DC__NUM_DPP__MAX]; 724 double PDEAndMetaPTEBytesFrame[DC__NUM_DPP__MAX]; 725 double MetaRowByte[DC__NUM_DPP__MAX]; 726 double PrefetchSourceLinesY[DC__NUM_DPP__MAX]; 727 double RequiredPrefetchPixDataBWLuma[DC__NUM_DPP__MAX]; 728 double RequiredPrefetchPixDataBWChroma[DC__NUM_DPP__MAX]; 729 double PrefetchSourceLinesC[DC__NUM_DPP__MAX]; 730 double PSCL_THROUGHPUT_LUMA[DC__NUM_DPP__MAX]; 731 double PSCL_THROUGHPUT_CHROMA[DC__NUM_DPP__MAX]; 732 double DSCCLK_calculated[DC__NUM_DPP__MAX]; 733 unsigned int DSCDelay[DC__NUM_DPP__MAX]; 734 unsigned int MaxVStartupLines[DC__NUM_DPP__MAX]; 735 double DPPCLKUsingSingleDPP[DC__NUM_DPP__MAX]; 736 double DPPCLK[DC__NUM_DPP__MAX]; 737 unsigned int DCCYMaxUncompressedBlock[DC__NUM_DPP__MAX]; 738 unsigned int DCCYMaxCompressedBlock[DC__NUM_DPP__MAX]; 739 unsigned int DCCYIndependent64ByteBlock[DC__NUM_DPP__MAX]; 740 double MaximumDCCCompressionYSurface[DC__NUM_DPP__MAX]; 741 unsigned int BlockHeight256BytesY[DC__NUM_DPP__MAX]; 742 unsigned int BlockHeight256BytesC[DC__NUM_DPP__MAX]; 743 unsigned int BlockWidth256BytesY[DC__NUM_DPP__MAX]; 744 unsigned int BlockWidth256BytesC[DC__NUM_DPP__MAX]; 745 double XFCSlaveVUpdateOffset[DC__NUM_DPP__MAX]; 746 double XFCSlaveVupdateWidth[DC__NUM_DPP__MAX]; 747 double XFCSlaveVReadyOffset[DC__NUM_DPP__MAX]; 748 double XFCTransferDelay[DC__NUM_DPP__MAX]; 749 double XFCPrechargeDelay[DC__NUM_DPP__MAX]; 750 double XFCRemoteSurfaceFlipLatency[DC__NUM_DPP__MAX]; 751 double XFCPrefetchMargin[DC__NUM_DPP__MAX]; 752 unsigned int dpte_row_width_luma_ub[DC__NUM_DPP__MAX]; 753 unsigned int dpte_row_width_chroma_ub[DC__NUM_DPP__MAX]; 754 double FullDETBufferingTimeY[DC__NUM_DPP__MAX]; // WM 755 double FullDETBufferingTimeC[DC__NUM_DPP__MAX]; // WM 756 double DST_Y_PER_PTE_ROW_NOM_L[DC__NUM_DPP__MAX]; 757 double DST_Y_PER_PTE_ROW_NOM_C[DC__NUM_DPP__MAX]; 758 double DST_Y_PER_META_ROW_NOM_L[DC__NUM_DPP__MAX]; 759 double TimePerMetaChunkNominal[DC__NUM_DPP__MAX]; 760 double TimePerMetaChunkVBlank[DC__NUM_DPP__MAX]; 761 double TimePerMetaChunkFlip[DC__NUM_DPP__MAX]; 762 unsigned int swath_width_luma_ub[DC__NUM_DPP__MAX]; 763 unsigned int swath_width_chroma_ub[DC__NUM_DPP__MAX]; 764 unsigned int PixelPTEReqWidthY[DC__NUM_DPP__MAX]; 765 unsigned int PixelPTEReqHeightY[DC__NUM_DPP__MAX]; 766 unsigned int PTERequestSizeY[DC__NUM_DPP__MAX]; 767 unsigned int PixelPTEReqWidthC[DC__NUM_DPP__MAX]; 768 unsigned int PixelPTEReqHeightC[DC__NUM_DPP__MAX]; 769 unsigned int PTERequestSizeC[DC__NUM_DPP__MAX]; 770 double time_per_pte_group_nom_luma[DC__NUM_DPP__MAX]; 771 double time_per_pte_group_nom_chroma[DC__NUM_DPP__MAX]; 772 double time_per_pte_group_vblank_luma[DC__NUM_DPP__MAX]; 773 double time_per_pte_group_vblank_chroma[DC__NUM_DPP__MAX]; 774 double time_per_pte_group_flip_luma[DC__NUM_DPP__MAX]; 775 double time_per_pte_group_flip_chroma[DC__NUM_DPP__MAX]; 776 double TimePerVMGroupVBlank[DC__NUM_DPP__MAX]; 777 double TimePerVMGroupFlip[DC__NUM_DPP__MAX]; 778 double TimePerVMRequestVBlank[DC__NUM_DPP__MAX]; 779 double TimePerVMRequestFlip[DC__NUM_DPP__MAX]; 780 unsigned int dpde0_bytes_per_frame_ub_l[DC__NUM_DPP__MAX]; 781 unsigned int meta_pte_bytes_per_frame_ub_l[DC__NUM_DPP__MAX]; 782 unsigned int dpde0_bytes_per_frame_ub_c[DC__NUM_DPP__MAX]; 783 unsigned int meta_pte_bytes_per_frame_ub_c[DC__NUM_DPP__MAX]; 784 double LinesToFinishSwathTransferStutterCriticalPlane; 785 unsigned int BytePerPixelYCriticalPlane; 786 double SwathWidthYCriticalPlane; 787 double LinesInDETY[DC__NUM_DPP__MAX]; 788 double LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX]; 789 790 double SwathWidthSingleDPPC[DC__NUM_DPP__MAX]; 791 double SwathWidthC[DC__NUM_DPP__MAX]; 792 unsigned int BytePerPixelY[DC__NUM_DPP__MAX]; 793 unsigned int BytePerPixelC[DC__NUM_DPP__MAX]; 794 unsigned int dummyinteger1; 795 unsigned int dummyinteger2; 796 double FinalDRAMClockChangeLatency; 797 double Tdmdl_vm[DC__NUM_DPP__MAX]; 798 double Tdmdl[DC__NUM_DPP__MAX]; 799 double TSetup[DC__NUM_DPP__MAX]; 800 unsigned int ThisVStartup; 801 bool WritebackAllowDRAMClockChangeEndPosition[DC__NUM_DPP__MAX]; 802 double DST_Y_PER_META_ROW_NOM_C[DC__NUM_DPP__MAX]; 803 double TimePerChromaMetaChunkNominal[DC__NUM_DPP__MAX]; 804 double TimePerChromaMetaChunkVBlank[DC__NUM_DPP__MAX]; 805 double TimePerChromaMetaChunkFlip[DC__NUM_DPP__MAX]; 806 unsigned int DCCCMaxUncompressedBlock[DC__NUM_DPP__MAX]; 807 unsigned int DCCCMaxCompressedBlock[DC__NUM_DPP__MAX]; 808 unsigned int DCCCIndependent64ByteBlock[DC__NUM_DPP__MAX]; 809 double VStartupMargin; 810 bool NotEnoughTimeForDynamicMetadata[DC__NUM_DPP__MAX]; 811 812 /* Missing from VBA */ 813 unsigned int MaximumMaxVStartupLines; 814 double FabricAndDRAMBandwidth; 815 double LinesInDETLuma; 816 double LinesInDETChroma; 817 unsigned int ImmediateFlipBytes[DC__NUM_DPP__MAX]; 818 unsigned int LinesInDETC[DC__NUM_DPP__MAX]; 819 unsigned int LinesInDETCRoundedDownToSwath[DC__NUM_DPP__MAX]; 820 double UrgentLatencySupportUsPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 821 double UrgentLatencySupportUs[DC__NUM_DPP__MAX]; 822 double FabricAndDRAMBandwidthPerState[DC__VOLTAGE_STATES]; 823 bool UrgentLatencySupport[DC__VOLTAGE_STATES][2]; 824 unsigned int SwathWidthYPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 825 unsigned int SwathHeightYPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 826 double qual_row_bw[DC__NUM_DPP__MAX]; 827 double prefetch_row_bw[DC__NUM_DPP__MAX]; 828 double prefetch_vm_bw[DC__NUM_DPP__MAX]; 829 830 double PTEGroupSize; 831 unsigned int PDEProcessingBufIn64KBReqs; 832 833 double MaxTotalVActiveRDBandwidth; 834 bool DoUrgentLatencyAdjustment; 835 double UrgentLatencyAdjustmentFabricClockComponent; 836 double UrgentLatencyAdjustmentFabricClockReference; 837 double MinUrgentLatencySupportUs; 838 double MinFullDETBufferingTime; 839 double AverageReadBandwidthGBytePerSecond; 840 bool FirstMainPlane; 841 842 unsigned int ViewportWidthChroma[DC__NUM_DPP__MAX]; 843 unsigned int ViewportHeightChroma[DC__NUM_DPP__MAX]; 844 double HRatioChroma[DC__NUM_DPP__MAX]; 845 double VRatioChroma[DC__NUM_DPP__MAX]; 846 int WritebackSourceWidth[DC__NUM_DPP__MAX]; 847 848 bool ModeIsSupported; 849 bool ODMCombine4To1Supported; 850 851 unsigned int SurfaceWidthY[DC__NUM_DPP__MAX]; 852 unsigned int SurfaceWidthC[DC__NUM_DPP__MAX]; 853 unsigned int SurfaceHeightY[DC__NUM_DPP__MAX]; 854 unsigned int SurfaceHeightC[DC__NUM_DPP__MAX]; 855 unsigned int WritebackHTaps[DC__NUM_DPP__MAX]; 856 unsigned int WritebackVTaps[DC__NUM_DPP__MAX]; 857 bool DSCEnable[DC__NUM_DPP__MAX]; 858 859 double DRAMClockChangeLatencyOverride; 860 861 double GPUVMMinPageSize; 862 double HostVMMinPageSize; 863 864 bool MPCCombineEnable[DC__NUM_DPP__MAX]; 865 unsigned int HostVMMaxNonCachedPageTableLevels; 866 bool DynamicMetadataVMEnabled; 867 double WritebackInterfaceBufferSize; 868 double WritebackLineBufferSize; 869 870 double DCCRateLuma[DC__NUM_DPP__MAX]; 871 double DCCRateChroma[DC__NUM_DPP__MAX]; 872 873 double PHYCLKD18PerState[DC__VOLTAGE_STATES]; 874 875 bool WritebackSupportInterleaveAndUsingWholeBufferForASingleStream; 876 bool NumberOfHDMIFRLSupport; 877 unsigned int MaxNumHDMIFRLOutputs; 878 int AudioSampleRate[DC__NUM_DPP__MAX]; 879 int AudioSampleLayout[DC__NUM_DPP__MAX]; 880 881 int PercentMarginOverMinimumRequiredDCFCLK; 882 bool DynamicMetadataSupported[DC__VOLTAGE_STATES][2]; 883 enum immediate_flip_requirement ImmediateFlipRequirement[DC__NUM_DPP__MAX]; 884 unsigned int DETBufferSizeYThisState[DC__NUM_DPP__MAX]; 885 unsigned int DETBufferSizeCThisState[DC__NUM_DPP__MAX]; 886 bool NoUrgentLatencyHiding[DC__NUM_DPP__MAX]; 887 bool NoUrgentLatencyHidingPre[DC__NUM_DPP__MAX]; 888 int swath_width_luma_ub_this_state[DC__NUM_DPP__MAX]; 889 int swath_width_chroma_ub_this_state[DC__NUM_DPP__MAX]; 890 double UrgLatency[DC__VOLTAGE_STATES]; 891 double VActiveCursorBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 892 double VActivePixelBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 893 bool NoTimeForPrefetch[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 894 bool NoTimeForDynamicMetadata[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 895 double dpte_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 896 double meta_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 897 double DETBufferSizeYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 898 double DETBufferSizeCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 899 int swath_width_luma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 900 int swath_width_chroma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 901 bool NotUrgentLatencyHiding[DC__VOLTAGE_STATES][2]; 902 unsigned int SwathHeightYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 903 unsigned int SwathHeightCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 904 unsigned int SwathWidthYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 905 unsigned int SwathWidthCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; 906 double TotalDPTERowBandwidth[DC__VOLTAGE_STATES][2]; 907 double TotalMetaRowBandwidth[DC__VOLTAGE_STATES][2]; 908 double TotalVActiveCursorBandwidth[DC__VOLTAGE_STATES][2]; 909 double TotalVActivePixelBandwidth[DC__VOLTAGE_STATES][2]; 910 double WritebackDelayTime[DC__NUM_DPP__MAX]; 911 unsigned int DCCYIndependentBlock[DC__NUM_DPP__MAX]; 912 unsigned int DCCCIndependentBlock[DC__NUM_DPP__MAX]; 913 unsigned int dummyinteger15; 914 unsigned int dummyinteger16; 915 unsigned int dummyinteger17; 916 unsigned int dummyinteger18; 917 unsigned int dummyinteger19; 918 unsigned int dummyinteger20; 919 unsigned int dummyinteger21; 920 unsigned int dummyinteger22; 921 unsigned int dummyinteger23; 922 unsigned int dummyinteger24; 923 unsigned int dummyinteger25; 924 unsigned int dummyinteger26; 925 unsigned int dummyinteger27; 926 unsigned int dummyinteger28; 927 unsigned int dummyinteger29; 928 bool dummystring[DC__NUM_DPP__MAX]; 929 double BPP; 930 enum odm_combine_policy ODMCombinePolicy; 931 bool UseMinimumRequiredDCFCLK; 932 bool ClampMinDCFCLK; 933 bool AllowDramClockChangeOneDisplayVactive; 934 935 double MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation; 936 double PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency; 937 double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData; 938 double PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly; 939 double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly; 940 double SRExitZ8Time; 941 double SREnterPlusExitZ8Time; 942 double Z8StutterExitWatermark; 943 double Z8StutterEnterPlusExitWatermark; 944 double Z8StutterEfficiencyNotIncludingVBlank; 945 double Z8StutterEfficiency; 946 double DCCFractionOfZeroSizeRequestsLuma[DC__NUM_DPP__MAX]; 947 double DCCFractionOfZeroSizeRequestsChroma[DC__NUM_DPP__MAX]; 948 double UrgBurstFactorCursor[DC__NUM_DPP__MAX]; 949 double UrgBurstFactorLuma[DC__NUM_DPP__MAX]; 950 double UrgBurstFactorChroma[DC__NUM_DPP__MAX]; 951 double UrgBurstFactorCursorPre[DC__NUM_DPP__MAX]; 952 double UrgBurstFactorLumaPre[DC__NUM_DPP__MAX]; 953 double UrgBurstFactorChromaPre[DC__NUM_DPP__MAX]; 954 bool NotUrgentLatencyHidingPre[DC__NUM_DPP__MAX]; 955 bool LinkCapacitySupport[DC__NUM_DPP__MAX]; 956 bool VREADY_AT_OR_AFTER_VSYNC[DC__NUM_DPP__MAX]; 957 unsigned int MIN_DST_Y_NEXT_START[DC__NUM_DPP__MAX]; 958 unsigned int VFrontPorch[DC__NUM_DPP__MAX]; 959 int ConfigReturnBufferSizeInKByte; 960 enum unbounded_requesting_policy UseUnboundedRequesting; 961 int CompressedBufferSegmentSizeInkByte; 962 int CompressedBufferSizeInkByte; 963 int MetaFIFOSizeInKEntries; 964 int ZeroSizeBufferEntries; 965 int COMPBUF_RESERVED_SPACE_64B; 966 int COMPBUF_RESERVED_SPACE_ZS; 967 bool UnboundedRequestEnabled; 968 bool DSC422NativeSupport; 969 bool NoEnoughUrgentLatencyHiding; 970 bool NoEnoughUrgentLatencyHidingPre; 971 int NumberOfStutterBurstsPerFrame; 972 int Z8NumberOfStutterBurstsPerFrame; 973 unsigned int MaximumDSCBitsPerComponent; 974 unsigned int NotEnoughUrgentLatencyHidingA[DC__VOLTAGE_STATES][2]; 975 }; 976 977 bool CalculateMinAndMaxPrefetchMode( 978 enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank, 979 unsigned int *MinPrefetchMode, 980 unsigned int *MaxPrefetchMode); 981 982 double CalculateWriteBackDISPCLK( 983 enum source_format_class WritebackPixelFormat, 984 double PixelClock, 985 double WritebackHRatio, 986 double WritebackVRatio, 987 unsigned int WritebackLumaHTaps, 988 unsigned int WritebackLumaVTaps, 989 unsigned int WritebackChromaHTaps, 990 unsigned int WritebackChromaVTaps, 991 double WritebackDestinationWidth, 992 unsigned int HTotal, 993 unsigned int WritebackChromaLineBufferWidth); 994 995 #endif /* _DML2_DISPLAY_MODE_VBA_H_ */ 996