1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Macros for accessing system registers with older binutils.
4  *
5  * Copyright (C) 2014 ARM Ltd.
6  * Author: Catalin Marinas <catalin.marinas@arm.com>
7  */
8 
9 #ifndef __ASM_SYSREG_H
10 #define __ASM_SYSREG_H
11 
12 #include <linux/bits.h>
13 #include <linux/stringify.h>
14 #include <linux/kasan-tags.h>
15 
16 #include <asm/gpr-num.h>
17 
18 /*
19  * ARMv8 ARM reserves the following encoding for system registers:
20  * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
21  *  C5.2, version:ARM DDI 0487A.f)
22  *	[20-19] : Op0
23  *	[18-16] : Op1
24  *	[15-12] : CRn
25  *	[11-8]  : CRm
26  *	[7-5]   : Op2
27  */
28 #define Op0_shift	19
29 #define Op0_mask	0x3
30 #define Op1_shift	16
31 #define Op1_mask	0x7
32 #define CRn_shift	12
33 #define CRn_mask	0xf
34 #define CRm_shift	8
35 #define CRm_mask	0xf
36 #define Op2_shift	5
37 #define Op2_mask	0x7
38 
39 #define sys_reg(op0, op1, crn, crm, op2) \
40 	(((op0) << Op0_shift) | ((op1) << Op1_shift) | \
41 	 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
42 	 ((op2) << Op2_shift))
43 
44 #define sys_insn	sys_reg
45 
46 #define sys_reg_Op0(id)	(((id) >> Op0_shift) & Op0_mask)
47 #define sys_reg_Op1(id)	(((id) >> Op1_shift) & Op1_mask)
48 #define sys_reg_CRn(id)	(((id) >> CRn_shift) & CRn_mask)
49 #define sys_reg_CRm(id)	(((id) >> CRm_shift) & CRm_mask)
50 #define sys_reg_Op2(id)	(((id) >> Op2_shift) & Op2_mask)
51 
52 #ifndef CONFIG_BROKEN_GAS_INST
53 
54 #ifdef __ASSEMBLY__
55 // The space separator is omitted so that __emit_inst(x) can be parsed as
56 // either an assembler directive or an assembler macro argument.
57 #define __emit_inst(x)			.inst(x)
58 #else
59 #define __emit_inst(x)			".inst " __stringify((x)) "\n\t"
60 #endif
61 
62 #else  /* CONFIG_BROKEN_GAS_INST */
63 
64 #ifndef CONFIG_CPU_BIG_ENDIAN
65 #define __INSTR_BSWAP(x)		(x)
66 #else  /* CONFIG_CPU_BIG_ENDIAN */
67 #define __INSTR_BSWAP(x)		((((x) << 24) & 0xff000000)	| \
68 					 (((x) <<  8) & 0x00ff0000)	| \
69 					 (((x) >>  8) & 0x0000ff00)	| \
70 					 (((x) >> 24) & 0x000000ff))
71 #endif	/* CONFIG_CPU_BIG_ENDIAN */
72 
73 #ifdef __ASSEMBLY__
74 #define __emit_inst(x)			.long __INSTR_BSWAP(x)
75 #else  /* __ASSEMBLY__ */
76 #define __emit_inst(x)			".long " __stringify(__INSTR_BSWAP(x)) "\n\t"
77 #endif	/* __ASSEMBLY__ */
78 
79 #endif	/* CONFIG_BROKEN_GAS_INST */
80 
81 /*
82  * Instructions for modifying PSTATE fields.
83  * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
84  * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions
85  * for accessing PSTATE fields have the following encoding:
86  *	Op0 = 0, CRn = 4
87  *	Op1, Op2 encodes the PSTATE field modified and defines the constraints.
88  *	CRm = Imm4 for the instruction.
89  *	Rt = 0x1f
90  */
91 #define pstate_field(op1, op2)		((op1) << Op1_shift | (op2) << Op2_shift)
92 #define PSTATE_Imm_shift		CRm_shift
93 #define SET_PSTATE(x, r)		__emit_inst(0xd500401f | PSTATE_ ## r | ((!!x) << PSTATE_Imm_shift))
94 
95 #define PSTATE_PAN			pstate_field(0, 4)
96 #define PSTATE_UAO			pstate_field(0, 3)
97 #define PSTATE_SSBS			pstate_field(3, 1)
98 #define PSTATE_DIT			pstate_field(3, 2)
99 #define PSTATE_TCO			pstate_field(3, 4)
100 
101 #define SET_PSTATE_PAN(x)		SET_PSTATE((x), PAN)
102 #define SET_PSTATE_UAO(x)		SET_PSTATE((x), UAO)
103 #define SET_PSTATE_SSBS(x)		SET_PSTATE((x), SSBS)
104 #define SET_PSTATE_DIT(x)		SET_PSTATE((x), DIT)
105 #define SET_PSTATE_TCO(x)		SET_PSTATE((x), TCO)
106 
107 #define set_pstate_pan(x)		asm volatile(SET_PSTATE_PAN(x))
108 #define set_pstate_uao(x)		asm volatile(SET_PSTATE_UAO(x))
109 #define set_pstate_ssbs(x)		asm volatile(SET_PSTATE_SSBS(x))
110 #define set_pstate_dit(x)		asm volatile(SET_PSTATE_DIT(x))
111 
112 #define __SYS_BARRIER_INSN(CRm, op2, Rt) \
113 	__emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
114 
115 #define SB_BARRIER_INSN			__SYS_BARRIER_INSN(0, 7, 31)
116 
117 #define SYS_DC_ISW			sys_insn(1, 0, 7, 6, 2)
118 #define SYS_DC_IGSW			sys_insn(1, 0, 7, 6, 4)
119 #define SYS_DC_IGDSW			sys_insn(1, 0, 7, 6, 6)
120 #define SYS_DC_CSW			sys_insn(1, 0, 7, 10, 2)
121 #define SYS_DC_CGSW			sys_insn(1, 0, 7, 10, 4)
122 #define SYS_DC_CGDSW			sys_insn(1, 0, 7, 10, 6)
123 #define SYS_DC_CISW			sys_insn(1, 0, 7, 14, 2)
124 #define SYS_DC_CIGSW			sys_insn(1, 0, 7, 14, 4)
125 #define SYS_DC_CIGDSW			sys_insn(1, 0, 7, 14, 6)
126 
127 #define SYS_IC_IALLUIS			sys_insn(1, 0, 7, 1, 0)
128 #define SYS_IC_IALLU			sys_insn(1, 0, 7, 5, 0)
129 #define SYS_IC_IVAU			sys_insn(1, 3, 7, 5, 1)
130 
131 #define SYS_DC_IVAC			sys_insn(1, 0, 7, 6, 1)
132 #define SYS_DC_IGVAC			sys_insn(1, 0, 7, 6, 3)
133 #define SYS_DC_IGDVAC			sys_insn(1, 0, 7, 6, 5)
134 
135 #define SYS_DC_CVAC			sys_insn(1, 3, 7, 10, 1)
136 #define SYS_DC_CGVAC			sys_insn(1, 3, 7, 10, 3)
137 #define SYS_DC_CGDVAC			sys_insn(1, 3, 7, 10, 5)
138 
139 #define SYS_DC_CVAU			sys_insn(1, 3, 7, 11, 1)
140 
141 #define SYS_DC_CVAP			sys_insn(1, 3, 7, 12, 1)
142 #define SYS_DC_CGVAP			sys_insn(1, 3, 7, 12, 3)
143 #define SYS_DC_CGDVAP			sys_insn(1, 3, 7, 12, 5)
144 
145 #define SYS_DC_CVADP			sys_insn(1, 3, 7, 13, 1)
146 #define SYS_DC_CGVADP			sys_insn(1, 3, 7, 13, 3)
147 #define SYS_DC_CGDVADP			sys_insn(1, 3, 7, 13, 5)
148 
149 #define SYS_DC_CIVAC			sys_insn(1, 3, 7, 14, 1)
150 #define SYS_DC_CIGVAC			sys_insn(1, 3, 7, 14, 3)
151 #define SYS_DC_CIGDVAC			sys_insn(1, 3, 7, 14, 5)
152 
153 /* Data cache zero operations */
154 #define SYS_DC_ZVA			sys_insn(1, 3, 7, 4, 1)
155 #define SYS_DC_GVA			sys_insn(1, 3, 7, 4, 3)
156 #define SYS_DC_GZVA			sys_insn(1, 3, 7, 4, 4)
157 
158 /*
159  * Automatically generated definitions for system registers, the
160  * manual encodings below are in the process of being converted to
161  * come from here. The header relies on the definition of sys_reg()
162  * earlier in this file.
163  */
164 #include "asm/sysreg-defs.h"
165 
166 /*
167  * System registers, organised loosely by encoding but grouped together
168  * where the architected name contains an index. e.g. ID_MMFR<n>_EL1.
169  */
170 #define SYS_SVCR_SMSTOP_SM_EL0		sys_reg(0, 3, 4, 2, 3)
171 #define SYS_SVCR_SMSTART_SM_EL0		sys_reg(0, 3, 4, 3, 3)
172 #define SYS_SVCR_SMSTOP_SMZA_EL0	sys_reg(0, 3, 4, 6, 3)
173 
174 #define SYS_DBGBVRn_EL1(n)		sys_reg(2, 0, 0, n, 4)
175 #define SYS_DBGBCRn_EL1(n)		sys_reg(2, 0, 0, n, 5)
176 #define SYS_DBGWVRn_EL1(n)		sys_reg(2, 0, 0, n, 6)
177 #define SYS_DBGWCRn_EL1(n)		sys_reg(2, 0, 0, n, 7)
178 #define SYS_MDRAR_EL1			sys_reg(2, 0, 1, 0, 0)
179 
180 #define SYS_OSLSR_EL1			sys_reg(2, 0, 1, 1, 4)
181 #define OSLSR_EL1_OSLM_MASK		(BIT(3) | BIT(0))
182 #define OSLSR_EL1_OSLM_NI		0
183 #define OSLSR_EL1_OSLM_IMPLEMENTED	BIT(3)
184 #define OSLSR_EL1_OSLK			BIT(1)
185 
186 #define SYS_OSDLR_EL1			sys_reg(2, 0, 1, 3, 4)
187 #define SYS_DBGPRCR_EL1			sys_reg(2, 0, 1, 4, 4)
188 #define SYS_DBGCLAIMSET_EL1		sys_reg(2, 0, 7, 8, 6)
189 #define SYS_DBGCLAIMCLR_EL1		sys_reg(2, 0, 7, 9, 6)
190 #define SYS_DBGAUTHSTATUS_EL1		sys_reg(2, 0, 7, 14, 6)
191 #define SYS_MDCCSR_EL0			sys_reg(2, 3, 0, 1, 0)
192 #define SYS_DBGDTR_EL0			sys_reg(2, 3, 0, 4, 0)
193 #define SYS_DBGDTRRX_EL0		sys_reg(2, 3, 0, 5, 0)
194 #define SYS_DBGDTRTX_EL0		sys_reg(2, 3, 0, 5, 0)
195 #define SYS_DBGVCR32_EL2		sys_reg(2, 4, 0, 7, 0)
196 
197 #define SYS_BRBINF_EL1(n)		sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
198 #define SYS_BRBINFINJ_EL1		sys_reg(2, 1, 9, 1, 0)
199 #define SYS_BRBSRC_EL1(n)		sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1))
200 #define SYS_BRBSRCINJ_EL1		sys_reg(2, 1, 9, 1, 1)
201 #define SYS_BRBTGT_EL1(n)		sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2))
202 #define SYS_BRBTGTINJ_EL1		sys_reg(2, 1, 9, 1, 2)
203 #define SYS_BRBTS_EL1			sys_reg(2, 1, 9, 0, 2)
204 
205 #define SYS_BRBCR_EL1			sys_reg(2, 1, 9, 0, 0)
206 #define SYS_BRBFCR_EL1			sys_reg(2, 1, 9, 0, 1)
207 #define SYS_BRBIDR0_EL1			sys_reg(2, 1, 9, 2, 0)
208 
209 #define SYS_TRCITECR_EL1		sys_reg(3, 0, 1, 2, 3)
210 #define SYS_TRCACATR(m)			sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
211 #define SYS_TRCACVR(m)			sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3)))
212 #define SYS_TRCAUTHSTATUS		sys_reg(2, 1, 7, 14, 6)
213 #define SYS_TRCAUXCTLR			sys_reg(2, 1, 0, 6, 0)
214 #define SYS_TRCBBCTLR			sys_reg(2, 1, 0, 15, 0)
215 #define SYS_TRCCCCTLR			sys_reg(2, 1, 0, 14, 0)
216 #define SYS_TRCCIDCCTLR0		sys_reg(2, 1, 3, 0, 2)
217 #define SYS_TRCCIDCCTLR1		sys_reg(2, 1, 3, 1, 2)
218 #define SYS_TRCCIDCVR(m)		sys_reg(2, 1, 3, ((m & 7) << 1), 0)
219 #define SYS_TRCCLAIMCLR			sys_reg(2, 1, 7, 9, 6)
220 #define SYS_TRCCLAIMSET			sys_reg(2, 1, 7, 8, 6)
221 #define SYS_TRCCNTCTLR(m)		sys_reg(2, 1, 0, (4 | (m & 3)), 5)
222 #define SYS_TRCCNTRLDVR(m)		sys_reg(2, 1, 0, (0 | (m & 3)), 5)
223 #define SYS_TRCCNTVR(m)			sys_reg(2, 1, 0, (8 | (m & 3)), 5)
224 #define SYS_TRCCONFIGR			sys_reg(2, 1, 0, 4, 0)
225 #define SYS_TRCDEVARCH			sys_reg(2, 1, 7, 15, 6)
226 #define SYS_TRCDEVID			sys_reg(2, 1, 7, 2, 7)
227 #define SYS_TRCEVENTCTL0R		sys_reg(2, 1, 0, 8, 0)
228 #define SYS_TRCEVENTCTL1R		sys_reg(2, 1, 0, 9, 0)
229 #define SYS_TRCEXTINSELR(m)		sys_reg(2, 1, 0, (8 | (m & 3)), 4)
230 #define SYS_TRCIDR0			sys_reg(2, 1, 0, 8, 7)
231 #define SYS_TRCIDR10			sys_reg(2, 1, 0, 2, 6)
232 #define SYS_TRCIDR11			sys_reg(2, 1, 0, 3, 6)
233 #define SYS_TRCIDR12			sys_reg(2, 1, 0, 4, 6)
234 #define SYS_TRCIDR13			sys_reg(2, 1, 0, 5, 6)
235 #define SYS_TRCIDR1			sys_reg(2, 1, 0, 9, 7)
236 #define SYS_TRCIDR2			sys_reg(2, 1, 0, 10, 7)
237 #define SYS_TRCIDR3			sys_reg(2, 1, 0, 11, 7)
238 #define SYS_TRCIDR4			sys_reg(2, 1, 0, 12, 7)
239 #define SYS_TRCIDR5			sys_reg(2, 1, 0, 13, 7)
240 #define SYS_TRCIDR6			sys_reg(2, 1, 0, 14, 7)
241 #define SYS_TRCIDR7			sys_reg(2, 1, 0, 15, 7)
242 #define SYS_TRCIDR8			sys_reg(2, 1, 0, 0, 6)
243 #define SYS_TRCIDR9			sys_reg(2, 1, 0, 1, 6)
244 #define SYS_TRCIMSPEC(m)		sys_reg(2, 1, 0, (m & 7), 7)
245 #define SYS_TRCITEEDCR			sys_reg(2, 1, 0, 2, 1)
246 #define SYS_TRCOSLSR			sys_reg(2, 1, 1, 1, 4)
247 #define SYS_TRCPRGCTLR			sys_reg(2, 1, 0, 1, 0)
248 #define SYS_TRCQCTLR			sys_reg(2, 1, 0, 1, 1)
249 #define SYS_TRCRSCTLR(m)		sys_reg(2, 1, 1, (m & 15), (0 | (m >> 4)))
250 #define SYS_TRCRSR			sys_reg(2, 1, 0, 10, 0)
251 #define SYS_TRCSEQEVR(m)		sys_reg(2, 1, 0, (m & 3), 4)
252 #define SYS_TRCSEQRSTEVR		sys_reg(2, 1, 0, 6, 4)
253 #define SYS_TRCSEQSTR			sys_reg(2, 1, 0, 7, 4)
254 #define SYS_TRCSSCCR(m)			sys_reg(2, 1, 1, (m & 7), 2)
255 #define SYS_TRCSSCSR(m)			sys_reg(2, 1, 1, (8 | (m & 7)), 2)
256 #define SYS_TRCSSPCICR(m)		sys_reg(2, 1, 1, (m & 7), 3)
257 #define SYS_TRCSTALLCTLR		sys_reg(2, 1, 0, 11, 0)
258 #define SYS_TRCSTATR			sys_reg(2, 1, 0, 3, 0)
259 #define SYS_TRCSYNCPR			sys_reg(2, 1, 0, 13, 0)
260 #define SYS_TRCTRACEIDR			sys_reg(2, 1, 0, 0, 1)
261 #define SYS_TRCTSCTLR			sys_reg(2, 1, 0, 12, 0)
262 #define SYS_TRCVICTLR			sys_reg(2, 1, 0, 0, 2)
263 #define SYS_TRCVIIECTLR			sys_reg(2, 1, 0, 1, 2)
264 #define SYS_TRCVIPCSSCTLR		sys_reg(2, 1, 0, 3, 2)
265 #define SYS_TRCVISSCTLR			sys_reg(2, 1, 0, 2, 2)
266 #define SYS_TRCVMIDCCTLR0		sys_reg(2, 1, 3, 2, 2)
267 #define SYS_TRCVMIDCCTLR1		sys_reg(2, 1, 3, 3, 2)
268 #define SYS_TRCVMIDCVR(m)		sys_reg(2, 1, 3, ((m & 7) << 1), 1)
269 
270 /* ETM */
271 #define SYS_TRCOSLAR			sys_reg(2, 1, 1, 0, 4)
272 
273 #define SYS_MIDR_EL1			sys_reg(3, 0, 0, 0, 0)
274 #define SYS_MPIDR_EL1			sys_reg(3, 0, 0, 0, 5)
275 #define SYS_REVIDR_EL1			sys_reg(3, 0, 0, 0, 6)
276 
277 #define SYS_ACTLR_EL1			sys_reg(3, 0, 1, 0, 1)
278 #define SYS_RGSR_EL1			sys_reg(3, 0, 1, 0, 5)
279 #define SYS_GCR_EL1			sys_reg(3, 0, 1, 0, 6)
280 
281 #define SYS_TRFCR_EL1			sys_reg(3, 0, 1, 2, 1)
282 
283 #define SYS_TCR_EL1			sys_reg(3, 0, 2, 0, 2)
284 
285 #define SYS_APIAKEYLO_EL1		sys_reg(3, 0, 2, 1, 0)
286 #define SYS_APIAKEYHI_EL1		sys_reg(3, 0, 2, 1, 1)
287 #define SYS_APIBKEYLO_EL1		sys_reg(3, 0, 2, 1, 2)
288 #define SYS_APIBKEYHI_EL1		sys_reg(3, 0, 2, 1, 3)
289 
290 #define SYS_APDAKEYLO_EL1		sys_reg(3, 0, 2, 2, 0)
291 #define SYS_APDAKEYHI_EL1		sys_reg(3, 0, 2, 2, 1)
292 #define SYS_APDBKEYLO_EL1		sys_reg(3, 0, 2, 2, 2)
293 #define SYS_APDBKEYHI_EL1		sys_reg(3, 0, 2, 2, 3)
294 
295 #define SYS_APGAKEYLO_EL1		sys_reg(3, 0, 2, 3, 0)
296 #define SYS_APGAKEYHI_EL1		sys_reg(3, 0, 2, 3, 1)
297 
298 #define SYS_SPSR_EL1			sys_reg(3, 0, 4, 0, 0)
299 #define SYS_ELR_EL1			sys_reg(3, 0, 4, 0, 1)
300 
301 #define SYS_ICC_PMR_EL1			sys_reg(3, 0, 4, 6, 0)
302 
303 #define SYS_AFSR0_EL1			sys_reg(3, 0, 5, 1, 0)
304 #define SYS_AFSR1_EL1			sys_reg(3, 0, 5, 1, 1)
305 #define SYS_ESR_EL1			sys_reg(3, 0, 5, 2, 0)
306 
307 #define SYS_ERRIDR_EL1			sys_reg(3, 0, 5, 3, 0)
308 #define SYS_ERRSELR_EL1			sys_reg(3, 0, 5, 3, 1)
309 #define SYS_ERXFR_EL1			sys_reg(3, 0, 5, 4, 0)
310 #define SYS_ERXCTLR_EL1			sys_reg(3, 0, 5, 4, 1)
311 #define SYS_ERXSTATUS_EL1		sys_reg(3, 0, 5, 4, 2)
312 #define SYS_ERXADDR_EL1			sys_reg(3, 0, 5, 4, 3)
313 #define SYS_ERXPFGF_EL1			sys_reg(3, 0, 5, 4, 4)
314 #define SYS_ERXPFGCTL_EL1		sys_reg(3, 0, 5, 4, 5)
315 #define SYS_ERXPFGCDN_EL1		sys_reg(3, 0, 5, 4, 6)
316 #define SYS_ERXMISC0_EL1		sys_reg(3, 0, 5, 5, 0)
317 #define SYS_ERXMISC1_EL1		sys_reg(3, 0, 5, 5, 1)
318 #define SYS_ERXMISC2_EL1		sys_reg(3, 0, 5, 5, 2)
319 #define SYS_ERXMISC3_EL1		sys_reg(3, 0, 5, 5, 3)
320 #define SYS_TFSR_EL1			sys_reg(3, 0, 5, 6, 0)
321 #define SYS_TFSRE0_EL1			sys_reg(3, 0, 5, 6, 1)
322 
323 #define SYS_PAR_EL1			sys_reg(3, 0, 7, 4, 0)
324 
325 #define SYS_PAR_EL1_F			BIT(0)
326 #define SYS_PAR_EL1_FST			GENMASK(6, 1)
327 
328 /*** Statistical Profiling Extension ***/
329 #define PMSEVFR_EL1_RES0_IMP	\
330 	(GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\
331 	 BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
332 #define PMSEVFR_EL1_RES0_V1P1	\
333 	(PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))
334 #define PMSEVFR_EL1_RES0_V1P2	\
335 	(PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6))
336 
337 /* Buffer error reporting */
338 #define PMBSR_EL1_FAULT_FSC_SHIFT	PMBSR_EL1_MSS_SHIFT
339 #define PMBSR_EL1_FAULT_FSC_MASK	PMBSR_EL1_MSS_MASK
340 
341 #define PMBSR_EL1_BUF_BSC_SHIFT		PMBSR_EL1_MSS_SHIFT
342 #define PMBSR_EL1_BUF_BSC_MASK		PMBSR_EL1_MSS_MASK
343 
344 #define PMBSR_EL1_BUF_BSC_FULL		0x1UL
345 
346 /*** End of Statistical Profiling Extension ***/
347 
348 #define TRBSR_EL1_BSC_MASK		GENMASK(5, 0)
349 #define TRBSR_EL1_BSC_SHIFT		0
350 
351 #define SYS_PMINTENSET_EL1		sys_reg(3, 0, 9, 14, 1)
352 #define SYS_PMINTENCLR_EL1		sys_reg(3, 0, 9, 14, 2)
353 
354 #define SYS_PMMIR_EL1			sys_reg(3, 0, 9, 14, 6)
355 
356 #define SYS_MAIR_EL1			sys_reg(3, 0, 10, 2, 0)
357 #define SYS_AMAIR_EL1			sys_reg(3, 0, 10, 3, 0)
358 
359 #define SYS_VBAR_EL1			sys_reg(3, 0, 12, 0, 0)
360 #define SYS_DISR_EL1			sys_reg(3, 0, 12, 1, 1)
361 
362 #define SYS_ICC_IAR0_EL1		sys_reg(3, 0, 12, 8, 0)
363 #define SYS_ICC_EOIR0_EL1		sys_reg(3, 0, 12, 8, 1)
364 #define SYS_ICC_HPPIR0_EL1		sys_reg(3, 0, 12, 8, 2)
365 #define SYS_ICC_BPR0_EL1		sys_reg(3, 0, 12, 8, 3)
366 #define SYS_ICC_AP0Rn_EL1(n)		sys_reg(3, 0, 12, 8, 4 | n)
367 #define SYS_ICC_AP0R0_EL1		SYS_ICC_AP0Rn_EL1(0)
368 #define SYS_ICC_AP0R1_EL1		SYS_ICC_AP0Rn_EL1(1)
369 #define SYS_ICC_AP0R2_EL1		SYS_ICC_AP0Rn_EL1(2)
370 #define SYS_ICC_AP0R3_EL1		SYS_ICC_AP0Rn_EL1(3)
371 #define SYS_ICC_AP1Rn_EL1(n)		sys_reg(3, 0, 12, 9, n)
372 #define SYS_ICC_AP1R0_EL1		SYS_ICC_AP1Rn_EL1(0)
373 #define SYS_ICC_AP1R1_EL1		SYS_ICC_AP1Rn_EL1(1)
374 #define SYS_ICC_AP1R2_EL1		SYS_ICC_AP1Rn_EL1(2)
375 #define SYS_ICC_AP1R3_EL1		SYS_ICC_AP1Rn_EL1(3)
376 #define SYS_ICC_DIR_EL1			sys_reg(3, 0, 12, 11, 1)
377 #define SYS_ICC_RPR_EL1			sys_reg(3, 0, 12, 11, 3)
378 #define SYS_ICC_SGI1R_EL1		sys_reg(3, 0, 12, 11, 5)
379 #define SYS_ICC_ASGI1R_EL1		sys_reg(3, 0, 12, 11, 6)
380 #define SYS_ICC_SGI0R_EL1		sys_reg(3, 0, 12, 11, 7)
381 #define SYS_ICC_IAR1_EL1		sys_reg(3, 0, 12, 12, 0)
382 #define SYS_ICC_EOIR1_EL1		sys_reg(3, 0, 12, 12, 1)
383 #define SYS_ICC_HPPIR1_EL1		sys_reg(3, 0, 12, 12, 2)
384 #define SYS_ICC_BPR1_EL1		sys_reg(3, 0, 12, 12, 3)
385 #define SYS_ICC_CTLR_EL1		sys_reg(3, 0, 12, 12, 4)
386 #define SYS_ICC_SRE_EL1			sys_reg(3, 0, 12, 12, 5)
387 #define SYS_ICC_IGRPEN0_EL1		sys_reg(3, 0, 12, 12, 6)
388 #define SYS_ICC_IGRPEN1_EL1		sys_reg(3, 0, 12, 12, 7)
389 
390 #define SYS_ACCDATA_EL1			sys_reg(3, 0, 13, 0, 5)
391 
392 #define SYS_CNTKCTL_EL1			sys_reg(3, 0, 14, 1, 0)
393 
394 #define SYS_AIDR_EL1			sys_reg(3, 1, 0, 0, 7)
395 
396 #define SYS_RNDR_EL0			sys_reg(3, 3, 2, 4, 0)
397 #define SYS_RNDRRS_EL0			sys_reg(3, 3, 2, 4, 1)
398 
399 #define SYS_PMCR_EL0			sys_reg(3, 3, 9, 12, 0)
400 #define SYS_PMCNTENSET_EL0		sys_reg(3, 3, 9, 12, 1)
401 #define SYS_PMCNTENCLR_EL0		sys_reg(3, 3, 9, 12, 2)
402 #define SYS_PMOVSCLR_EL0		sys_reg(3, 3, 9, 12, 3)
403 #define SYS_PMSWINC_EL0			sys_reg(3, 3, 9, 12, 4)
404 #define SYS_PMSELR_EL0			sys_reg(3, 3, 9, 12, 5)
405 #define SYS_PMCEID0_EL0			sys_reg(3, 3, 9, 12, 6)
406 #define SYS_PMCEID1_EL0			sys_reg(3, 3, 9, 12, 7)
407 #define SYS_PMCCNTR_EL0			sys_reg(3, 3, 9, 13, 0)
408 #define SYS_PMXEVTYPER_EL0		sys_reg(3, 3, 9, 13, 1)
409 #define SYS_PMXEVCNTR_EL0		sys_reg(3, 3, 9, 13, 2)
410 #define SYS_PMUSERENR_EL0		sys_reg(3, 3, 9, 14, 0)
411 #define SYS_PMOVSSET_EL0		sys_reg(3, 3, 9, 14, 3)
412 
413 #define SYS_TPIDR_EL0			sys_reg(3, 3, 13, 0, 2)
414 #define SYS_TPIDRRO_EL0			sys_reg(3, 3, 13, 0, 3)
415 #define SYS_TPIDR2_EL0			sys_reg(3, 3, 13, 0, 5)
416 
417 #define SYS_SCXTNUM_EL0			sys_reg(3, 3, 13, 0, 7)
418 
419 /* Definitions for system register interface to AMU for ARMv8.4 onwards */
420 #define SYS_AM_EL0(crm, op2)		sys_reg(3, 3, 13, (crm), (op2))
421 #define SYS_AMCR_EL0			SYS_AM_EL0(2, 0)
422 #define SYS_AMCFGR_EL0			SYS_AM_EL0(2, 1)
423 #define SYS_AMCGCR_EL0			SYS_AM_EL0(2, 2)
424 #define SYS_AMUSERENR_EL0		SYS_AM_EL0(2, 3)
425 #define SYS_AMCNTENCLR0_EL0		SYS_AM_EL0(2, 4)
426 #define SYS_AMCNTENSET0_EL0		SYS_AM_EL0(2, 5)
427 #define SYS_AMCNTENCLR1_EL0		SYS_AM_EL0(3, 0)
428 #define SYS_AMCNTENSET1_EL0		SYS_AM_EL0(3, 1)
429 
430 /*
431  * Group 0 of activity monitors (architected):
432  *                op0  op1  CRn   CRm       op2
433  * Counter:       11   011  1101  010:n<3>  n<2:0>
434  * Type:          11   011  1101  011:n<3>  n<2:0>
435  * n: 0-15
436  *
437  * Group 1 of activity monitors (auxiliary):
438  *                op0  op1  CRn   CRm       op2
439  * Counter:       11   011  1101  110:n<3>  n<2:0>
440  * Type:          11   011  1101  111:n<3>  n<2:0>
441  * n: 0-15
442  */
443 
444 #define SYS_AMEVCNTR0_EL0(n)		SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
445 #define SYS_AMEVTYPER0_EL0(n)		SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
446 #define SYS_AMEVCNTR1_EL0(n)		SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
447 #define SYS_AMEVTYPER1_EL0(n)		SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
448 
449 /* AMU v1: Fixed (architecturally defined) activity monitors */
450 #define SYS_AMEVCNTR0_CORE_EL0		SYS_AMEVCNTR0_EL0(0)
451 #define SYS_AMEVCNTR0_CONST_EL0		SYS_AMEVCNTR0_EL0(1)
452 #define SYS_AMEVCNTR0_INST_RET_EL0	SYS_AMEVCNTR0_EL0(2)
453 #define SYS_AMEVCNTR0_MEM_STALL		SYS_AMEVCNTR0_EL0(3)
454 
455 #define SYS_CNTFRQ_EL0			sys_reg(3, 3, 14, 0, 0)
456 
457 #define SYS_CNTPCT_EL0			sys_reg(3, 3, 14, 0, 1)
458 #define SYS_CNTPCTSS_EL0		sys_reg(3, 3, 14, 0, 5)
459 #define SYS_CNTVCTSS_EL0		sys_reg(3, 3, 14, 0, 6)
460 
461 #define SYS_CNTP_TVAL_EL0		sys_reg(3, 3, 14, 2, 0)
462 #define SYS_CNTP_CTL_EL0		sys_reg(3, 3, 14, 2, 1)
463 #define SYS_CNTP_CVAL_EL0		sys_reg(3, 3, 14, 2, 2)
464 
465 #define SYS_CNTV_CTL_EL0		sys_reg(3, 3, 14, 3, 1)
466 #define SYS_CNTV_CVAL_EL0		sys_reg(3, 3, 14, 3, 2)
467 
468 #define SYS_AARCH32_CNTP_TVAL		sys_reg(0, 0, 14, 2, 0)
469 #define SYS_AARCH32_CNTP_CTL		sys_reg(0, 0, 14, 2, 1)
470 #define SYS_AARCH32_CNTPCT		sys_reg(0, 0, 0, 14, 0)
471 #define SYS_AARCH32_CNTP_CVAL		sys_reg(0, 2, 0, 14, 0)
472 #define SYS_AARCH32_CNTPCTSS		sys_reg(0, 8, 0, 14, 0)
473 
474 #define __PMEV_op2(n)			((n) & 0x7)
475 #define __CNTR_CRm(n)			(0x8 | (((n) >> 3) & 0x3))
476 #define SYS_PMEVCNTRn_EL0(n)		sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
477 #define __TYPER_CRm(n)			(0xc | (((n) >> 3) & 0x3))
478 #define SYS_PMEVTYPERn_EL0(n)		sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
479 
480 #define SYS_PMCCFILTR_EL0		sys_reg(3, 3, 14, 15, 7)
481 
482 #define SYS_VPIDR_EL2			sys_reg(3, 4, 0, 0, 0)
483 #define SYS_VMPIDR_EL2			sys_reg(3, 4, 0, 0, 5)
484 
485 #define SYS_SCTLR_EL2			sys_reg(3, 4, 1, 0, 0)
486 #define SYS_ACTLR_EL2			sys_reg(3, 4, 1, 0, 1)
487 #define SYS_HCR_EL2			sys_reg(3, 4, 1, 1, 0)
488 #define SYS_MDCR_EL2			sys_reg(3, 4, 1, 1, 1)
489 #define SYS_CPTR_EL2			sys_reg(3, 4, 1, 1, 2)
490 #define SYS_HSTR_EL2			sys_reg(3, 4, 1, 1, 3)
491 #define SYS_HACR_EL2			sys_reg(3, 4, 1, 1, 7)
492 
493 #define SYS_TTBR0_EL2			sys_reg(3, 4, 2, 0, 0)
494 #define SYS_TTBR1_EL2			sys_reg(3, 4, 2, 0, 1)
495 #define SYS_TCR_EL2			sys_reg(3, 4, 2, 0, 2)
496 #define SYS_VTTBR_EL2			sys_reg(3, 4, 2, 1, 0)
497 #define SYS_VTCR_EL2			sys_reg(3, 4, 2, 1, 2)
498 
499 #define SYS_TRFCR_EL2			sys_reg(3, 4, 1, 2, 1)
500 #define SYS_HAFGRTR_EL2			sys_reg(3, 4, 3, 1, 6)
501 #define SYS_SPSR_EL2			sys_reg(3, 4, 4, 0, 0)
502 #define SYS_ELR_EL2			sys_reg(3, 4, 4, 0, 1)
503 #define SYS_SP_EL1			sys_reg(3, 4, 4, 1, 0)
504 #define SYS_IFSR32_EL2			sys_reg(3, 4, 5, 0, 1)
505 #define SYS_AFSR0_EL2			sys_reg(3, 4, 5, 1, 0)
506 #define SYS_AFSR1_EL2			sys_reg(3, 4, 5, 1, 1)
507 #define SYS_ESR_EL2			sys_reg(3, 4, 5, 2, 0)
508 #define SYS_VSESR_EL2			sys_reg(3, 4, 5, 2, 3)
509 #define SYS_FPEXC32_EL2			sys_reg(3, 4, 5, 3, 0)
510 #define SYS_TFSR_EL2			sys_reg(3, 4, 5, 6, 0)
511 
512 #define SYS_FAR_EL2			sys_reg(3, 4, 6, 0, 0)
513 #define SYS_HPFAR_EL2			sys_reg(3, 4, 6, 0, 4)
514 
515 #define SYS_MAIR_EL2			sys_reg(3, 4, 10, 2, 0)
516 #define SYS_AMAIR_EL2			sys_reg(3, 4, 10, 3, 0)
517 
518 #define SYS_VBAR_EL2			sys_reg(3, 4, 12, 0, 0)
519 #define SYS_RVBAR_EL2			sys_reg(3, 4, 12, 0, 1)
520 #define SYS_RMR_EL2			sys_reg(3, 4, 12, 0, 2)
521 #define SYS_VDISR_EL2			sys_reg(3, 4, 12, 1, 1)
522 #define __SYS__AP0Rx_EL2(x)		sys_reg(3, 4, 12, 8, x)
523 #define SYS_ICH_AP0R0_EL2		__SYS__AP0Rx_EL2(0)
524 #define SYS_ICH_AP0R1_EL2		__SYS__AP0Rx_EL2(1)
525 #define SYS_ICH_AP0R2_EL2		__SYS__AP0Rx_EL2(2)
526 #define SYS_ICH_AP0R3_EL2		__SYS__AP0Rx_EL2(3)
527 
528 #define __SYS__AP1Rx_EL2(x)		sys_reg(3, 4, 12, 9, x)
529 #define SYS_ICH_AP1R0_EL2		__SYS__AP1Rx_EL2(0)
530 #define SYS_ICH_AP1R1_EL2		__SYS__AP1Rx_EL2(1)
531 #define SYS_ICH_AP1R2_EL2		__SYS__AP1Rx_EL2(2)
532 #define SYS_ICH_AP1R3_EL2		__SYS__AP1Rx_EL2(3)
533 
534 #define SYS_ICH_VSEIR_EL2		sys_reg(3, 4, 12, 9, 4)
535 #define SYS_ICC_SRE_EL2			sys_reg(3, 4, 12, 9, 5)
536 #define SYS_ICH_HCR_EL2			sys_reg(3, 4, 12, 11, 0)
537 #define SYS_ICH_VTR_EL2			sys_reg(3, 4, 12, 11, 1)
538 #define SYS_ICH_MISR_EL2		sys_reg(3, 4, 12, 11, 2)
539 #define SYS_ICH_EISR_EL2		sys_reg(3, 4, 12, 11, 3)
540 #define SYS_ICH_ELRSR_EL2		sys_reg(3, 4, 12, 11, 5)
541 #define SYS_ICH_VMCR_EL2		sys_reg(3, 4, 12, 11, 7)
542 
543 #define __SYS__LR0_EL2(x)		sys_reg(3, 4, 12, 12, x)
544 #define SYS_ICH_LR0_EL2			__SYS__LR0_EL2(0)
545 #define SYS_ICH_LR1_EL2			__SYS__LR0_EL2(1)
546 #define SYS_ICH_LR2_EL2			__SYS__LR0_EL2(2)
547 #define SYS_ICH_LR3_EL2			__SYS__LR0_EL2(3)
548 #define SYS_ICH_LR4_EL2			__SYS__LR0_EL2(4)
549 #define SYS_ICH_LR5_EL2			__SYS__LR0_EL2(5)
550 #define SYS_ICH_LR6_EL2			__SYS__LR0_EL2(6)
551 #define SYS_ICH_LR7_EL2			__SYS__LR0_EL2(7)
552 
553 #define __SYS__LR8_EL2(x)		sys_reg(3, 4, 12, 13, x)
554 #define SYS_ICH_LR8_EL2			__SYS__LR8_EL2(0)
555 #define SYS_ICH_LR9_EL2			__SYS__LR8_EL2(1)
556 #define SYS_ICH_LR10_EL2		__SYS__LR8_EL2(2)
557 #define SYS_ICH_LR11_EL2		__SYS__LR8_EL2(3)
558 #define SYS_ICH_LR12_EL2		__SYS__LR8_EL2(4)
559 #define SYS_ICH_LR13_EL2		__SYS__LR8_EL2(5)
560 #define SYS_ICH_LR14_EL2		__SYS__LR8_EL2(6)
561 #define SYS_ICH_LR15_EL2		__SYS__LR8_EL2(7)
562 
563 #define SYS_CONTEXTIDR_EL2		sys_reg(3, 4, 13, 0, 1)
564 #define SYS_TPIDR_EL2			sys_reg(3, 4, 13, 0, 2)
565 
566 #define SYS_CNTVOFF_EL2			sys_reg(3, 4, 14, 0, 3)
567 #define SYS_CNTHCTL_EL2			sys_reg(3, 4, 14, 1, 0)
568 
569 /* VHE encodings for architectural EL0/1 system registers */
570 #define SYS_SCTLR_EL12			sys_reg(3, 5, 1, 0, 0)
571 #define SYS_TTBR0_EL12			sys_reg(3, 5, 2, 0, 0)
572 #define SYS_TTBR1_EL12			sys_reg(3, 5, 2, 0, 1)
573 #define SYS_TCR_EL12			sys_reg(3, 5, 2, 0, 2)
574 #define SYS_SPSR_EL12			sys_reg(3, 5, 4, 0, 0)
575 #define SYS_ELR_EL12			sys_reg(3, 5, 4, 0, 1)
576 #define SYS_AFSR0_EL12			sys_reg(3, 5, 5, 1, 0)
577 #define SYS_AFSR1_EL12			sys_reg(3, 5, 5, 1, 1)
578 #define SYS_ESR_EL12			sys_reg(3, 5, 5, 2, 0)
579 #define SYS_TFSR_EL12			sys_reg(3, 5, 5, 6, 0)
580 #define SYS_MAIR_EL12			sys_reg(3, 5, 10, 2, 0)
581 #define SYS_AMAIR_EL12			sys_reg(3, 5, 10, 3, 0)
582 #define SYS_VBAR_EL12			sys_reg(3, 5, 12, 0, 0)
583 #define SYS_CNTKCTL_EL12		sys_reg(3, 5, 14, 1, 0)
584 #define SYS_CNTP_TVAL_EL02		sys_reg(3, 5, 14, 2, 0)
585 #define SYS_CNTP_CTL_EL02		sys_reg(3, 5, 14, 2, 1)
586 #define SYS_CNTP_CVAL_EL02		sys_reg(3, 5, 14, 2, 2)
587 #define SYS_CNTV_TVAL_EL02		sys_reg(3, 5, 14, 3, 0)
588 #define SYS_CNTV_CTL_EL02		sys_reg(3, 5, 14, 3, 1)
589 #define SYS_CNTV_CVAL_EL02		sys_reg(3, 5, 14, 3, 2)
590 
591 #define SYS_SP_EL2			sys_reg(3, 6,  4, 1, 0)
592 
593 /* AT instructions */
594 #define AT_Op0 1
595 #define AT_CRn 7
596 
597 #define OP_AT_S1E1R	sys_insn(AT_Op0, 0, AT_CRn, 8, 0)
598 #define OP_AT_S1E1W	sys_insn(AT_Op0, 0, AT_CRn, 8, 1)
599 #define OP_AT_S1E0R	sys_insn(AT_Op0, 0, AT_CRn, 8, 2)
600 #define OP_AT_S1E0W	sys_insn(AT_Op0, 0, AT_CRn, 8, 3)
601 #define OP_AT_S1E1RP	sys_insn(AT_Op0, 0, AT_CRn, 9, 0)
602 #define OP_AT_S1E1WP	sys_insn(AT_Op0, 0, AT_CRn, 9, 1)
603 #define OP_AT_S1E2R	sys_insn(AT_Op0, 4, AT_CRn, 8, 0)
604 #define OP_AT_S1E2W	sys_insn(AT_Op0, 4, AT_CRn, 8, 1)
605 #define OP_AT_S12E1R	sys_insn(AT_Op0, 4, AT_CRn, 8, 4)
606 #define OP_AT_S12E1W	sys_insn(AT_Op0, 4, AT_CRn, 8, 5)
607 #define OP_AT_S12E0R	sys_insn(AT_Op0, 4, AT_CRn, 8, 6)
608 #define OP_AT_S12E0W	sys_insn(AT_Op0, 4, AT_CRn, 8, 7)
609 
610 /* TLBI instructions */
611 #define OP_TLBI_VMALLE1OS		sys_insn(1, 0, 8, 1, 0)
612 #define OP_TLBI_VAE1OS			sys_insn(1, 0, 8, 1, 1)
613 #define OP_TLBI_ASIDE1OS		sys_insn(1, 0, 8, 1, 2)
614 #define OP_TLBI_VAAE1OS			sys_insn(1, 0, 8, 1, 3)
615 #define OP_TLBI_VALE1OS			sys_insn(1, 0, 8, 1, 5)
616 #define OP_TLBI_VAALE1OS		sys_insn(1, 0, 8, 1, 7)
617 #define OP_TLBI_RVAE1IS			sys_insn(1, 0, 8, 2, 1)
618 #define OP_TLBI_RVAAE1IS		sys_insn(1, 0, 8, 2, 3)
619 #define OP_TLBI_RVALE1IS		sys_insn(1, 0, 8, 2, 5)
620 #define OP_TLBI_RVAALE1IS		sys_insn(1, 0, 8, 2, 7)
621 #define OP_TLBI_VMALLE1IS		sys_insn(1, 0, 8, 3, 0)
622 #define OP_TLBI_VAE1IS			sys_insn(1, 0, 8, 3, 1)
623 #define OP_TLBI_ASIDE1IS		sys_insn(1, 0, 8, 3, 2)
624 #define OP_TLBI_VAAE1IS			sys_insn(1, 0, 8, 3, 3)
625 #define OP_TLBI_VALE1IS			sys_insn(1, 0, 8, 3, 5)
626 #define OP_TLBI_VAALE1IS		sys_insn(1, 0, 8, 3, 7)
627 #define OP_TLBI_RVAE1OS			sys_insn(1, 0, 8, 5, 1)
628 #define OP_TLBI_RVAAE1OS		sys_insn(1, 0, 8, 5, 3)
629 #define OP_TLBI_RVALE1OS		sys_insn(1, 0, 8, 5, 5)
630 #define OP_TLBI_RVAALE1OS		sys_insn(1, 0, 8, 5, 7)
631 #define OP_TLBI_RVAE1			sys_insn(1, 0, 8, 6, 1)
632 #define OP_TLBI_RVAAE1			sys_insn(1, 0, 8, 6, 3)
633 #define OP_TLBI_RVALE1			sys_insn(1, 0, 8, 6, 5)
634 #define OP_TLBI_RVAALE1			sys_insn(1, 0, 8, 6, 7)
635 #define OP_TLBI_VMALLE1			sys_insn(1, 0, 8, 7, 0)
636 #define OP_TLBI_VAE1			sys_insn(1, 0, 8, 7, 1)
637 #define OP_TLBI_ASIDE1			sys_insn(1, 0, 8, 7, 2)
638 #define OP_TLBI_VAAE1			sys_insn(1, 0, 8, 7, 3)
639 #define OP_TLBI_VALE1			sys_insn(1, 0, 8, 7, 5)
640 #define OP_TLBI_VAALE1			sys_insn(1, 0, 8, 7, 7)
641 #define OP_TLBI_VMALLE1OSNXS		sys_insn(1, 0, 9, 1, 0)
642 #define OP_TLBI_VAE1OSNXS		sys_insn(1, 0, 9, 1, 1)
643 #define OP_TLBI_ASIDE1OSNXS		sys_insn(1, 0, 9, 1, 2)
644 #define OP_TLBI_VAAE1OSNXS		sys_insn(1, 0, 9, 1, 3)
645 #define OP_TLBI_VALE1OSNXS		sys_insn(1, 0, 9, 1, 5)
646 #define OP_TLBI_VAALE1OSNXS		sys_insn(1, 0, 9, 1, 7)
647 #define OP_TLBI_RVAE1ISNXS		sys_insn(1, 0, 9, 2, 1)
648 #define OP_TLBI_RVAAE1ISNXS		sys_insn(1, 0, 9, 2, 3)
649 #define OP_TLBI_RVALE1ISNXS		sys_insn(1, 0, 9, 2, 5)
650 #define OP_TLBI_RVAALE1ISNXS		sys_insn(1, 0, 9, 2, 7)
651 #define OP_TLBI_VMALLE1ISNXS		sys_insn(1, 0, 9, 3, 0)
652 #define OP_TLBI_VAE1ISNXS		sys_insn(1, 0, 9, 3, 1)
653 #define OP_TLBI_ASIDE1ISNXS		sys_insn(1, 0, 9, 3, 2)
654 #define OP_TLBI_VAAE1ISNXS		sys_insn(1, 0, 9, 3, 3)
655 #define OP_TLBI_VALE1ISNXS		sys_insn(1, 0, 9, 3, 5)
656 #define OP_TLBI_VAALE1ISNXS		sys_insn(1, 0, 9, 3, 7)
657 #define OP_TLBI_RVAE1OSNXS		sys_insn(1, 0, 9, 5, 1)
658 #define OP_TLBI_RVAAE1OSNXS		sys_insn(1, 0, 9, 5, 3)
659 #define OP_TLBI_RVALE1OSNXS		sys_insn(1, 0, 9, 5, 5)
660 #define OP_TLBI_RVAALE1OSNXS		sys_insn(1, 0, 9, 5, 7)
661 #define OP_TLBI_RVAE1NXS		sys_insn(1, 0, 9, 6, 1)
662 #define OP_TLBI_RVAAE1NXS		sys_insn(1, 0, 9, 6, 3)
663 #define OP_TLBI_RVALE1NXS		sys_insn(1, 0, 9, 6, 5)
664 #define OP_TLBI_RVAALE1NXS		sys_insn(1, 0, 9, 6, 7)
665 #define OP_TLBI_VMALLE1NXS		sys_insn(1, 0, 9, 7, 0)
666 #define OP_TLBI_VAE1NXS			sys_insn(1, 0, 9, 7, 1)
667 #define OP_TLBI_ASIDE1NXS		sys_insn(1, 0, 9, 7, 2)
668 #define OP_TLBI_VAAE1NXS		sys_insn(1, 0, 9, 7, 3)
669 #define OP_TLBI_VALE1NXS		sys_insn(1, 0, 9, 7, 5)
670 #define OP_TLBI_VAALE1NXS		sys_insn(1, 0, 9, 7, 7)
671 #define OP_TLBI_IPAS2E1IS		sys_insn(1, 4, 8, 0, 1)
672 #define OP_TLBI_RIPAS2E1IS		sys_insn(1, 4, 8, 0, 2)
673 #define OP_TLBI_IPAS2LE1IS		sys_insn(1, 4, 8, 0, 5)
674 #define OP_TLBI_RIPAS2LE1IS		sys_insn(1, 4, 8, 0, 6)
675 #define OP_TLBI_ALLE2OS			sys_insn(1, 4, 8, 1, 0)
676 #define OP_TLBI_VAE2OS			sys_insn(1, 4, 8, 1, 1)
677 #define OP_TLBI_ALLE1OS			sys_insn(1, 4, 8, 1, 4)
678 #define OP_TLBI_VALE2OS			sys_insn(1, 4, 8, 1, 5)
679 #define OP_TLBI_VMALLS12E1OS		sys_insn(1, 4, 8, 1, 6)
680 #define OP_TLBI_RVAE2IS			sys_insn(1, 4, 8, 2, 1)
681 #define OP_TLBI_RVALE2IS		sys_insn(1, 4, 8, 2, 5)
682 #define OP_TLBI_ALLE2IS			sys_insn(1, 4, 8, 3, 0)
683 #define OP_TLBI_VAE2IS			sys_insn(1, 4, 8, 3, 1)
684 #define OP_TLBI_ALLE1IS			sys_insn(1, 4, 8, 3, 4)
685 #define OP_TLBI_VALE2IS			sys_insn(1, 4, 8, 3, 5)
686 #define OP_TLBI_VMALLS12E1IS		sys_insn(1, 4, 8, 3, 6)
687 #define OP_TLBI_IPAS2E1OS		sys_insn(1, 4, 8, 4, 0)
688 #define OP_TLBI_IPAS2E1			sys_insn(1, 4, 8, 4, 1)
689 #define OP_TLBI_RIPAS2E1		sys_insn(1, 4, 8, 4, 2)
690 #define OP_TLBI_RIPAS2E1OS		sys_insn(1, 4, 8, 4, 3)
691 #define OP_TLBI_IPAS2LE1OS		sys_insn(1, 4, 8, 4, 4)
692 #define OP_TLBI_IPAS2LE1		sys_insn(1, 4, 8, 4, 5)
693 #define OP_TLBI_RIPAS2LE1		sys_insn(1, 4, 8, 4, 6)
694 #define OP_TLBI_RIPAS2LE1OS		sys_insn(1, 4, 8, 4, 7)
695 #define OP_TLBI_RVAE2OS			sys_insn(1, 4, 8, 5, 1)
696 #define OP_TLBI_RVALE2OS		sys_insn(1, 4, 8, 5, 5)
697 #define OP_TLBI_RVAE2			sys_insn(1, 4, 8, 6, 1)
698 #define OP_TLBI_RVALE2			sys_insn(1, 4, 8, 6, 5)
699 #define OP_TLBI_ALLE2			sys_insn(1, 4, 8, 7, 0)
700 #define OP_TLBI_VAE2			sys_insn(1, 4, 8, 7, 1)
701 #define OP_TLBI_ALLE1			sys_insn(1, 4, 8, 7, 4)
702 #define OP_TLBI_VALE2			sys_insn(1, 4, 8, 7, 5)
703 #define OP_TLBI_VMALLS12E1		sys_insn(1, 4, 8, 7, 6)
704 #define OP_TLBI_IPAS2E1ISNXS		sys_insn(1, 4, 9, 0, 1)
705 #define OP_TLBI_RIPAS2E1ISNXS		sys_insn(1, 4, 9, 0, 2)
706 #define OP_TLBI_IPAS2LE1ISNXS		sys_insn(1, 4, 9, 0, 5)
707 #define OP_TLBI_RIPAS2LE1ISNXS		sys_insn(1, 4, 9, 0, 6)
708 #define OP_TLBI_ALLE2OSNXS		sys_insn(1, 4, 9, 1, 0)
709 #define OP_TLBI_VAE2OSNXS		sys_insn(1, 4, 9, 1, 1)
710 #define OP_TLBI_ALLE1OSNXS		sys_insn(1, 4, 9, 1, 4)
711 #define OP_TLBI_VALE2OSNXS		sys_insn(1, 4, 9, 1, 5)
712 #define OP_TLBI_VMALLS12E1OSNXS		sys_insn(1, 4, 9, 1, 6)
713 #define OP_TLBI_RVAE2ISNXS		sys_insn(1, 4, 9, 2, 1)
714 #define OP_TLBI_RVALE2ISNXS		sys_insn(1, 4, 9, 2, 5)
715 #define OP_TLBI_ALLE2ISNXS		sys_insn(1, 4, 9, 3, 0)
716 #define OP_TLBI_VAE2ISNXS		sys_insn(1, 4, 9, 3, 1)
717 #define OP_TLBI_ALLE1ISNXS		sys_insn(1, 4, 9, 3, 4)
718 #define OP_TLBI_VALE2ISNXS		sys_insn(1, 4, 9, 3, 5)
719 #define OP_TLBI_VMALLS12E1ISNXS		sys_insn(1, 4, 9, 3, 6)
720 #define OP_TLBI_IPAS2E1OSNXS		sys_insn(1, 4, 9, 4, 0)
721 #define OP_TLBI_IPAS2E1NXS		sys_insn(1, 4, 9, 4, 1)
722 #define OP_TLBI_RIPAS2E1NXS		sys_insn(1, 4, 9, 4, 2)
723 #define OP_TLBI_RIPAS2E1OSNXS		sys_insn(1, 4, 9, 4, 3)
724 #define OP_TLBI_IPAS2LE1OSNXS		sys_insn(1, 4, 9, 4, 4)
725 #define OP_TLBI_IPAS2LE1NXS		sys_insn(1, 4, 9, 4, 5)
726 #define OP_TLBI_RIPAS2LE1NXS		sys_insn(1, 4, 9, 4, 6)
727 #define OP_TLBI_RIPAS2LE1OSNXS		sys_insn(1, 4, 9, 4, 7)
728 #define OP_TLBI_RVAE2OSNXS		sys_insn(1, 4, 9, 5, 1)
729 #define OP_TLBI_RVALE2OSNXS		sys_insn(1, 4, 9, 5, 5)
730 #define OP_TLBI_RVAE2NXS		sys_insn(1, 4, 9, 6, 1)
731 #define OP_TLBI_RVALE2NXS		sys_insn(1, 4, 9, 6, 5)
732 #define OP_TLBI_ALLE2NXS		sys_insn(1, 4, 9, 7, 0)
733 #define OP_TLBI_VAE2NXS			sys_insn(1, 4, 9, 7, 1)
734 #define OP_TLBI_ALLE1NXS		sys_insn(1, 4, 9, 7, 4)
735 #define OP_TLBI_VALE2NXS		sys_insn(1, 4, 9, 7, 5)
736 #define OP_TLBI_VMALLS12E1NXS		sys_insn(1, 4, 9, 7, 6)
737 
738 /* Misc instructions */
739 #define OP_BRB_IALL			sys_insn(1, 1, 7, 2, 4)
740 #define OP_BRB_INJ			sys_insn(1, 1, 7, 2, 5)
741 #define OP_CFP_RCTX			sys_insn(1, 3, 7, 3, 4)
742 #define OP_DVP_RCTX			sys_insn(1, 3, 7, 3, 5)
743 #define OP_CPP_RCTX			sys_insn(1, 3, 7, 3, 7)
744 
745 /* Common SCTLR_ELx flags. */
746 #define SCTLR_ELx_ENTP2	(BIT(60))
747 #define SCTLR_ELx_DSSBS	(BIT(44))
748 #define SCTLR_ELx_ATA	(BIT(43))
749 
750 #define SCTLR_ELx_EE_SHIFT	25
751 #define SCTLR_ELx_ENIA_SHIFT	31
752 
753 #define SCTLR_ELx_ITFSB	 (BIT(37))
754 #define SCTLR_ELx_ENIA	 (BIT(SCTLR_ELx_ENIA_SHIFT))
755 #define SCTLR_ELx_ENIB	 (BIT(30))
756 #define SCTLR_ELx_LSMAOE (BIT(29))
757 #define SCTLR_ELx_nTLSMD (BIT(28))
758 #define SCTLR_ELx_ENDA	 (BIT(27))
759 #define SCTLR_ELx_EE     (BIT(SCTLR_ELx_EE_SHIFT))
760 #define SCTLR_ELx_EIS	 (BIT(22))
761 #define SCTLR_ELx_IESB	 (BIT(21))
762 #define SCTLR_ELx_TSCXT	 (BIT(20))
763 #define SCTLR_ELx_WXN	 (BIT(19))
764 #define SCTLR_ELx_ENDB	 (BIT(13))
765 #define SCTLR_ELx_I	 (BIT(12))
766 #define SCTLR_ELx_EOS	 (BIT(11))
767 #define SCTLR_ELx_SA	 (BIT(3))
768 #define SCTLR_ELx_C	 (BIT(2))
769 #define SCTLR_ELx_A	 (BIT(1))
770 #define SCTLR_ELx_M	 (BIT(0))
771 
772 /* SCTLR_EL2 specific flags. */
773 #define SCTLR_EL2_RES1	((BIT(4))  | (BIT(5))  | (BIT(11)) | (BIT(16)) | \
774 			 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
775 			 (BIT(29)))
776 
777 #define SCTLR_EL2_BT	(BIT(36))
778 #ifdef CONFIG_CPU_BIG_ENDIAN
779 #define ENDIAN_SET_EL2		SCTLR_ELx_EE
780 #else
781 #define ENDIAN_SET_EL2		0
782 #endif
783 
784 #define INIT_SCTLR_EL2_MMU_ON						\
785 	(SCTLR_ELx_M  | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_ELx_I |	\
786 	 SCTLR_ELx_IESB | SCTLR_ELx_WXN | ENDIAN_SET_EL2 |		\
787 	 SCTLR_ELx_ITFSB | SCTLR_EL2_RES1)
788 
789 #define INIT_SCTLR_EL2_MMU_OFF \
790 	(SCTLR_EL2_RES1 | ENDIAN_SET_EL2)
791 
792 /* SCTLR_EL1 specific flags. */
793 #ifdef CONFIG_CPU_BIG_ENDIAN
794 #define ENDIAN_SET_EL1		(SCTLR_EL1_E0E | SCTLR_ELx_EE)
795 #else
796 #define ENDIAN_SET_EL1		0
797 #endif
798 
799 #define INIT_SCTLR_EL1_MMU_OFF \
800 	(ENDIAN_SET_EL1 | SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | \
801 	 SCTLR_EL1_EIS  | SCTLR_EL1_TSCXT  | SCTLR_EL1_EOS)
802 
803 #define INIT_SCTLR_EL1_MMU_ON \
804 	(SCTLR_ELx_M      | SCTLR_ELx_C      | SCTLR_ELx_SA    | \
805 	 SCTLR_EL1_SA0    | SCTLR_EL1_SED    | SCTLR_ELx_I     | \
806 	 SCTLR_EL1_DZE    | SCTLR_EL1_UCT    | SCTLR_EL1_nTWE  | \
807 	 SCTLR_ELx_IESB   | SCTLR_EL1_SPAN   | SCTLR_ELx_ITFSB | \
808 	 ENDIAN_SET_EL1   | SCTLR_EL1_UCI    | SCTLR_EL1_EPAN  | \
809 	 SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS   | \
810 	 SCTLR_EL1_TSCXT  | SCTLR_EL1_EOS)
811 
812 /* MAIR_ELx memory attributes (used by Linux) */
813 #define MAIR_ATTR_DEVICE_nGnRnE		UL(0x00)
814 #define MAIR_ATTR_DEVICE_nGnRE		UL(0x04)
815 #define MAIR_ATTR_NORMAL_NC		UL(0x44)
816 #define MAIR_ATTR_NORMAL_TAGGED		UL(0xf0)
817 #define MAIR_ATTR_NORMAL		UL(0xff)
818 #define MAIR_ATTR_MASK			UL(0xff)
819 
820 /* Position the attr at the correct index */
821 #define MAIR_ATTRIDX(attr, idx)		((attr) << ((idx) * 8))
822 
823 /* id_aa64pfr0 */
824 #define ID_AA64PFR0_EL1_ELx_64BIT_ONLY		0x1
825 #define ID_AA64PFR0_EL1_ELx_32BIT_64BIT		0x2
826 
827 /* id_aa64mmfr0 */
828 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN	0x0
829 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX	0x7
830 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN	0x0
831 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX	0x7
832 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN	0x1
833 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX	0xf
834 
835 #define ARM64_MIN_PARANGE_BITS		32
836 
837 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT	0x0
838 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE		0x1
839 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN		0x2
840 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX		0x7
841 
842 #ifdef CONFIG_ARM64_PA_BITS_52
843 #define ID_AA64MMFR0_EL1_PARANGE_MAX	ID_AA64MMFR0_EL1_PARANGE_52
844 #else
845 #define ID_AA64MMFR0_EL1_PARANGE_MAX	ID_AA64MMFR0_EL1_PARANGE_48
846 #endif
847 
848 #if defined(CONFIG_ARM64_4K_PAGES)
849 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN4_SHIFT
850 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN
851 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX
852 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT
853 #elif defined(CONFIG_ARM64_16K_PAGES)
854 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN16_SHIFT
855 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN
856 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX
857 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT
858 #elif defined(CONFIG_ARM64_64K_PAGES)
859 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN64_SHIFT
860 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN
861 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX
862 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT
863 #endif
864 
865 #define CPACR_EL1_FPEN_EL1EN	(BIT(20)) /* enable EL1 access */
866 #define CPACR_EL1_FPEN_EL0EN	(BIT(21)) /* enable EL0 access, if EL1EN set */
867 
868 #define CPACR_EL1_SMEN_EL1EN	(BIT(24)) /* enable EL1 access */
869 #define CPACR_EL1_SMEN_EL0EN	(BIT(25)) /* enable EL0 access, if EL1EN set */
870 
871 #define CPACR_EL1_ZEN_EL1EN	(BIT(16)) /* enable EL1 access */
872 #define CPACR_EL1_ZEN_EL0EN	(BIT(17)) /* enable EL0 access, if EL1EN set */
873 
874 /* GCR_EL1 Definitions */
875 #define SYS_GCR_EL1_RRND	(BIT(16))
876 #define SYS_GCR_EL1_EXCL_MASK	0xffffUL
877 
878 #ifdef CONFIG_KASAN_HW_TAGS
879 /*
880  * KASAN always uses a whole byte for its tags. With CONFIG_KASAN_HW_TAGS it
881  * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
882  */
883 #define __MTE_TAG_MIN		(KASAN_TAG_MIN & 0xf)
884 #define __MTE_TAG_MAX		(KASAN_TAG_MAX & 0xf)
885 #define __MTE_TAG_INCL		GENMASK(__MTE_TAG_MAX, __MTE_TAG_MIN)
886 #define KERNEL_GCR_EL1_EXCL	(SYS_GCR_EL1_EXCL_MASK & ~__MTE_TAG_INCL)
887 #else
888 #define KERNEL_GCR_EL1_EXCL	SYS_GCR_EL1_EXCL_MASK
889 #endif
890 
891 #define KERNEL_GCR_EL1		(SYS_GCR_EL1_RRND | KERNEL_GCR_EL1_EXCL)
892 
893 /* RGSR_EL1 Definitions */
894 #define SYS_RGSR_EL1_TAG_MASK	0xfUL
895 #define SYS_RGSR_EL1_SEED_SHIFT	8
896 #define SYS_RGSR_EL1_SEED_MASK	0xffffUL
897 
898 /* TFSR{,E0}_EL1 bit definitions */
899 #define SYS_TFSR_EL1_TF0_SHIFT	0
900 #define SYS_TFSR_EL1_TF1_SHIFT	1
901 #define SYS_TFSR_EL1_TF0	(UL(1) << SYS_TFSR_EL1_TF0_SHIFT)
902 #define SYS_TFSR_EL1_TF1	(UL(1) << SYS_TFSR_EL1_TF1_SHIFT)
903 
904 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
905 #define SYS_MPIDR_SAFE_VAL	(BIT(31))
906 
907 #define TRFCR_ELx_TS_SHIFT		5
908 #define TRFCR_ELx_TS_MASK		((0x3UL) << TRFCR_ELx_TS_SHIFT)
909 #define TRFCR_ELx_TS_VIRTUAL		((0x1UL) << TRFCR_ELx_TS_SHIFT)
910 #define TRFCR_ELx_TS_GUEST_PHYSICAL	((0x2UL) << TRFCR_ELx_TS_SHIFT)
911 #define TRFCR_ELx_TS_PHYSICAL		((0x3UL) << TRFCR_ELx_TS_SHIFT)
912 #define TRFCR_EL2_CX			BIT(3)
913 #define TRFCR_ELx_ExTRE			BIT(1)
914 #define TRFCR_ELx_E0TRE			BIT(0)
915 
916 /* GIC Hypervisor interface registers */
917 /* ICH_MISR_EL2 bit definitions */
918 #define ICH_MISR_EOI		(1 << 0)
919 #define ICH_MISR_U		(1 << 1)
920 
921 /* ICH_LR*_EL2 bit definitions */
922 #define ICH_LR_VIRTUAL_ID_MASK	((1ULL << 32) - 1)
923 
924 #define ICH_LR_EOI		(1ULL << 41)
925 #define ICH_LR_GROUP		(1ULL << 60)
926 #define ICH_LR_HW		(1ULL << 61)
927 #define ICH_LR_STATE		(3ULL << 62)
928 #define ICH_LR_PENDING_BIT	(1ULL << 62)
929 #define ICH_LR_ACTIVE_BIT	(1ULL << 63)
930 #define ICH_LR_PHYS_ID_SHIFT	32
931 #define ICH_LR_PHYS_ID_MASK	(0x3ffULL << ICH_LR_PHYS_ID_SHIFT)
932 #define ICH_LR_PRIORITY_SHIFT	48
933 #define ICH_LR_PRIORITY_MASK	(0xffULL << ICH_LR_PRIORITY_SHIFT)
934 
935 /* ICH_HCR_EL2 bit definitions */
936 #define ICH_HCR_EN		(1 << 0)
937 #define ICH_HCR_UIE		(1 << 1)
938 #define ICH_HCR_NPIE		(1 << 3)
939 #define ICH_HCR_TC		(1 << 10)
940 #define ICH_HCR_TALL0		(1 << 11)
941 #define ICH_HCR_TALL1		(1 << 12)
942 #define ICH_HCR_TDIR		(1 << 14)
943 #define ICH_HCR_EOIcount_SHIFT	27
944 #define ICH_HCR_EOIcount_MASK	(0x1f << ICH_HCR_EOIcount_SHIFT)
945 
946 /* ICH_VMCR_EL2 bit definitions */
947 #define ICH_VMCR_ACK_CTL_SHIFT	2
948 #define ICH_VMCR_ACK_CTL_MASK	(1 << ICH_VMCR_ACK_CTL_SHIFT)
949 #define ICH_VMCR_FIQ_EN_SHIFT	3
950 #define ICH_VMCR_FIQ_EN_MASK	(1 << ICH_VMCR_FIQ_EN_SHIFT)
951 #define ICH_VMCR_CBPR_SHIFT	4
952 #define ICH_VMCR_CBPR_MASK	(1 << ICH_VMCR_CBPR_SHIFT)
953 #define ICH_VMCR_EOIM_SHIFT	9
954 #define ICH_VMCR_EOIM_MASK	(1 << ICH_VMCR_EOIM_SHIFT)
955 #define ICH_VMCR_BPR1_SHIFT	18
956 #define ICH_VMCR_BPR1_MASK	(7 << ICH_VMCR_BPR1_SHIFT)
957 #define ICH_VMCR_BPR0_SHIFT	21
958 #define ICH_VMCR_BPR0_MASK	(7 << ICH_VMCR_BPR0_SHIFT)
959 #define ICH_VMCR_PMR_SHIFT	24
960 #define ICH_VMCR_PMR_MASK	(0xffUL << ICH_VMCR_PMR_SHIFT)
961 #define ICH_VMCR_ENG0_SHIFT	0
962 #define ICH_VMCR_ENG0_MASK	(1 << ICH_VMCR_ENG0_SHIFT)
963 #define ICH_VMCR_ENG1_SHIFT	1
964 #define ICH_VMCR_ENG1_MASK	(1 << ICH_VMCR_ENG1_SHIFT)
965 
966 /* ICH_VTR_EL2 bit definitions */
967 #define ICH_VTR_PRI_BITS_SHIFT	29
968 #define ICH_VTR_PRI_BITS_MASK	(7 << ICH_VTR_PRI_BITS_SHIFT)
969 #define ICH_VTR_ID_BITS_SHIFT	23
970 #define ICH_VTR_ID_BITS_MASK	(7 << ICH_VTR_ID_BITS_SHIFT)
971 #define ICH_VTR_SEIS_SHIFT	22
972 #define ICH_VTR_SEIS_MASK	(1 << ICH_VTR_SEIS_SHIFT)
973 #define ICH_VTR_A3V_SHIFT	21
974 #define ICH_VTR_A3V_MASK	(1 << ICH_VTR_A3V_SHIFT)
975 #define ICH_VTR_TDS_SHIFT	19
976 #define ICH_VTR_TDS_MASK	(1 << ICH_VTR_TDS_SHIFT)
977 
978 /*
979  * Permission Indirection Extension (PIE) permission encodings.
980  * Encodings with the _O suffix, have overlays applied (Permission Overlay Extension).
981  */
982 #define PIE_NONE_O	0x0
983 #define PIE_R_O		0x1
984 #define PIE_X_O		0x2
985 #define PIE_RX_O	0x3
986 #define PIE_RW_O	0x5
987 #define PIE_RWnX_O	0x6
988 #define PIE_RWX_O	0x7
989 #define PIE_R		0x8
990 #define PIE_GCS		0x9
991 #define PIE_RX		0xa
992 #define PIE_RW		0xc
993 #define PIE_RWX		0xe
994 
995 #define PIRx_ELx_PERM(idx, perm)	((perm) << ((idx) * 4))
996 
997 #define ARM64_FEATURE_FIELD_BITS	4
998 
999 /* Defined for compatibility only, do not add new users. */
1000 #define ARM64_FEATURE_MASK(x)	(x##_MASK)
1001 
1002 #ifdef __ASSEMBLY__
1003 
1004 	.macro	mrs_s, rt, sreg
1005 	 __emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt))
1006 	.endm
1007 
1008 	.macro	msr_s, sreg, rt
1009 	__emit_inst(0xd5000000|(\sreg)|(.L__gpr_num_\rt))
1010 	.endm
1011 
1012 #else
1013 
1014 #include <linux/bitfield.h>
1015 #include <linux/build_bug.h>
1016 #include <linux/types.h>
1017 #include <asm/alternative.h>
1018 
1019 #define DEFINE_MRS_S						\
1020 	__DEFINE_ASM_GPR_NUMS					\
1021 "	.macro	mrs_s, rt, sreg\n"				\
1022 	__emit_inst(0xd5200000|(\\sreg)|(.L__gpr_num_\\rt))	\
1023 "	.endm\n"
1024 
1025 #define DEFINE_MSR_S						\
1026 	__DEFINE_ASM_GPR_NUMS					\
1027 "	.macro	msr_s, sreg, rt\n"				\
1028 	__emit_inst(0xd5000000|(\\sreg)|(.L__gpr_num_\\rt))	\
1029 "	.endm\n"
1030 
1031 #define UNDEFINE_MRS_S						\
1032 "	.purgem	mrs_s\n"
1033 
1034 #define UNDEFINE_MSR_S						\
1035 "	.purgem	msr_s\n"
1036 
1037 #define __mrs_s(v, r)						\
1038 	DEFINE_MRS_S						\
1039 "	mrs_s " v ", " __stringify(r) "\n"			\
1040 	UNDEFINE_MRS_S
1041 
1042 #define __msr_s(r, v)						\
1043 	DEFINE_MSR_S						\
1044 "	msr_s " __stringify(r) ", " v "\n"			\
1045 	UNDEFINE_MSR_S
1046 
1047 /*
1048  * Unlike read_cpuid, calls to read_sysreg are never expected to be
1049  * optimized away or replaced with synthetic values.
1050  */
1051 #define read_sysreg(r) ({					\
1052 	u64 __val;						\
1053 	asm volatile("mrs %0, " __stringify(r) : "=r" (__val));	\
1054 	__val;							\
1055 })
1056 
1057 /*
1058  * The "Z" constraint normally means a zero immediate, but when combined with
1059  * the "%x0" template means XZR.
1060  */
1061 #define write_sysreg(v, r) do {					\
1062 	u64 __val = (u64)(v);					\
1063 	asm volatile("msr " __stringify(r) ", %x0"		\
1064 		     : : "rZ" (__val));				\
1065 } while (0)
1066 
1067 /*
1068  * For registers without architectural names, or simply unsupported by
1069  * GAS.
1070  *
1071  * __check_r forces warnings to be generated by the compiler when
1072  * evaluating r which wouldn't normally happen due to being passed to
1073  * the assembler via __stringify(r).
1074  */
1075 #define read_sysreg_s(r) ({						\
1076 	u64 __val;							\
1077 	u32 __maybe_unused __check_r = (u32)(r);			\
1078 	asm volatile(__mrs_s("%0", r) : "=r" (__val));			\
1079 	__val;								\
1080 })
1081 
1082 #define write_sysreg_s(v, r) do {					\
1083 	u64 __val = (u64)(v);						\
1084 	u32 __maybe_unused __check_r = (u32)(r);			\
1085 	asm volatile(__msr_s(r, "%x0") : : "rZ" (__val));		\
1086 } while (0)
1087 
1088 /*
1089  * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the
1090  * set mask are set. Other bits are left as-is.
1091  */
1092 #define sysreg_clear_set(sysreg, clear, set) do {			\
1093 	u64 __scs_val = read_sysreg(sysreg);				\
1094 	u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set);		\
1095 	if (__scs_new != __scs_val)					\
1096 		write_sysreg(__scs_new, sysreg);			\
1097 } while (0)
1098 
1099 #define sysreg_clear_set_s(sysreg, clear, set) do {			\
1100 	u64 __scs_val = read_sysreg_s(sysreg);				\
1101 	u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set);		\
1102 	if (__scs_new != __scs_val)					\
1103 		write_sysreg_s(__scs_new, sysreg);			\
1104 } while (0)
1105 
1106 #define read_sysreg_par() ({						\
1107 	u64 par;							\
1108 	asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412));	\
1109 	par = read_sysreg(par_el1);					\
1110 	asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412));	\
1111 	par;								\
1112 })
1113 
1114 #define SYS_FIELD_GET(reg, field, val)		\
1115 		 FIELD_GET(reg##_##field##_MASK, val)
1116 
1117 #define SYS_FIELD_PREP(reg, field, val)		\
1118 		 FIELD_PREP(reg##_##field##_MASK, val)
1119 
1120 #define SYS_FIELD_PREP_ENUM(reg, field, val)		\
1121 		 FIELD_PREP(reg##_##field##_MASK, reg##_##field##_##val)
1122 
1123 #endif
1124 
1125 #endif	/* __ASM_SYSREG_H */
1126