1 #ifndef __MACH_MOTHERBOARD_H 2 #define __MACH_MOTHERBOARD_H 3 4 /* 5 * Physical addresses, offset from V2M_PA_CS0-3 6 */ 7 #define V2M_NOR0 (V2M_PA_CS0) 8 #define V2M_NOR1 (V2M_PA_CS1) 9 #define V2M_SRAM (V2M_PA_CS2) 10 #define V2M_VIDEO_SRAM (V2M_PA_CS3 + 0x00000000) 11 #define V2M_LAN9118 (V2M_PA_CS3 + 0x02000000) 12 #define V2M_ISP1761 (V2M_PA_CS3 + 0x03000000) 13 14 /* 15 * Physical addresses, offset from V2M_PA_CS7 16 */ 17 #define V2M_SYSREGS (V2M_PA_CS7 + 0x00000000) 18 #define V2M_SYSCTL (V2M_PA_CS7 + 0x00001000) 19 #define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + 0x00002000) 20 21 #define V2M_AACI (V2M_PA_CS7 + 0x00004000) 22 #define V2M_MMCI (V2M_PA_CS7 + 0x00005000) 23 #define V2M_KMI0 (V2M_PA_CS7 + 0x00006000) 24 #define V2M_KMI1 (V2M_PA_CS7 + 0x00007000) 25 26 #define V2M_UART0 (V2M_PA_CS7 + 0x00009000) 27 #define V2M_UART1 (V2M_PA_CS7 + 0x0000a000) 28 #define V2M_UART2 (V2M_PA_CS7 + 0x0000b000) 29 #define V2M_UART3 (V2M_PA_CS7 + 0x0000c000) 30 31 #define V2M_WDT (V2M_PA_CS7 + 0x0000f000) 32 33 #define V2M_TIMER01 (V2M_PA_CS7 + 0x00011000) 34 #define V2M_TIMER23 (V2M_PA_CS7 + 0x00012000) 35 36 #define V2M_SERIAL_BUS_DVI (V2M_PA_CS7 + 0x00016000) 37 #define V2M_RTC (V2M_PA_CS7 + 0x00017000) 38 39 #define V2M_CF (V2M_PA_CS7 + 0x0001a000) 40 #define V2M_CLCD (V2M_PA_CS7 + 0x0001f000) 41 42 /* 43 * Offsets from SYSREGS base 44 */ 45 #define V2M_SYS_ID 0x000 46 #define V2M_SYS_SW 0x004 47 #define V2M_SYS_LED 0x008 48 #define V2M_SYS_100HZ 0x024 49 #define V2M_SYS_FLAGS 0x030 50 #define V2M_SYS_FLAGSSET 0x030 51 #define V2M_SYS_FLAGSCLR 0x034 52 #define V2M_SYS_NVFLAGS 0x038 53 #define V2M_SYS_NVFLAGSSET 0x038 54 #define V2M_SYS_NVFLAGSCLR 0x03c 55 #define V2M_SYS_MCI 0x048 56 #define V2M_SYS_FLASH 0x03c 57 #define V2M_SYS_CFGSW 0x058 58 #define V2M_SYS_24MHZ 0x05c 59 #define V2M_SYS_MISC 0x060 60 #define V2M_SYS_DMA 0x064 61 #define V2M_SYS_PROCID0 0x084 62 #define V2M_SYS_PROCID1 0x088 63 #define V2M_SYS_CFGDATA 0x0a0 64 #define V2M_SYS_CFGCTRL 0x0a4 65 #define V2M_SYS_CFGSTAT 0x0a8 66 67 68 /* 69 * Interrupts. Those in {} are for AMBA devices 70 */ 71 #define IRQ_V2M_WDT { (32 + 0) } 72 #define IRQ_V2M_TIMER0 (32 + 2) 73 #define IRQ_V2M_TIMER1 (32 + 2) 74 #define IRQ_V2M_TIMER2 (32 + 3) 75 #define IRQ_V2M_TIMER3 (32 + 3) 76 #define IRQ_V2M_RTC { (32 + 4) } 77 #define IRQ_V2M_UART0 { (32 + 5) } 78 #define IRQ_V2M_UART1 { (32 + 6) } 79 #define IRQ_V2M_UART2 { (32 + 7) } 80 #define IRQ_V2M_UART3 { (32 + 8) } 81 #define IRQ_V2M_MMCI { (32 + 9), (32 + 10) } 82 #define IRQ_V2M_AACI { (32 + 11) } 83 #define IRQ_V2M_KMI0 { (32 + 12) } 84 #define IRQ_V2M_KMI1 { (32 + 13) } 85 #define IRQ_V2M_CLCD { (32 + 14) } 86 #define IRQ_V2M_LAN9118 (32 + 15) 87 #define IRQ_V2M_ISP1761 (32 + 16) 88 #define IRQ_V2M_PCIE (32 + 17) 89 90 91 /* 92 * Configuration 93 */ 94 #define SYS_CFG_START (1 << 31) 95 #define SYS_CFG_WRITE (1 << 30) 96 #define SYS_CFG_OSC (1 << 20) 97 #define SYS_CFG_VOLT (2 << 20) 98 #define SYS_CFG_AMP (3 << 20) 99 #define SYS_CFG_TEMP (4 << 20) 100 #define SYS_CFG_RESET (5 << 20) 101 #define SYS_CFG_SCC (6 << 20) 102 #define SYS_CFG_MUXFPGA (7 << 20) 103 #define SYS_CFG_SHUTDOWN (8 << 20) 104 #define SYS_CFG_REBOOT (9 << 20) 105 #define SYS_CFG_DVIMODE (11 << 20) 106 #define SYS_CFG_POWER (12 << 20) 107 #define SYS_CFG_SITE_MB (0 << 16) 108 #define SYS_CFG_SITE_DB1 (1 << 16) 109 #define SYS_CFG_SITE_DB2 (2 << 16) 110 #define SYS_CFG_STACK(n) ((n) << 12) 111 112 #define SYS_CFG_ERR (1 << 1) 113 #define SYS_CFG_COMPLETE (1 << 0) 114 115 int v2m_cfg_write(u32 devfn, u32 data); 116 int v2m_cfg_read(u32 devfn, u32 *data); 117 void v2m_flags_set(u32 data); 118 119 /* 120 * Miscellaneous 121 */ 122 #define SYS_MISC_MASTERSITE (1 << 14) 123 #define SYS_PROCIDx_HBI_MASK 0xfff 124 125 /* 126 * Core tile IDs 127 */ 128 #define V2M_CT_ID_CA9 0x0c000191 129 #define V2M_CT_ID_UNSUPPORTED 0xff000191 130 #define V2M_CT_ID_MASK 0xff000fff 131 132 struct ct_desc { 133 u32 id; 134 const char *name; 135 void (*map_io)(void); 136 void (*init_early)(void); 137 void (*init_irq)(void); 138 void (*init_tile)(void); 139 #ifdef CONFIG_SMP 140 void (*init_cpu_map)(void); 141 void (*smp_enable)(unsigned int); 142 #endif 143 }; 144 145 extern struct ct_desc *ct_desc; 146 147 #endif 148