1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright 2012 Freescale Semiconductor, Inc.
4 */
5
6 #include <linux/clk/mxs.h>
7 #include <linux/clkdev.h>
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
10 #include <linux/err.h>
11 #include <linux/init.h>
12 #include <linux/io.h>
13 #include <linux/of.h>
14 #include <linux/of_address.h>
15 #include "clk.h"
16
17 static void __iomem *clkctrl;
18 #define CLKCTRL clkctrl
19
20 #define PLL0CTRL0 (CLKCTRL + 0x0000)
21 #define PLL1CTRL0 (CLKCTRL + 0x0020)
22 #define PLL2CTRL0 (CLKCTRL + 0x0040)
23 #define CPU (CLKCTRL + 0x0050)
24 #define HBUS (CLKCTRL + 0x0060)
25 #define XBUS (CLKCTRL + 0x0070)
26 #define XTAL (CLKCTRL + 0x0080)
27 #define SSP0 (CLKCTRL + 0x0090)
28 #define SSP1 (CLKCTRL + 0x00a0)
29 #define SSP2 (CLKCTRL + 0x00b0)
30 #define SSP3 (CLKCTRL + 0x00c0)
31 #define GPMI (CLKCTRL + 0x00d0)
32 #define SPDIF (CLKCTRL + 0x00e0)
33 #define EMI (CLKCTRL + 0x00f0)
34 #define SAIF0 (CLKCTRL + 0x0100)
35 #define SAIF1 (CLKCTRL + 0x0110)
36 #define LCDIF (CLKCTRL + 0x0120)
37 #define ETM (CLKCTRL + 0x0130)
38 #define ENET (CLKCTRL + 0x0140)
39 #define FLEXCAN (CLKCTRL + 0x0160)
40 #define FRAC0 (CLKCTRL + 0x01b0)
41 #define FRAC1 (CLKCTRL + 0x01c0)
42 #define CLKSEQ (CLKCTRL + 0x01d0)
43
44 #define BP_CPU_INTERRUPT_WAIT 12
45 #define BP_SAIF_DIV_FRAC_EN 16
46 #define BP_ENET_DIV_TIME 21
47 #define BP_ENET_SLEEP 31
48 #define BP_CLKSEQ_BYPASS_SAIF0 0
49 #define BP_CLKSEQ_BYPASS_SSP0 3
50 #define BP_FRAC0_IO1FRAC 16
51 #define BP_FRAC0_IO0FRAC 24
52
53 static void __iomem *digctrl;
54 #define DIGCTRL digctrl
55 #define BP_SAIF_CLKMUX 10
56
57 /*
58 * HW_SAIF_CLKMUX_SEL:
59 * DIRECT(0x0): SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1
60 * clock pins selected for SAIF1 input clocks.
61 * CROSSINPUT(0x1): SAIF1 clock inputs selected for SAIF0 input clocks, and
62 * SAIF0 clock inputs selected for SAIF1 input clocks.
63 * EXTMSTR0(0x2): SAIF0 clock pin selected for both SAIF0 and SAIF1 input
64 * clocks.
65 * EXTMSTR1(0x3): SAIF1 clock pin selected for both SAIF0 and SAIF1 input
66 * clocks.
67 */
mxs_saif_clkmux_select(unsigned int clkmux)68 int mxs_saif_clkmux_select(unsigned int clkmux)
69 {
70 if (clkmux > 0x3)
71 return -EINVAL;
72
73 writel_relaxed(0x3 << BP_SAIF_CLKMUX, DIGCTRL + CLR);
74 writel_relaxed(clkmux << BP_SAIF_CLKMUX, DIGCTRL + SET);
75
76 return 0;
77 }
78
clk_misc_init(void)79 static void __init clk_misc_init(void)
80 {
81 u32 val;
82
83 /* Gate off cpu clock in WFI for power saving */
84 writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
85
86 /* 0 is a bad default value for a divider */
87 writel_relaxed(1 << BP_ENET_DIV_TIME, ENET + SET);
88
89 /* Clear BYPASS for SAIF */
90 writel_relaxed(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ + CLR);
91
92 /* SAIF has to use frac div for functional operation */
93 val = readl_relaxed(SAIF0);
94 val |= 1 << BP_SAIF_DIV_FRAC_EN;
95 writel_relaxed(val, SAIF0);
96
97 val = readl_relaxed(SAIF1);
98 val |= 1 << BP_SAIF_DIV_FRAC_EN;
99 writel_relaxed(val, SAIF1);
100
101 /* Extra fec clock setting */
102 val = readl_relaxed(ENET);
103 val &= ~(1 << BP_ENET_SLEEP);
104 writel_relaxed(val, ENET);
105
106 /*
107 * Source ssp clock from ref_io than ref_xtal,
108 * as ref_xtal only provides 24 MHz as maximum.
109 */
110 writel_relaxed(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ + CLR);
111
112 /*
113 * 480 MHz seems too high to be ssp clock source directly,
114 * so set frac0 to get a 288 MHz ref_io0 and ref_io1.
115 */
116 val = readl_relaxed(FRAC0);
117 val &= ~((0x3f << BP_FRAC0_IO0FRAC) | (0x3f << BP_FRAC0_IO1FRAC));
118 val |= (30 << BP_FRAC0_IO0FRAC) | (30 << BP_FRAC0_IO1FRAC);
119 writel_relaxed(val, FRAC0);
120 }
121
122 static const char *const sel_cpu[] __initconst = { "ref_cpu", "ref_xtal", };
123 static const char *const sel_io0[] __initconst = { "ref_io0", "ref_xtal", };
124 static const char *const sel_io1[] __initconst = { "ref_io1", "ref_xtal", };
125 static const char *const sel_pix[] __initconst = { "ref_pix", "ref_xtal", };
126 static const char *const sel_gpmi[] __initconst = { "ref_gpmi", "ref_xtal", };
127 static const char *const sel_pll0[] __initconst = { "pll0", "ref_xtal", };
128 static const char *const cpu_sels[] __initconst = { "cpu_pll", "cpu_xtal", };
129 static const char *const emi_sels[] __initconst = { "emi_pll", "emi_xtal", };
130 static const char *const ptp_sels[] __initconst = { "ref_xtal", "pll0", };
131
132 enum imx28_clk {
133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1,
134 ref_pix, ref_hsadc, ref_gpmi, saif0_sel, saif1_sel, gpmi_sel,
135 ssp0_sel, ssp1_sel, ssp2_sel, ssp3_sel, emi_sel, etm_sel,
136 lcdif_sel, cpu, ptp_sel, cpu_pll, cpu_xtal, hbus, xbus,
137 ssp0_div, ssp1_div, ssp2_div, ssp3_div, gpmi_div, emi_pll,
138 emi_xtal, lcdif_div, etm_div, ptp, saif0_div, saif1_div,
139 clk32k_div, rtc, lradc, spdif_div, clk32k, pwm, uart, ssp0,
140 ssp1, ssp2, ssp3, gpmi, spdif, emi, saif0, saif1, lcdif, etm,
141 fec, can0, can1, usb0, usb1, usb0_phy, usb1_phy, enet_out,
142 clk_max
143 };
144
145 static struct clk *clks[clk_max];
146 static struct clk_onecell_data clk_data;
147
148 static enum imx28_clk clks_init_on[] __initdata = {
149 cpu, hbus, xbus, emi, uart,
150 };
151
mx28_clocks_init(struct device_node * np)152 static void __init mx28_clocks_init(struct device_node *np)
153 {
154 struct device_node *dcnp;
155 u32 i;
156
157 dcnp = of_find_compatible_node(NULL, NULL, "fsl,imx28-digctl");
158 digctrl = of_iomap(dcnp, 0);
159 WARN_ON(!digctrl);
160 of_node_put(dcnp);
161
162 clkctrl = of_iomap(np, 0);
163 WARN_ON(!clkctrl);
164
165 clk_misc_init();
166
167 clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000);
168 clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000);
169 clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000);
170 clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000);
171 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0);
172 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1);
173 clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2);
174 clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3);
175 clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC1, 0);
176 clks[ref_hsadc] = mxs_clk_ref("ref_hsadc", "pll0", FRAC1, 1);
177 clks[ref_gpmi] = mxs_clk_ref("ref_gpmi", "pll0", FRAC1, 2);
178 clks[saif0_sel] = mxs_clk_mux("saif0_sel", CLKSEQ, 0, 1, sel_pll0, ARRAY_SIZE(sel_pll0));
179 clks[saif1_sel] = mxs_clk_mux("saif1_sel", CLKSEQ, 1, 1, sel_pll0, ARRAY_SIZE(sel_pll0));
180 clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 2, 1, sel_gpmi, ARRAY_SIZE(sel_gpmi));
181 clks[ssp0_sel] = mxs_clk_mux("ssp0_sel", CLKSEQ, 3, 1, sel_io0, ARRAY_SIZE(sel_io0));
182 clks[ssp1_sel] = mxs_clk_mux("ssp1_sel", CLKSEQ, 4, 1, sel_io0, ARRAY_SIZE(sel_io0));
183 clks[ssp2_sel] = mxs_clk_mux("ssp2_sel", CLKSEQ, 5, 1, sel_io1, ARRAY_SIZE(sel_io1));
184 clks[ssp3_sel] = mxs_clk_mux("ssp3_sel", CLKSEQ, 6, 1, sel_io1, ARRAY_SIZE(sel_io1));
185 clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 7, 1, emi_sels, ARRAY_SIZE(emi_sels));
186 clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu));
187 clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 14, 1, sel_pix, ARRAY_SIZE(sel_pix));
188 clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 18, 1, cpu_sels, ARRAY_SIZE(cpu_sels));
189 clks[ptp_sel] = mxs_clk_mux("ptp_sel", ENET, 19, 1, ptp_sels, ARRAY_SIZE(ptp_sels));
190 clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28);
191 clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29);
192 clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 31);
193 clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31);
194 clks[ssp0_div] = mxs_clk_div("ssp0_div", "ssp0_sel", SSP0, 0, 9, 29);
195 clks[ssp1_div] = mxs_clk_div("ssp1_div", "ssp1_sel", SSP1, 0, 9, 29);
196 clks[ssp2_div] = mxs_clk_div("ssp2_div", "ssp2_sel", SSP2, 0, 9, 29);
197 clks[ssp3_div] = mxs_clk_div("ssp3_div", "ssp3_sel", SSP3, 0, 9, 29);
198 clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29);
199 clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28);
200 clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29);
201 clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", LCDIF, 0, 13, 29);
202 clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 7, 29);
203 clks[ptp] = mxs_clk_div("ptp", "ptp_sel", ENET, 21, 6, 27);
204 clks[saif0_div] = mxs_clk_frac("saif0_div", "saif0_sel", SAIF0, 0, 16, 29);
205 clks[saif1_div] = mxs_clk_frac("saif1_div", "saif1_sel", SAIF1, 0, 16, 29);
206 clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750);
207 clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768);
208 clks[lradc] = mxs_clk_fixed_factor("lradc", "clk32k", 1, 16);
209 clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll0", 1, 4);
210 clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26);
211 clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29);
212 clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31);
213 clks[ssp0] = mxs_clk_gate("ssp0", "ssp0_div", SSP0, 31);
214 clks[ssp1] = mxs_clk_gate("ssp1", "ssp1_div", SSP1, 31);
215 clks[ssp2] = mxs_clk_gate("ssp2", "ssp2_div", SSP2, 31);
216 clks[ssp3] = mxs_clk_gate("ssp3", "ssp3_div", SSP3, 31);
217 clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31);
218 clks[spdif] = mxs_clk_gate("spdif", "spdif_div", SPDIF, 31);
219 clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31);
220 clks[saif0] = mxs_clk_gate("saif0", "saif0_div", SAIF0, 31);
221 clks[saif1] = mxs_clk_gate("saif1", "saif1_div", SAIF1, 31);
222 clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", LCDIF, 31);
223 clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31);
224 clks[fec] = mxs_clk_gate("fec", "hbus", ENET, 30);
225 clks[can0] = mxs_clk_gate("can0", "ref_xtal", FLEXCAN, 30);
226 clks[can1] = mxs_clk_gate("can1", "ref_xtal", FLEXCAN, 28);
227 clks[usb0] = mxs_clk_gate("usb0", "usb0_phy", DIGCTRL, 2);
228 clks[usb1] = mxs_clk_gate("usb1", "usb1_phy", DIGCTRL, 16);
229 clks[usb0_phy] = clk_register_gate(NULL, "usb0_phy", "pll0", 0, PLL0CTRL0, 18, 0, &mxs_lock);
230 clks[usb1_phy] = clk_register_gate(NULL, "usb1_phy", "pll1", 0, PLL1CTRL0, 18, 0, &mxs_lock);
231 clks[enet_out] = clk_register_gate(NULL, "enet_out", "pll2", 0, ENET, 18, 0, &mxs_lock);
232
233 for (i = 0; i < ARRAY_SIZE(clks); i++)
234 if (IS_ERR(clks[i])) {
235 pr_err("i.MX28 clk %d: register failed with %ld\n",
236 i, PTR_ERR(clks[i]));
237 return;
238 }
239
240 clk_data.clks = clks;
241 clk_data.clk_num = ARRAY_SIZE(clks);
242 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
243
244 clk_register_clkdev(clks[enet_out], NULL, "enet_out");
245
246 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
247 clk_prepare_enable(clks[clks_init_on[i]]);
248 }
249 CLK_OF_DECLARE(imx28_clkctrl, "fsl,imx28-clkctrl", mx28_clocks_init);
250