1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 */
5
6 #ifndef __LINUX_MTD_SPI_NOR_H
7 #define __LINUX_MTD_SPI_NOR_H
8
9 #include <linux/bitops.h>
10 #include <linux/mtd/cfi.h>
11 #include <linux/mtd/mtd.h>
12 #include <linux/spi/spi-mem.h>
13
14 /*
15 * Note on opcode nomenclature: some opcodes have a format like
16 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
17 * of I/O lines used for the opcode, address, and data (respectively). The
18 * FUNCTION has an optional suffix of '4', to represent an opcode which
19 * requires a 4-byte (32-bit) address.
20 */
21
22 /* Flash opcodes. */
23 #define SPINOR_OP_WRDI 0x04 /* Write disable */
24 #define SPINOR_OP_WREN 0x06 /* Write enable */
25 #define SPINOR_OP_RDSR 0x05 /* Read status register */
26 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
27 #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
28 #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
29 #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
30 #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
31 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
32 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
33 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
34 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
35 #define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
36 #define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
37 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
38 #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
39 #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
40 #define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */
41 #define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */
42 #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
43 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
44 #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
45 #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
46 #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
47 #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
48 #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
49 #define SPINOR_OP_RDCR 0x35 /* Read configuration register */
50 #define SPINOR_OP_SRSTEN 0x66 /* Software Reset Enable */
51 #define SPINOR_OP_SRST 0x99 /* Software Reset */
52 #define SPINOR_OP_GBULK 0x98 /* Global Block Unlock */
53
54 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
55 #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
56 #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
57 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
58 #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
59 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
60 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
61 #define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */
62 #define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */
63 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
64 #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
65 #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
66 #define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */
67 #define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */
68 #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
69 #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
70 #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
71
72 /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
73 #define SPINOR_OP_READ_1_1_1_DTR 0x0d
74 #define SPINOR_OP_READ_1_2_2_DTR 0xbd
75 #define SPINOR_OP_READ_1_4_4_DTR 0xed
76
77 #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
78 #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
79 #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
80
81 /* Used for SST flashes only. */
82 #define SPINOR_OP_BP 0x02 /* Byte program */
83 #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
84
85 /* Used for Macronix and Winbond flashes. */
86 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
87 #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
88
89 /* Used for Spansion flashes only. */
90 #define SPINOR_OP_BRWR 0x17 /* Bank register write */
91
92 /* Used for Micron flashes only. */
93 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
94 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
95
96 /* Used for GigaDevices and Winbond flashes. */
97 #define SPINOR_OP_ESECR 0x44 /* Erase Security registers */
98 #define SPINOR_OP_PSECR 0x42 /* Program Security registers */
99 #define SPINOR_OP_RSECR 0x48 /* Read Security registers */
100
101 /* Status Register bits. */
102 #define SR_WIP BIT(0) /* Write in progress */
103 #define SR_WEL BIT(1) /* Write enable latch */
104 /* meaning of other SR_* bits may differ between vendors */
105 #define SR_BP0 BIT(2) /* Block protect 0 */
106 #define SR_BP1 BIT(3) /* Block protect 1 */
107 #define SR_BP2 BIT(4) /* Block protect 2 */
108 #define SR_BP3 BIT(5) /* Block protect 3 */
109 #define SR_TB_BIT5 BIT(5) /* Top/Bottom protect */
110 #define SR_BP3_BIT6 BIT(6) /* Block protect 3 */
111 #define SR_TB_BIT6 BIT(6) /* Top/Bottom protect */
112 #define SR_SRWD BIT(7) /* SR write protect */
113 /* Spansion/Cypress specific status bits */
114 #define SR_E_ERR BIT(5)
115 #define SR_P_ERR BIT(6)
116
117 #define SR1_QUAD_EN_BIT6 BIT(6)
118
119 #define SR_BP_SHIFT 2
120
121 /* Enhanced Volatile Configuration Register bits */
122 #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
123
124 /* Status Register 2 bits. */
125 #define SR2_QUAD_EN_BIT1 BIT(1)
126 #define SR2_LB1 BIT(3) /* Security Register Lock Bit 1 */
127 #define SR2_LB2 BIT(4) /* Security Register Lock Bit 2 */
128 #define SR2_LB3 BIT(5) /* Security Register Lock Bit 3 */
129 #define SR2_QUAD_EN_BIT7 BIT(7)
130
131 /* Supported SPI protocols */
132 #define SNOR_PROTO_INST_MASK GENMASK(23, 16)
133 #define SNOR_PROTO_INST_SHIFT 16
134 #define SNOR_PROTO_INST(_nbits) \
135 ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
136 SNOR_PROTO_INST_MASK)
137
138 #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
139 #define SNOR_PROTO_ADDR_SHIFT 8
140 #define SNOR_PROTO_ADDR(_nbits) \
141 ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
142 SNOR_PROTO_ADDR_MASK)
143
144 #define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
145 #define SNOR_PROTO_DATA_SHIFT 0
146 #define SNOR_PROTO_DATA(_nbits) \
147 ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
148 SNOR_PROTO_DATA_MASK)
149
150 #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */
151
152 #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
153 (SNOR_PROTO_INST(_inst_nbits) | \
154 SNOR_PROTO_ADDR(_addr_nbits) | \
155 SNOR_PROTO_DATA(_data_nbits))
156 #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
157 (SNOR_PROTO_IS_DTR | \
158 SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
159
160 enum spi_nor_protocol {
161 SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
162 SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
163 SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
164 SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
165 SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
166 SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
167 SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
168 SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
169 SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
170 SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
171
172 SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
173 SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
174 SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
175 SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
176 SNOR_PROTO_8_8_8_DTR = SNOR_PROTO_DTR(8, 8, 8),
177 };
178
spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)179 static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
180 {
181 return !!(proto & SNOR_PROTO_IS_DTR);
182 }
183
spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)184 static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
185 {
186 return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
187 SNOR_PROTO_INST_SHIFT;
188 }
189
spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)190 static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
191 {
192 return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
193 SNOR_PROTO_ADDR_SHIFT;
194 }
195
spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)196 static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
197 {
198 return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
199 SNOR_PROTO_DATA_SHIFT;
200 }
201
spi_nor_get_protocol_width(enum spi_nor_protocol proto)202 static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
203 {
204 return spi_nor_get_protocol_data_nbits(proto);
205 }
206
207 /**
208 * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
209 * supported by the SPI controller (bus master).
210 * @mask: the bitmask listing all the supported hw capabilies
211 */
212 struct spi_nor_hwcaps {
213 u32 mask;
214 };
215
216 /*
217 *(Fast) Read capabilities.
218 * MUST be ordered by priority: the higher bit position, the higher priority.
219 * As a matter of performances, it is relevant to use Octal SPI protocols first,
220 * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
221 * (Slow) Read.
222 */
223 #define SNOR_HWCAPS_READ_MASK GENMASK(15, 0)
224 #define SNOR_HWCAPS_READ BIT(0)
225 #define SNOR_HWCAPS_READ_FAST BIT(1)
226 #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
227
228 #define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
229 #define SNOR_HWCAPS_READ_1_1_2 BIT(3)
230 #define SNOR_HWCAPS_READ_1_2_2 BIT(4)
231 #define SNOR_HWCAPS_READ_2_2_2 BIT(5)
232 #define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
233
234 #define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
235 #define SNOR_HWCAPS_READ_1_1_4 BIT(7)
236 #define SNOR_HWCAPS_READ_1_4_4 BIT(8)
237 #define SNOR_HWCAPS_READ_4_4_4 BIT(9)
238 #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
239
240 #define SNOR_HWCAPS_READ_OCTAL GENMASK(15, 11)
241 #define SNOR_HWCAPS_READ_1_1_8 BIT(11)
242 #define SNOR_HWCAPS_READ_1_8_8 BIT(12)
243 #define SNOR_HWCAPS_READ_8_8_8 BIT(13)
244 #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
245 #define SNOR_HWCAPS_READ_8_8_8_DTR BIT(15)
246
247 /*
248 * Page Program capabilities.
249 * MUST be ordered by priority: the higher bit position, the higher priority.
250 * Like (Fast) Read capabilities, Octal/Quad SPI protocols are preferred to the
251 * legacy SPI 1-1-1 protocol.
252 * Note that Dual Page Programs are not supported because there is no existing
253 * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
254 * implements such commands.
255 */
256 #define SNOR_HWCAPS_PP_MASK GENMASK(23, 16)
257 #define SNOR_HWCAPS_PP BIT(16)
258
259 #define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
260 #define SNOR_HWCAPS_PP_1_1_4 BIT(17)
261 #define SNOR_HWCAPS_PP_1_4_4 BIT(18)
262 #define SNOR_HWCAPS_PP_4_4_4 BIT(19)
263
264 #define SNOR_HWCAPS_PP_OCTAL GENMASK(23, 20)
265 #define SNOR_HWCAPS_PP_1_1_8 BIT(20)
266 #define SNOR_HWCAPS_PP_1_8_8 BIT(21)
267 #define SNOR_HWCAPS_PP_8_8_8 BIT(22)
268 #define SNOR_HWCAPS_PP_8_8_8_DTR BIT(23)
269
270 #define SNOR_HWCAPS_X_X_X (SNOR_HWCAPS_READ_2_2_2 | \
271 SNOR_HWCAPS_READ_4_4_4 | \
272 SNOR_HWCAPS_READ_8_8_8 | \
273 SNOR_HWCAPS_PP_4_4_4 | \
274 SNOR_HWCAPS_PP_8_8_8)
275
276 #define SNOR_HWCAPS_X_X_X_DTR (SNOR_HWCAPS_READ_8_8_8_DTR | \
277 SNOR_HWCAPS_PP_8_8_8_DTR)
278
279 #define SNOR_HWCAPS_DTR (SNOR_HWCAPS_READ_1_1_1_DTR | \
280 SNOR_HWCAPS_READ_1_2_2_DTR | \
281 SNOR_HWCAPS_READ_1_4_4_DTR | \
282 SNOR_HWCAPS_READ_1_8_8_DTR | \
283 SNOR_HWCAPS_READ_8_8_8_DTR)
284
285 #define SNOR_HWCAPS_ALL (SNOR_HWCAPS_READ_MASK | \
286 SNOR_HWCAPS_PP_MASK)
287
288 /* Forward declaration that is used in 'struct spi_nor_controller_ops' */
289 struct spi_nor;
290
291 /**
292 * struct spi_nor_controller_ops - SPI NOR controller driver specific
293 * operations.
294 * @prepare: [OPTIONAL] do some preparations for the
295 * read/write/erase/lock/unlock operations.
296 * @unprepare: [OPTIONAL] do some post work after the
297 * read/write/erase/lock/unlock operations.
298 * @read_reg: read out the register.
299 * @write_reg: write data to the register.
300 * @read: read data from the SPI NOR.
301 * @write: write data to the SPI NOR.
302 * @erase: erase a sector of the SPI NOR at the offset @offs; if
303 * not provided by the driver, SPI NOR will send the erase
304 * opcode via write_reg().
305 */
306 struct spi_nor_controller_ops {
307 int (*prepare)(struct spi_nor *nor);
308 void (*unprepare)(struct spi_nor *nor);
309 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, size_t len);
310 int (*write_reg)(struct spi_nor *nor, u8 opcode, const u8 *buf,
311 size_t len);
312
313 ssize_t (*read)(struct spi_nor *nor, loff_t from, size_t len, u8 *buf);
314 ssize_t (*write)(struct spi_nor *nor, loff_t to, size_t len,
315 const u8 *buf);
316 int (*erase)(struct spi_nor *nor, loff_t offs);
317 };
318
319 /**
320 * enum spi_nor_cmd_ext - describes the command opcode extension in DTR mode
321 * @SPI_NOR_EXT_NONE: no extension. This is the default, and is used in Legacy
322 * SPI mode
323 * @SPI_NOR_EXT_REPEAT: the extension is same as the opcode
324 * @SPI_NOR_EXT_INVERT: the extension is the bitwise inverse of the opcode
325 * @SPI_NOR_EXT_HEX: the extension is any hex value. The command and opcode
326 * combine to form a 16-bit opcode.
327 */
328 enum spi_nor_cmd_ext {
329 SPI_NOR_EXT_NONE = 0,
330 SPI_NOR_EXT_REPEAT,
331 SPI_NOR_EXT_INVERT,
332 SPI_NOR_EXT_HEX,
333 };
334
335 /*
336 * Forward declarations that are used internally by the core and manufacturer
337 * drivers.
338 */
339 struct flash_info;
340 struct spi_nor_manufacturer;
341 struct spi_nor_flash_parameter;
342
343 /**
344 * struct spi_nor - Structure for defining the SPI NOR layer
345 * @mtd: an mtd_info structure
346 * @lock: the lock for the read/write/erase/lock/unlock operations
347 * @dev: pointer to an SPI device or an SPI NOR controller device
348 * @spimem: pointer to the SPI memory device
349 * @bouncebuf: bounce buffer used when the buffer passed by the MTD
350 * layer is not DMA-able
351 * @bouncebuf_size: size of the bounce buffer
352 * @info: SPI NOR part JEDEC MFR ID and other info
353 * @manufacturer: SPI NOR manufacturer
354 * @addr_width: number of address bytes
355 * @erase_opcode: the opcode for erasing a sector
356 * @read_opcode: the read opcode
357 * @read_dummy: the dummy needed by the read operation
358 * @program_opcode: the program opcode
359 * @sst_write_second: used by the SST write operation
360 * @flags: flag options for the current SPI NOR (SNOR_F_*)
361 * @cmd_ext_type: the command opcode extension type for DTR mode.
362 * @read_proto: the SPI protocol for read operations
363 * @write_proto: the SPI protocol for write operations
364 * @reg_proto: the SPI protocol for read_reg/write_reg/erase operations
365 * @sfdp: the SFDP data of the flash
366 * @debugfs_root: pointer to the debugfs directory
367 * @controller_ops: SPI NOR controller driver specific operations.
368 * @params: [FLASH-SPECIFIC] SPI NOR flash parameters and settings.
369 * The structure includes legacy flash parameters and
370 * settings that can be overwritten by the spi_nor_fixups
371 * hooks, or dynamically when parsing the SFDP tables.
372 * @dirmap: pointers to struct spi_mem_dirmap_desc for reads/writes.
373 * @priv: pointer to the private data
374 */
375 struct spi_nor {
376 struct mtd_info mtd;
377 struct mutex lock;
378 struct device *dev;
379 struct spi_mem *spimem;
380 u8 *bouncebuf;
381 size_t bouncebuf_size;
382 const struct flash_info *info;
383 const struct spi_nor_manufacturer *manufacturer;
384 u8 addr_width;
385 u8 erase_opcode;
386 u8 read_opcode;
387 u8 read_dummy;
388 u8 program_opcode;
389 enum spi_nor_protocol read_proto;
390 enum spi_nor_protocol write_proto;
391 enum spi_nor_protocol reg_proto;
392 bool sst_write_second;
393 u32 flags;
394 enum spi_nor_cmd_ext cmd_ext_type;
395 struct sfdp *sfdp;
396 struct dentry *debugfs_root;
397
398 const struct spi_nor_controller_ops *controller_ops;
399
400 struct spi_nor_flash_parameter *params;
401
402 struct {
403 struct spi_mem_dirmap_desc *rdesc;
404 struct spi_mem_dirmap_desc *wdesc;
405 } dirmap;
406
407 void *priv;
408 };
409
spi_nor_set_flash_node(struct spi_nor * nor,struct device_node * np)410 static inline void spi_nor_set_flash_node(struct spi_nor *nor,
411 struct device_node *np)
412 {
413 mtd_set_of_node(&nor->mtd, np);
414 }
415
spi_nor_get_flash_node(struct spi_nor * nor)416 static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
417 {
418 return mtd_get_of_node(&nor->mtd);
419 }
420
421 /**
422 * spi_nor_scan() - scan the SPI NOR
423 * @nor: the spi_nor structure
424 * @name: the chip type name
425 * @hwcaps: the hardware capabilities supported by the controller driver
426 *
427 * The drivers can use this function to scan the SPI NOR.
428 * In the scanning, it will try to get all the necessary information to
429 * fill the mtd_info{} and the spi_nor{}.
430 *
431 * The chip type name can be provided through the @name parameter.
432 *
433 * Return: 0 for success, others for failure.
434 */
435 int spi_nor_scan(struct spi_nor *nor, const char *name,
436 const struct spi_nor_hwcaps *hwcaps);
437
438 /**
439 * spi_nor_restore_addr_mode() - restore the status of SPI NOR
440 * @nor: the spi_nor structure
441 */
442 void spi_nor_restore(struct spi_nor *nor);
443
444 #endif
445