1 /* 2 * linux/include/asm-arm/hardware/SA-1111.h 3 * 4 * Copyright (C) 2000 John G Dorsey <john+@cs.cmu.edu> 5 * 6 * This file contains definitions for the SA-1111 Companion Chip. 7 * (Structure and naming borrowed from SA-1101.h, by Peter Danielsson.) 8 * 9 * Macro that calculates real address for registers in the SA-1111 10 */ 11 12 #ifndef _ASM_ARCH_SA1111 13 #define _ASM_ARCH_SA1111 14 15 #include <asm/arch/bitfield.h> 16 17 /* 18 * The SA1111 is always located at virtual 0xf4000000, and is always 19 * "native" endian. 20 */ 21 22 #define SA1111_VBASE 0xf4000000 23 24 /* Don't use these! */ 25 #define SA1111_p2v( x ) ((x) - SA1111_BASE + SA1111_VBASE) 26 #define SA1111_v2p( x ) ((x) - SA1111_VBASE + SA1111_BASE) 27 28 #ifndef __ASSEMBLY__ 29 30 extern struct resource sa1111_resource; 31 #define _SA1111(x) ((x) + sa1111_resource.start) 32 #endif 33 34 /* 35 * 26 bits of the SA-1110 address bus are available to the SA-1111. 36 * Use these when feeding target addresses to the DMA engines. 37 */ 38 39 #define SA1111_ADDR_WIDTH (26) 40 #define SA1111_ADDR_MASK ((1<<SA1111_ADDR_WIDTH)-1) 41 #define SA1111_DMA_ADDR(x) ((x)&SA1111_ADDR_MASK) 42 43 /* 44 * Don't ask the (SAC) DMA engines to move less than this amount. 45 */ 46 47 #define SA1111_SAC_DMA_MIN_XFER (0x800) 48 49 /* 50 * SA1111 register definitions. 51 */ 52 #define __CCREG(x) __REGP(SA1111_VBASE + (x)) 53 54 /* System Bus Interface (SBI) 55 * 56 * Registers 57 * SKCR Control Register 58 * SMCR Shared Memory Controller Register 59 * SKID ID Register 60 */ 61 #define SA1111_SKCR 0x0000 62 #define SA1111_SMCR 0x0004 63 #define SA1111_SKID 0x0008 64 65 #define _SBI_SKCR _SA1111(SA1111_SKCR) 66 #define _SBI_SMCR _SA1111(SA1111_SMCR) 67 #define _SBI_SKID _SA1111(SA1111_SKID) 68 69 #if LANGUAGE == C 70 71 #define SBI_SKCR __CCREG(SA1111_SKCR) 72 #define SBI_SMCR __CCREG(SA1111_SMCR) 73 #define SBI_SKID __CCREG(SA1111_SKID) 74 75 #endif /* LANGUAGE == C */ 76 77 #define SKCR_PLL_BYPASS (1<<0) 78 #define SKCR_RCLKEN (1<<1) 79 #define SKCR_SLEEP (1<<2) 80 #define SKCR_DOZE (1<<3) 81 #define SKCR_VCO_OFF (1<<4) 82 #define SKCR_SCANTSTEN (1<<5) 83 #define SKCR_CLKTSTEN (1<<6) 84 #define SKCR_RDYEN (1<<7) 85 #define SKCR_SELAC (1<<8) 86 #define SKCR_OPPC (1<<9) 87 #define SKCR_PLLTSTEN (1<<10) 88 #define SKCR_USBIOTSTEN (1<<11) 89 /* 90 * Don't believe the specs! Take them, throw them outside. Leave them 91 * there for a week. Spit on them. Walk on them. Stamp on them. 92 * Pour gasoline over them and finally burn them. Now think about coding. 93 * - The October 1999 errata (278260-007) says its bit 13, 1 to enable. 94 * - The Feb 2001 errata (278260-010) says that the previous errata 95 * (278260-009) is wrong, and its bit actually 12, fixed in spec 96 * 278242-003. 97 * - The SA1111 manual (278242) says bit 12, but 0 to enable. 98 * - Reality is bit 13, 1 to enable. 99 * -- rmk 100 */ 101 #define SKCR_OE_EN (1<<13) 102 103 #define SMCR_DTIM (1<<0) 104 #define SMCR_MBGE (1<<1) 105 #define SMCR_DRAC_0 (1<<2) 106 #define SMCR_DRAC_1 (1<<3) 107 #define SMCR_DRAC_2 (1<<4) 108 #define SMCR_DRAC Fld(3, 2) 109 #define SMCR_CLAT (1<<5) 110 111 #define SKID_SIREV_MASK (0x000000f0) 112 #define SKID_MTREV_MASK (0x0000000f) 113 #define SKID_ID_MASK (0xffffff00) 114 #define SKID_SA1111_ID (0x690cc200) 115 116 /* 117 * System Controller 118 * 119 * Registers 120 * SKPCR Power Control Register 121 * SKCDR Clock Divider Register 122 * SKAUD Audio Clock Divider Register 123 * SKPMC PS/2 Mouse Clock Divider Register 124 * SKPTC PS/2 Track Pad Clock Divider Register 125 * SKPEN0 PWM0 Enable Register 126 * SKPWM0 PWM0 Clock Register 127 * SKPEN1 PWM1 Enable Register 128 * SKPWM1 PWM1 Clock Register 129 */ 130 131 #define _SKPCR _SA1111(0x0200) 132 #define _SKCDR _SA1111(0x0204) 133 #define _SKAUD _SA1111(0x0208) 134 #define _SKPMC _SA1111(0x020c) 135 #define _SKPTC _SA1111(0x0210) 136 #define _SKPEN0 _SA1111(0x0214) 137 #define _SKPWM0 _SA1111(0x0218) 138 #define _SKPEN1 _SA1111(0x021c) 139 #define _SKPWM1 _SA1111(0x0220) 140 141 #if LANGUAGE == C 142 143 #define SKPCR __CCREG(0x0200) 144 #define SKCDR __CCREG(0x0204) 145 #define SKAUD __CCREG(0x0208) 146 #define SKPMC __CCREG(0x020c) 147 #define SKPTC __CCREG(0x0210) 148 #define SKPEN0 __CCREG(0x0214) 149 #define SKPWM0 __CCREG(0x0218) 150 #define SKPEN1 __CCREG(0x021c) 151 #define SKPWM1 __CCREG(0x0220) 152 153 #endif /* LANGUAGE == C */ 154 155 #define SKPCR_UCLKEN (1<<0) 156 #define SKPCR_ACCLKEN (1<<1) 157 #define SKPCR_I2SCLKEN (1<<2) 158 #define SKPCR_L3CLKEN (1<<3) 159 #define SKPCR_SCLKEN (1<<4) 160 #define SKPCR_PMCLKEN (1<<5) 161 #define SKPCR_PTCLKEN (1<<6) 162 #define SKPCR_DCLKEN (1<<7) 163 #define SKPCR_PWMCLKEN (1<<8) 164 165 /* 166 * USB Host controller 167 */ 168 #define _USB_OHCI_OP_BASE _SA1111( 0x400 ) 169 #define _USB_STATUS _SA1111( 0x518 ) 170 #define _USB_RESET _SA1111( 0x51c ) 171 #define _USB_INTERRUPTEST _SA1111( 0x520 ) 172 173 #define _USB_EXTENT (_USB_INTERRUPTEST - _USB_OHCI_OP_BASE + 4) 174 175 #if LANGUAGE == C 176 177 #define USB_OHCI_OP_BASE __CCREG(0x0400) 178 #define USB_STATUS __CCREG(0x0518) 179 #define USB_RESET __CCREG(0x051c) 180 #define USB_INTERRUPTEST __CCReG(0x0520) 181 182 #endif /* LANGUAGE == C */ 183 184 #define USB_RESET_FORCEIFRESET (1 << 0) 185 #define USB_RESET_FORCEHCRESET (1 << 1) 186 #define USB_RESET_CLKGENRESET (1 << 2) 187 #define USB_RESET_SIMSCALEDOWN (1 << 3) 188 #define USB_RESET_USBINTTEST (1 << 4) 189 #define USB_RESET_SLEEPSTBYEN (1 << 5) 190 #define USB_RESET_PWRSENSELOW (1 << 6) 191 #define USB_RESET_PWRCTRLLOW (1 << 7) 192 193 /* 194 * Serial Audio Controller 195 * 196 * Registers 197 * SACR0 Serial Audio Common Control Register 198 * SACR1 Serial Audio Alternate Mode (I2C/MSB) Control Register 199 * SACR2 Serial Audio AC-link Control Register 200 * SASR0 Serial Audio I2S/MSB Interface & FIFO Status Register 201 * SASR1 Serial Audio AC-link Interface & FIFO Status Register 202 * SASCR Serial Audio Status Clear Register 203 * L3_CAR L3 Control Bus Address Register 204 * L3_CDR L3 Control Bus Data Register 205 * ACCAR AC-link Command Address Register 206 * ACCDR AC-link Command Data Register 207 * ACSAR AC-link Status Address Register 208 * ACSDR AC-link Status Data Register 209 * SADTCS Serial Audio DMA Transmit Control/Status Register 210 * SADTSA Serial Audio DMA Transmit Buffer Start Address A 211 * SADTCA Serial Audio DMA Transmit Buffer Count Register A 212 * SADTSB Serial Audio DMA Transmit Buffer Start Address B 213 * SADTCB Serial Audio DMA Transmit Buffer Count Register B 214 * SADRCS Serial Audio DMA Receive Control/Status Register 215 * SADRSA Serial Audio DMA Receive Buffer Start Address A 216 * SADRCA Serial Audio DMA Receive Buffer Count Register A 217 * SADRSB Serial Audio DMA Receive Buffer Start Address B 218 * SADRCB Serial Audio DMA Receive Buffer Count Register B 219 * SAITR Serial Audio Interrupt Test Register 220 * SADR Serial Audio Data Register (16 x 32-bit) 221 */ 222 223 #define _SACR0 _SA1111( 0x0600 ) 224 #define _SACR1 _SA1111( 0x0604 ) 225 #define _SACR2 _SA1111( 0x0608 ) 226 #define _SASR0 _SA1111( 0x060c ) 227 #define _SASR1 _SA1111( 0x0610 ) 228 #define _SASCR _SA1111( 0x0618 ) 229 #define _L3_CAR _SA1111( 0x061c ) 230 #define _L3_CDR _SA1111( 0x0620 ) 231 #define _ACCAR _SA1111( 0x0624 ) 232 #define _ACCDR _SA1111( 0x0628 ) 233 #define _ACSAR _SA1111( 0x062c ) 234 #define _ACSDR _SA1111( 0x0630 ) 235 #define _SADTCS _SA1111( 0x0634 ) 236 #define _SADTSA _SA1111( 0x0638 ) 237 #define _SADTCA _SA1111( 0x063c ) 238 #define _SADTSB _SA1111( 0x0640 ) 239 #define _SADTCB _SA1111( 0x0644 ) 240 #define _SADRCS _SA1111( 0x0648 ) 241 #define _SADRSA _SA1111( 0x064c ) 242 #define _SADRCA _SA1111( 0x0650 ) 243 #define _SADRSB _SA1111( 0x0654 ) 244 #define _SADRCB _SA1111( 0x0658 ) 245 #define _SAITR _SA1111( 0x065c ) 246 #define _SADR _SA1111( 0x0680 ) 247 248 #if LANGUAGE == C 249 250 #define SACR0 __CCREG(0x0600) 251 #define SACR1 __CCREG(0x0604) 252 #define SACR2 __CCREG(0x0608) 253 #define SASR0 __CCREG(0x060c) 254 #define SASR1 __CCREG(0x0610) 255 #define SASCR __CCREG(0x0618) 256 #define L3_CAR __CCREG(0x061c) 257 #define L3_CDR __CCREG(0x0620) 258 #define ACCAR __CCREG(0x0624) 259 #define ACCDR __CCREG(0x0628) 260 #define ACSAR __CCREG(0x062c) 261 #define ACSDR __CCREG(0x0630) 262 #define SADTCS __CCREG(0x0634) 263 #define SADTSA __CCREG(0x0638) 264 #define SADTCA __CCREG(0x063c) 265 #define SADTSB __CCREG(0x0640) 266 #define SADTCB __CCREG(0x0644) 267 #define SADRCS __CCREG(0x0648) 268 #define SADRSA __CCREG(0x064c) 269 #define SADRCA __CCREG(0x0650) 270 #define SADRSB __CCREG(0x0654) 271 #define SADRCB __CCREG(0x0658) 272 #define SAITR __CCREG(0x065c) 273 #define SADR __CCREG(0x0680) 274 275 #endif /* LANGUAGE == C */ 276 277 #define SACR0_ENB (1<<0) 278 #define SACR0_BCKD (1<<2) 279 #define SACR0_RST (1<<3) 280 281 #define SACR1_AMSL (1<<0) 282 #define SACR1_L3EN (1<<1) 283 #define SACR1_L3MB (1<<2) 284 #define SACR1_DREC (1<<3) 285 #define SACR1_DRPL (1<<4) 286 #define SACR1_ENLBF (1<<5) 287 288 #define SACR2_TS3V (1<<0) 289 #define SACR2_TS4V (1<<1) 290 #define SACR2_WKUP (1<<2) 291 #define SACR2_DREC (1<<3) 292 #define SACR2_DRPL (1<<4) 293 #define SACR2_ENLBF (1<<5) 294 #define SACR2_RESET (1<<6) 295 296 #define SASR0_TNF (1<<0) 297 #define SASR0_RNE (1<<1) 298 #define SASR0_BSY (1<<2) 299 #define SASR0_TFS (1<<3) 300 #define SASR0_RFS (1<<4) 301 #define SASR0_TUR (1<<5) 302 #define SASR0_ROR (1<<6) 303 #define SASR0_L3WD (1<<16) 304 #define SASR0_L3RD (1<<17) 305 306 #define SASR1_TNF (1<<0) 307 #define SASR1_RNE (1<<1) 308 #define SASR1_BSY (1<<2) 309 #define SASR1_TFS (1<<3) 310 #define SASR1_RFS (1<<4) 311 #define SASR1_TUR (1<<5) 312 #define SASR1_ROR (1<<6) 313 #define SASR1_CADT (1<<16) 314 #define SASR1_SADR (1<<17) 315 #define SASR1_RSTO (1<<18) 316 #define SASR1_CLPM (1<<19) 317 #define SASR1_CRDY (1<<20) 318 #define SASR1_RS3V (1<<21) 319 #define SASR1_RS4V (1<<22) 320 321 #define SASCR_TUR (1<<5) 322 #define SASCR_ROR (1<<6) 323 #define SASCR_DTS (1<<16) 324 #define SASCR_RDD (1<<17) 325 #define SASCR_STO (1<<18) 326 327 #define SADTCS_TDEN (1<<0) 328 #define SADTCS_TDIE (1<<1) 329 #define SADTCS_TDBDA (1<<3) 330 #define SADTCS_TDSTA (1<<4) 331 #define SADTCS_TDBDB (1<<5) 332 #define SADTCS_TDSTB (1<<6) 333 #define SADTCS_TBIU (1<<7) 334 335 #define SADRCS_RDEN (1<<0) 336 #define SADRCS_RDIE (1<<1) 337 #define SADRCS_RDBDA (1<<3) 338 #define SADRCS_RDSTA (1<<4) 339 #define SADRCS_RDBDB (1<<5) 340 #define SADRCS_RDSTB (1<<6) 341 #define SADRCS_RBIU (1<<7) 342 343 #define SAD_CS_DEN (1<<0) 344 #define SAD_CS_DIE (1<<1) /* Not functional on metal 1 */ 345 #define SAD_CS_DBDA (1<<3) /* Not functional on metal 1 */ 346 #define SAD_CS_DSTA (1<<4) 347 #define SAD_CS_DBDB (1<<5) /* Not functional on metal 1 */ 348 #define SAD_CS_DSTB (1<<6) 349 #define SAD_CS_BIU (1<<7) /* Not functional on metal 1 */ 350 351 #define SAITR_TFS (1<<0) 352 #define SAITR_RFS (1<<1) 353 #define SAITR_TUR (1<<2) 354 #define SAITR_ROR (1<<3) 355 #define SAITR_CADT (1<<4) 356 #define SAITR_SADR (1<<5) 357 #define SAITR_RSTO (1<<6) 358 #define SAITR_TDBDA (1<<8) 359 #define SAITR_TDBDB (1<<9) 360 #define SAITR_RDBDA (1<<10) 361 #define SAITR_RDBDB (1<<11) 362 363 /* 364 * General-Purpose I/O Interface 365 * 366 * Registers 367 * PA_DDR GPIO Block A Data Direction 368 * PA_DRR/PA_DWR GPIO Block A Data Value Register (read/write) 369 * PA_SDR GPIO Block A Sleep Direction 370 * PA_SSR GPIO Block A Sleep State 371 * PB_DDR GPIO Block B Data Direction 372 * PB_DRR/PB_DWR GPIO Block B Data Value Register (read/write) 373 * PB_SDR GPIO Block B Sleep Direction 374 * PB_SSR GPIO Block B Sleep State 375 * PC_DDR GPIO Block C Data Direction 376 * PC_DRR/PC_DWR GPIO Block C Data Value Register (read/write) 377 * PC_SDR GPIO Block C Sleep Direction 378 * PC_SSR GPIO Block C Sleep State 379 */ 380 381 #define _PA_DDR _SA1111( 0x1000 ) 382 #define _PA_DRR _SA1111( 0x1004 ) 383 #define _PA_DWR _SA1111( 0x1004 ) 384 #define _PA_SDR _SA1111( 0x1008 ) 385 #define _PA_SSR _SA1111( 0x100c ) 386 #define _PB_DDR _SA1111( 0x1010 ) 387 #define _PB_DRR _SA1111( 0x1014 ) 388 #define _PB_DWR _SA1111( 0x1014 ) 389 #define _PB_SDR _SA1111( 0x1018 ) 390 #define _PB_SSR _SA1111( 0x101c ) 391 #define _PC_DDR _SA1111( 0x1020 ) 392 #define _PC_DRR _SA1111( 0x1024 ) 393 #define _PC_DWR _SA1111( 0x1024 ) 394 #define _PC_SDR _SA1111( 0x1028 ) 395 #define _PC_SSR _SA1111( 0x102c ) 396 397 #if LANGUAGE == C 398 399 #define PA_DDR __CCREG(0x1000) 400 #define PA_DRR __CCREG(0x1004) 401 #define PA_DWR __CCREG(0x1004) 402 #define PA_SDR __CCREG(0x1008) 403 #define PA_SSR __CCREG(0x100c) 404 #define PB_DDR __CCREG(0x1010) 405 #define PB_DRR __CCREG(0x1014) 406 #define PB_DWR __CCREG(0x1014) 407 #define PB_SDR __CCREG(0x1018) 408 #define PB_SSR __CCREG(0x101c) 409 #define PC_DDR __CCREG(0x1020) 410 #define PC_DRR __CCREG(0x1024) 411 #define PC_DWR __CCREG(0x1024) 412 #define PC_SDR __CCREG(0x1028) 413 #define PC_SSR __CCREG(0x102c) 414 415 #endif /* LANGUAGE == C */ 416 417 /* 418 * Interrupt Controller 419 * 420 * Registers 421 * INTTEST0 Test register 0 422 * INTTEST1 Test register 1 423 * INTEN0 Interrupt Enable register 0 424 * INTEN1 Interrupt Enable register 1 425 * INTPOL0 Interrupt Polarity selection 0 426 * INTPOL1 Interrupt Polarity selection 1 427 * INTTSTSEL Interrupt source selection 428 * INTSTATCLR0 Interrupt Status/Clear 0 429 * INTSTATCLR1 Interrupt Status/Clear 1 430 * INTSET0 Interrupt source set 0 431 * INTSET1 Interrupt source set 1 432 * WAKE_EN0 Wake-up source enable 0 433 * WAKE_EN1 Wake-up source enable 1 434 * WAKE_POL0 Wake-up polarity selection 0 435 * WAKE_POL1 Wake-up polarity selection 1 436 */ 437 438 #define SA1111_INTTEST0 0x1600 439 #define SA1111_INTTEST1 0x1604 440 #define SA1111_INTEN0 0x1608 441 #define SA1111_INTEN1 0x160c 442 #define SA1111_INTPOL0 0x1610 443 #define SA1111_INTPOL1 0x1614 444 #define SA1111_INTTSTSEL 0x1618 445 #define SA1111_INTSTATCLR0 0x161c 446 #define SA1111_INTSTATCLR1 0x1620 447 #define SA1111_INTSET0 0x1624 448 #define SA1111_INTSET1 0x1628 449 #define SA1111_WAKE_EN0 0x162c 450 #define SA1111_WAKE_EN1 0x1630 451 #define SA1111_WAKE_POL0 0x1634 452 #define SA1111_WAKE_POL1 0x1638 453 454 #define _INTTEST0 _SA1111(SA1111_INTTEST0) 455 #define _INTTEST1 _SA1111(SA1111_INTTEST1) 456 #define _INTEN0 _SA1111(SA1111_INTEN0) 457 #define _INTEN1 _SA1111(SA1111_INTEN1) 458 #define _INTPOL0 _SA1111(SA1111_INTPOL0) 459 #define _INTPOL1 _SA1111(SA1111_INTPOL1) 460 #define _INTTSTSEL _SA1111(SA1111_INTTSTSEL) 461 #define _INTSTATCLR0 _SA1111(SA1111_INTSTATCLR0) 462 #define _INTSTATCLR1 _SA1111(SA1111_INTSTATCLR1) 463 #define _INTSET0 _SA1111(SA1111_INTSET0) 464 #define _INTSET1 _SA1111(SA1111_INTSET1) 465 #define _WAKE_EN0 _SA1111(SA1111_WAKE_EN0) 466 #define _WAKE_EN1 _SA1111(SA1111_WAKE_EN1) 467 #define _WAKE_POL0 _SA1111(SA1111_WAKE_POL0) 468 #define _WAKE_POL1 _SA1111(SA1111_WAKE_POL1) 469 470 #if LANGUAGE == C 471 472 #define INTTEST0 __CCREG(SA1111_INTTEST0) 473 #define INTTEST1 __CCREG(SA1111_INTTEST1) 474 #define INTEN0 __CCREG(SA1111_INTEN0) 475 #define INTEN1 __CCREG(SA1111_INTEN1) 476 #define INTPOL0 __CCREG(SA1111_INTPOL0) 477 #define INTPOL1 __CCREG(SA1111_INTPOL1) 478 #define INTTSTSEL __CCREG(SA1111_INTTSTSEL) 479 #define INTSTATCLR0 __CCREG(SA1111_INTSTATCLR0) 480 #define INTSTATCLR1 __CCREG(SA1111_INTSTATCLR1) 481 #define INTSET0 __CCREG(SA1111_INTSET0) 482 #define INTSET1 __CCREG(SA1111_INTSET1) 483 #define WAKE_EN0 __CCREG(SA1111_WAKE_EN0) 484 #define WAKE_EN1 __CCREG(SA1111_WAKE_EN1) 485 #define WAKE_POL0 __CCREG(SA1111_WAKE_POL0) 486 #define WAKE_POL1 __CCREG(SA1111_WAKE_POL1) 487 488 #endif /* LANGUAGE == C */ 489 490 /* 491 * PS/2 Trackpad and Mouse Interfaces 492 * 493 * Registers (prefix kbd applies to trackpad interface, mse to mouse) 494 * KBDCR Control Register 495 * KBDSTAT Status Register 496 * KBDDATA Transmit/Receive Data register 497 * KBDCLKDIV Clock Division Register 498 * KBDPRECNT Clock Precount Register 499 * KBDTEST1 Test register 1 500 * KBDTEST2 Test register 2 501 * KBDTEST3 Test register 3 502 * KBDTEST4 Test register 4 503 * MSECR 504 * MSESTAT 505 * MSEDATA 506 * MSECLKDIV 507 * MSEPRECNT 508 * MSETEST1 509 * MSETEST2 510 * MSETEST3 511 * MSETEST4 512 * 513 */ 514 515 #define _KBD( x ) _SA1111( 0x0A00 ) 516 #define _MSE( x ) _SA1111( 0x0C00 ) 517 518 #define _KBDCR _SA1111( 0x0A00 ) 519 #define _KBDSTAT _SA1111( 0x0A04 ) 520 #define _KBDDATA _SA1111( 0x0A08 ) 521 #define _KBDCLKDIV _SA1111( 0x0A0C ) 522 #define _KBDPRECNT _SA1111( 0x0A10 ) 523 #define _MSECR _SA1111( 0x0C00 ) 524 #define _MSESTAT _SA1111( 0x0C04 ) 525 #define _MSEDATA _SA1111( 0x0C08 ) 526 #define _MSECLKDIV _SA1111( 0x0C0C ) 527 #define _MSEPRECNT _SA1111( 0x0C10 ) 528 529 #if ( LANGUAGE == C ) 530 531 #define KBDCR __CCREG(0x0a00) 532 #define KBDSTAT __CCREG(0x0a04) 533 #define KBDDATA __CCREG(0x0a08) 534 #define KBDCLKDIV __CCREG(0x0a0c) 535 #define KBDPRECNT __CCREG(0x0a10) 536 #define MSECR __CCREG(0x0c00) 537 #define MSESTAT __CCREG(0x0c04) 538 #define MSEDATA __CCREG(0x0c08) 539 #define MSECLKDIV __CCREG(0x0c0c) 540 #define MSEPRECNT __CCREG(0x0c10) 541 542 #define KBDCR_ENA 0x08 543 #define KBDCR_FKD 0x02 544 #define KBDCR_FKC 0x01 545 546 #define KBDSTAT_TXE 0x80 547 #define KBDSTAT_TXB 0x40 548 #define KBDSTAT_RXF 0x20 549 #define KBDSTAT_RXB 0x10 550 #define KBDSTAT_ENA 0x08 551 #define KBDSTAT_RXP 0x04 552 #define KBDSTAT_KBD 0x02 553 #define KBDSTAT_KBC 0x01 554 555 #define KBDCLKDIV_DivVal Fld(4,0) 556 557 #define MSECR_ENA 0x08 558 #define MSECR_FKD 0x02 559 #define MSECR_FKC 0x01 560 561 #define MSESTAT_TXE 0x80 562 #define MSESTAT_TXB 0x40 563 #define MSESTAT_RXF 0x20 564 #define MSESTAT_RXB 0x10 565 #define MSESTAT_ENA 0x08 566 #define MSESTAT_RXP 0x04 567 #define MSESTAT_MSD 0x02 568 #define MSESTAT_MSC 0x01 569 570 #define MSECLKDIV_DivVal Fld(4,0) 571 572 #define KBDTEST1_CD 0x80 573 #define KBDTEST1_RC1 0x40 574 #define KBDTEST1_MC 0x20 575 #define KBDTEST1_C Fld(2,3) 576 #define KBDTEST1_T2 0x40 577 #define KBDTEST1_T1 0x20 578 #define KBDTEST1_T0 0x10 579 #define KBDTEST2_TICBnRES 0x08 580 #define KBDTEST2_RKC 0x04 581 #define KBDTEST2_RKD 0x02 582 #define KBDTEST2_SEL 0x01 583 #define KBDTEST3_ms_16 0x80 584 #define KBDTEST3_us_64 0x40 585 #define KBDTEST3_us_16 0x20 586 #define KBDTEST3_DIV8 0x10 587 #define KBDTEST3_DIn 0x08 588 #define KBDTEST3_CIn 0x04 589 #define KBDTEST3_KD 0x02 590 #define KBDTEST3_KC 0x01 591 #define KBDTEST4_BC12 0x80 592 #define KBDTEST4_BC11 0x40 593 #define KBDTEST4_TRES 0x20 594 #define KBDTEST4_CLKOE 0x10 595 #define KBDTEST4_CRES 0x08 596 #define KBDTEST4_RXB 0x04 597 #define KBDTEST4_TXB 0x02 598 #define KBDTEST4_SRX 0x01 599 600 #define MSETEST1_CD 0x80 601 #define MSETEST1_RC1 0x40 602 #define MSETEST1_MC 0x20 603 #define MSETEST1_C Fld(2,3) 604 #define MSETEST1_T2 0x40 605 #define MSETEST1_T1 0x20 606 #define MSETEST1_T0 0x10 607 #define MSETEST2_TICBnRES 0x08 608 #define MSETEST2_RKC 0x04 609 #define MSETEST2_RKD 0x02 610 #define MSETEST2_SEL 0x01 611 #define MSETEST3_ms_16 0x80 612 #define MSETEST3_us_64 0x40 613 #define MSETEST3_us_16 0x20 614 #define MSETEST3_DIV8 0x10 615 #define MSETEST3_DIn 0x08 616 #define MSETEST3_CIn 0x04 617 #define MSETEST3_KD 0x02 618 #define MSETEST3_KC 0x01 619 #define MSETEST4_BC12 0x80 620 #define MSETEST4_BC11 0x40 621 #define MSETEST4_TRES 0x20 622 #define MSETEST4_CLKOE 0x10 623 #define MSETEST4_CRES 0x08 624 #define MSETEST4_RXB 0x04 625 #define MSETEST4_TXB 0x02 626 #define MSETEST4_SRX 0x01 627 628 #endif /* LANGUAGE == C */ 629 630 /* 631 * PCMCIA Interface 632 * 633 * Registers 634 * PCSR Status Register 635 * PCCR Control Register 636 * PCSSR Sleep State Register 637 */ 638 639 #define _PCCR _SA1111( 0x1800 ) 640 #define _PCSSR _SA1111( 0x1804 ) 641 #define _PCSR _SA1111( 0x1808 ) 642 643 #if LANGUAGE == C 644 645 #define PCCR __CCREG(0x1800) 646 #define PCSSR __CCREG(0x1804) 647 #define PCSR __CCREG(0x1808) 648 649 #endif /* LANGUAGE == C */ 650 651 #define PCSR_S0_READY (1<<0) 652 #define PCSR_S1_READY (1<<1) 653 #define PCSR_S0_DETECT (1<<2) 654 #define PCSR_S1_DETECT (1<<3) 655 #define PCSR_S0_VS1 (1<<4) 656 #define PCSR_S0_VS2 (1<<5) 657 #define PCSR_S1_VS1 (1<<6) 658 #define PCSR_S1_VS2 (1<<7) 659 #define PCSR_S0_WP (1<<8) 660 #define PCSR_S1_WP (1<<9) 661 #define PCSR_S0_BVD1 (1<<10) 662 #define PCSR_S0_BVD2 (1<<11) 663 #define PCSR_S1_BVD1 (1<<12) 664 #define PCSR_S1_BVD2 (1<<13) 665 666 #define PCCR_S0_RST (1<<0) 667 #define PCCR_S1_RST (1<<1) 668 #define PCCR_S0_FLT (1<<2) 669 #define PCCR_S1_FLT (1<<3) 670 #define PCCR_S0_PWAITEN (1<<4) 671 #define PCCR_S1_PWAITEN (1<<5) 672 #define PCCR_S0_PSE (1<<6) 673 #define PCCR_S1_PSE (1<<7) 674 675 #define PCSSR_S0_SLEEP (1<<0) 676 #define PCSSR_S1_SLEEP (1<<1) 677 678 int sa1111_check_dma_bug(dma_addr_t addr); 679 680 #endif /* _ASM_ARCH_SA1111 */ 681