1 /* Driver for Realtek RTS51xx USB card reader
2 * Header file
3 *
4 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2, or (at your option) any
9 * later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
18 *
19 * Author:
20 * wwang (wei_wang@realsil.com.cn)
21 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
22 * Maintainer:
23 * Edwin Rong (edwin_rong@realsil.com.cn)
24 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
25 */
26
27 #ifndef __RTS51X_CHIP_H
28 #define __RTS51X_CHIP_H
29
30 #include <linux/usb.h>
31 #include <linux/usb_usual.h>
32 #include <linux/blkdev.h>
33 #include <linux/completion.h>
34 #include <linux/mutex.h>
35 #include <scsi/scsi_host.h>
36
37 #include "trace.h"
38
39 #define SUPPORT_CPRM
40 #define SUPPORT_MAGIC_GATE
41 #define SUPPORT_MSXC
42 /* #define LED_AUTO_BLINK */
43
44 /* { wwang, 2010-07-26
45 * Add support for SD lock/unlock */
46 /* #define SUPPORT_SD_LOCK */
47 /* } wwang, 2010-07-26 */
48
49 #ifdef SUPPORT_MAGIC_GA
50 /* Using NORMAL_WRITE instead of AUTO_WRITE to set ICVTE */
51 #define MG_SET_ICV_SLOW
52 #endif
53
54 #ifdef SUPPORT_MSXC
55 #define XC_POWERCLASS
56 #define SUPPORT_PCGL_1P18
57 #endif
58
59 #define GET_CARD_STATUS_USING_EPC
60
61 #define CLOSE_SSC_POWER
62
63 #define SUPPORT_OCP
64
65 #define MS_SPEEDUP
66 /* #define XD_SPEEDUP */
67
68 #define SD_XD_IO_FOLLOW_PWR
69
70 #define SD_NR 2
71 #define MS_NR 3
72 #define XD_NR 4
73 #define SD_CARD (1 << SD_NR)
74 #define MS_CARD (1 << MS_NR)
75 #define XD_CARD (1 << XD_NR)
76
77 #define SD_CD 0x01
78 #define MS_CD 0x02
79 #define XD_CD 0x04
80 #define SD_WP 0x08
81
82 #define MAX_ALLOWED_LUN_CNT 8
83 #define CMD_BUF_LEN 1024
84 #define RSP_BUF_LEN 1024
85 #define POLLING_INTERVAL 50 /* 50ms */
86
87 #define XD_FREE_TABLE_CNT 1200
88 #define MS_FREE_TABLE_CNT 512
89
90 /* Bit Operation */
91 #define SET_BIT(data, idx) ((data) |= 1 << (idx))
92 #define CLR_BIT(data, idx) ((data) &= ~(1 << (idx)))
93 #define CHK_BIT(data, idx) ((data) & (1 << (idx)))
94
95 /* Command type */
96 #define READ_REG_CMD 0
97 #define WRITE_REG_CMD 1
98 #define CHECK_REG_CMD 2
99
100 #define PACKET_TYPE 4
101 #define CNT_H 5
102 #define CNT_L 6
103 #define STAGE_FLAG 7
104 #define CMD_OFFSET 8
105
106 /* Packet type */
107 #define BATCH_CMD 0
108 #define SEQ_READ 1
109 #define SEQ_WRITE 2
110
111 /* Stage flag */
112 #define STAGE_R 0x01
113 #define STAGE_DI 0x02
114 #define STAGE_DO 0x04
115 /* Return MS_TRANS_CFG, GET_INT */
116 #define STAGE_MS_STATUS 0x08
117 /* Return XD_CFG, XD_CTL, XD_PAGE_STATUS */
118 #define STAGE_XD_STATUS 0x10
119 /* Command stage mode */
120 #define MODE_C 0x00
121 #define MODE_CR (STAGE_R)
122 #define MODE_CDIR (STAGE_R | STAGE_DI)
123 #define MODE_CDOR (STAGE_R | STAGE_DO)
124
125 /* Function return code */
126 #ifndef STATUS_SUCCESS
127 #define STATUS_SUCCESS 0
128 #endif
129
130 #define STATUS_FAIL 1
131 #define STATUS_READ_FAIL 2
132 #define STATUS_WRITE_FAIL 3
133 #define STATUS_TIMEDOUT 4
134 #define STATUS_NOMEM 5
135 #define STATUS_TRANS_SHORT 6
136 #define STATUS_TRANS_LONG 7
137 #define STATUS_STALLED 8
138 #define STATUS_ERROR 10
139
140 #define IDLE_MAX_COUNT 10
141 #define POLLING_WAIT_CNT 1
142 #define DELINK_DELAY 100
143 #define LED_TOGGLE_INTERVAL 6
144 #define LED_GPIO 0
145
146 /* package */
147 #define QFN24 0
148 #define LQFP48 1
149
150 #define USB_11 0
151 #define USB_20 1
152
153 /*
154 * Transport return codes
155 */
156 /* Transport good, command good */
157 #define TRANSPORT_GOOD 0
158 /* Transport good, command failed */
159 #define TRANSPORT_FAILED 1
160 /* Command failed, no auto-sense */
161 #define TRANSPORT_NO_SENSE 2
162 /* Transport bad (i.e. device dead) */
163 #define TRANSPORT_ERROR 3
164
165 /* Supported Clock */
166 enum card_clock { CLK_20 = 1, CLK_30, CLK_40, CLK_50, CLK_60, CLK_80, CLK_100 };
167
168 #ifdef _MSG_TRACE
169
170 #define TRACE_ITEM_CNT 64
171
172 struct trace_msg_t {
173 u16 line;
174 #define MSG_FUNC_LEN 64
175 char func[MSG_FUNC_LEN];
176 #define MSG_FILE_LEN 32
177 char file[MSG_FILE_LEN];
178 #define TIME_VAL_LEN 16
179 u8 timeval_buf[TIME_VAL_LEN];
180 u8 valid;
181 };
182
183 #endif /* _MSG_TRACE */
184
185 /* Size of the autosense data buffer */
186 #define SENSE_SIZE 18
187
188 /* Sense type */
189 #define SENSE_TYPE_NO_SENSE 0
190 #define SENSE_TYPE_MEDIA_CHANGE 1
191 #define SENSE_TYPE_MEDIA_NOT_PRESENT 2
192 #define SENSE_TYPE_MEDIA_LBA_OVER_RANGE 3
193 #define SENSE_TYPE_MEDIA_LUN_NOT_SUPPORT 4
194 #define SENSE_TYPE_MEDIA_WRITE_PROTECT 5
195 #define SENSE_TYPE_MEDIA_INVALID_CMD_FIELD 6
196 #define SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR 7
197 #define SENSE_TYPE_MEDIA_WRITE_ERR 8
198 #define SENSE_TYPE_FORMAT_IN_PROGRESS 9
199 #define SENSE_TYPE_FORMAT_CMD_FAILED 10
200 #ifdef SUPPORT_MAGIC_GATE
201 /* COPY PROTECTION KEY EXCHANGE FAILURE - KEY NOT ESTABLISHED */
202 #define SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB 0x0b
203 /* COPY PROTECTION KEY EXCHANGE FAILURE - AUTHENTICATION FAILURE */
204 #define SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN 0x0c
205 /* INCOMPATIBLE MEDIUM INSTALLED */
206 #define SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM 0x0d
207 /* WRITE ERROR */
208 #define SENSE_TYPE_MG_WRITE_ERR 0x0e
209 #endif
210 #ifdef SUPPORT_SD_LOCK
211 /* FOR Locked SD card */
212 #define SENSE_TYPE_MEDIA_READ_FORBIDDEN 0x10
213 #endif
214
215 /*---- sense key ----*/
216 #define ILI 0x20 /* ILI bit is on */
217
218 #define NO_SENSE 0x00 /* not exist sense key */
219 #define RECOVER_ERR 0x01 /* Target/Logical unit is recoverd */
220 #define NOT_READY 0x02 /* Logical unit is not ready */
221 #define MEDIA_ERR 0x03 /* medium/data error */
222 #define HARDWARE_ERR 0x04 /* hardware error */
223 #define ILGAL_REQ 0x05 /* CDB/parameter/identify msg error */
224 #define UNIT_ATTENTION 0x06 /* unit attention condition occur */
225 #define DAT_PRTCT 0x07 /* read/write is desable */
226 #define BLNC_CHK 0x08 /* find blank/DOF in read */
227 /* write to unblank area */
228 #define CPY_ABRT 0x0a /* Copy/Compare/Copy&Verify illgal */
229 #define ABRT_CMD 0x0b /* Target make the command in error */
230 #define EQUAL 0x0c /* Search Data end with Equal */
231 #define VLM_OVRFLW 0x0d /* Some data are left in buffer */
232 #define MISCMP 0x0e /* find inequality */
233
234 /*-----------------------------------
235 SENSE_DATA
236 -----------------------------------*/
237 /*---- valid ----*/
238 #define SENSE_VALID 0x80 /* Sense data is valid as SCSI2 */
239 #define SENSE_INVALID 0x00 /* Sense data is invalid as SCSI2 */
240
241 /*---- error code ----*/
242 #define CUR_ERR 0x70 /* current error */
243 #define DEF_ERR 0x71 /* specific command error */
244
245 /*---- sense key Infomation ----*/
246 #define SNSKEYINFO_LEN 3 /* length of sense key infomation */
247
248 #define SKSV 0x80
249 #define CDB_ILLEGAL 0x40
250 #define DAT_ILLEGAL 0x00
251 #define BPV 0x08
252 #define BIT_ILLEGAL0 0 /* bit0 is illegal */
253 #define BIT_ILLEGAL1 1 /* bit1 is illegal */
254 #define BIT_ILLEGAL2 2 /* bit2 is illegal */
255 #define BIT_ILLEGAL3 3 /* bit3 is illegal */
256 #define BIT_ILLEGAL4 4 /* bit4 is illegal */
257 #define BIT_ILLEGAL5 5 /* bit5 is illegal */
258 #define BIT_ILLEGAL6 6 /* bit6 is illegal */
259 #define BIT_ILLEGAL7 7 /* bit7 is illegal */
260
261 /*---- ASC ----*/
262 #define ASC_NO_INFO 0x00
263 #define ASC_MISCMP 0x1d
264 #define ASC_INVLD_CDB 0x24
265 #define ASC_INVLD_PARA 0x26
266 #define ASC_LU_NOT_READY 0x04
267 #define ASC_WRITE_ERR 0x0c
268 #define ASC_READ_ERR 0x11
269 #define ASC_LOAD_EJCT_ERR 0x53
270 #define ASC_MEDIA_NOT_PRESENT 0x3A
271 #define ASC_MEDIA_CHANGED 0x28
272 #define ASC_MEDIA_IN_PROCESS 0x04
273 #define ASC_WRITE_PROTECT 0x27
274 #define ASC_LUN_NOT_SUPPORTED 0x25
275
276 /*---- ASQC ----*/
277 #define ASCQ_NO_INFO 0x00
278 #define ASCQ_MEDIA_IN_PROCESS 0x01
279 #define ASCQ_MISCMP 0x00
280 #define ASCQ_INVLD_CDB 0x00
281 #define ASCQ_INVLD_PARA 0x02
282 #define ASCQ_LU_NOT_READY 0x02
283 #define ASCQ_WRITE_ERR 0x02
284 #define ASCQ_READ_ERR 0x00
285 #define ASCQ_LOAD_EJCT_ERR 0x00
286 #define ASCQ_WRITE_PROTECT 0x00
287
288 struct sense_data_t {
289 unsigned char err_code; /* error code */
290 /* bit7 : valid */
291 /* (1 : SCSI2) */
292 /* (0 : Vendor specific) */
293 /* bit6-0 : error code */
294 /* (0x70 : current error) */
295 /* (0x71 : specific command error) */
296 unsigned char seg_no; /* segment No. */
297 unsigned char sense_key; /* byte5 : ILI */
298 /* bit3-0 : sense key */
299 unsigned char info[4]; /* infomation */
300 unsigned char ad_sense_len; /* additional sense data length */
301 unsigned char cmd_info[4]; /* command specific infomation */
302 unsigned char asc; /* ASC */
303 unsigned char ascq; /* ASCQ */
304 unsigned char rfu; /* FRU */
305 unsigned char sns_key_info[3]; /* sense key specific infomation */
306 };
307
308 /* sd_ctl bit map */
309 /* SD push point control, bit 0, 1 */
310 #define SD_PUSH_POINT_CTL_MASK 0x03
311 #define SD_PUSH_POINT_DELAY 0x01
312 #define SD_PUSH_POINT_AUTO 0x02
313 /* SD sample point control, bit 2, 3 */
314 #define SD_SAMPLE_POINT_CTL_MASK 0x0C
315 #define SD_SAMPLE_POINT_DELAY 0x04
316 #define SD_SAMPLE_POINT_AUTO 0x08
317 /* SD DDR Tx phase set by user, bit 4 */
318 #define SD_DDR_TX_PHASE_SET_BY_USER 0x10
319 /* MMC DDR Tx phase set by user, bit 5 */
320 #define MMC_DDR_TX_PHASE_SET_BY_USER 0x20
321 /* Support MMC DDR mode, bit 6 */
322 /*#define SUPPORT_MMC_DDR_MODE 0x40 */
323 #define SUPPORT_UHS50_MMC44 0x40
324
325 struct rts51x_option {
326 u8 led_blink_speed;
327
328 int mspro_formatter_enable;
329
330 /* card clock expected by user for fpga platform */
331 int fpga_sd_sdr104_clk;
332 int fpga_sd_ddr50_clk;
333 int fpga_sd_sdr50_clk;
334 int fpga_sd_hs_clk;
335 int fpga_mmc_52m_clk;
336 int fpga_ms_hg_clk;
337 int fpga_ms_4bit_clk;
338
339 /* card clock expected by user for asic platform */
340 int asic_sd_sdr104_clk;
341 int asic_sd_ddr50_clk;
342 int asic_sd_sdr50_clk;
343 int asic_sd_hs_clk;
344 int asic_mmc_52m_clk;
345 int asic_ms_hg_clk;
346 int asic_ms_4bit_clk;
347
348 u8 ssc_depth_sd_sdr104; /* sw */
349 u8 ssc_depth_sd_ddr50; /* sw */
350 u8 ssc_depth_sd_sdr50; /* sw */
351 u8 ssc_depth_sd_hs; /* sw */
352 u8 ssc_depth_mmc_52m; /* sw */
353 u8 ssc_depth_ms_hg; /* sw */
354 u8 ssc_depth_ms_4bit; /* sw */
355 u8 ssc_depth_low_speed; /* sw */
356
357 /* SD/MMC Tx phase */
358 int sd_ddr_tx_phase; /* Enabled by bit 4 of sd_ctl */
359 int mmc_ddr_tx_phase; /* Enabled by bit 5 of sd_ctl */
360
361 /* priority of choosing sd speed funciton */
362 u32 sd_speed_prior;
363
364 /* sd card control */
365 u32 sd_ctl;
366
367 /* Enable Selective Suspend */
368 int ss_en;
369 /* Interval to enter SS from IDLE state (second) */
370 int ss_delay;
371 int needs_remote_wakeup;
372 u8 ww_enable; /* sangdy2010-08-03:add for remote wakeup */
373
374 /* Enable SSC clock */
375 int ssc_en;
376
377 int auto_delink_en;
378
379 /* sangdy2010-07-13:add FT2 fast mode */
380 int FT2_fast_mode;
381 /* sangdy2010-07-15:
382 * add for config delay between 1/4 PMOS and 3/4 PMOS */
383 int pwr_delay;
384
385 int xd_rw_step; /* add to tune xd tRP */
386 int D3318_off_delay; /* add to tune D3318 off delay time */
387 int delink_delay; /* add to tune delink delay time */
388 /* add for rts5129 to enable/disable D3318 off */
389 u8 rts5129_D3318_off_enable;
390 u8 sd20_pad_drive; /* add to config SD20 PAD drive */
391 u8 sd30_pad_drive; /* add to config SD30 pad drive */
392 /*if reset or rw fail,then set SD20 pad drive again */
393 u8 reset_or_rw_fail_set_pad_drive;
394
395 u8 rcc_fail_flag; /* add to indicate whether rcc bug happen */
396 u8 rcc_bug_fix_en; /* if set,then support fixing rcc bug */
397 u8 debounce_num; /* debounce number */
398 int polling_time; /* polling delay time */
399 u8 led_toggle_interval; /* used to control led toggle speed */
400 int xd_rwn_step;
401 u8 sd_send_status_en;
402 /* used to store default phase which is
403 * used when phase tune all pass. */
404 u8 ddr50_tx_phase;
405 u8 ddr50_rx_phase;
406 u8 sdr50_tx_phase;
407 u8 sdr50_rx_phase;
408 /* used to enable select sdr50 tx phase according to proportion. */
409 u8 sdr50_phase_sel;
410 u8 ms_errreg_fix;
411 u8 reset_mmc_first;
412 u8 speed_mmc; /* when set, then try CMD55 only twice */
413 u8 led_always_on; /* if set, then led always on when card exist */
414 u8 dv18_voltage; /* add to tune dv18 voltage */
415 };
416
417 #define MS_FORMATTER_ENABLED(chip) ((chip)->option.mspro_formatter_enable)
418
419 struct rts51x_chip;
420
421 typedef int (*card_rw_func) (struct scsi_cmnd *srb, struct rts51x_chip *chip,
422 u32 sec_addr, u16 sec_cnt);
423
424 /* For MS Card */
425 #define MAX_DEFECTIVE_BLOCK 10
426
427 struct zone_entry {
428 u16 *l2p_table;
429 u16 *free_table;
430 u16 defect_list[MAX_DEFECTIVE_BLOCK]; /* For MS card only */
431 int set_index;
432 int get_index;
433 int unused_blk_cnt;
434 int disable_count;
435 /* To indicate whether the L2P table of this zone has been built. */
436 int build_flag;
437 };
438
439 struct xd_delay_write_tag {
440 u32 old_phyblock;
441 u32 new_phyblock;
442 u32 logblock;
443 u8 pageoff;
444 u8 delay_write_flag;
445 };
446
447 struct xd_info {
448 u8 maker_code;
449 u8 device_code;
450 u8 block_shift;
451 u8 page_off;
452 u8 addr_cycle;
453 u16 cis_block;
454 u8 multi_flag;
455 u8 err_code;
456 u32 capacity;
457
458 struct zone_entry *zone;
459 int zone_cnt;
460
461 struct xd_delay_write_tag delay_write;
462
463 int counter;
464
465 int xd_clock;
466 };
467
468 #define TYPE_SD 0x0000
469 #define TYPE_MMC 0x0001
470
471 /* TYPE_SD */
472 #define SD_HS 0x0100
473 #define SD_SDR50 0x0200
474 #define SD_DDR50 0x0400
475 #define SD_SDR104 0x0800
476 #define SD_HCXC 0x1000
477
478 /* TYPE_MMC */
479 #define MMC_26M 0x0100
480 #define MMC_52M 0x0200
481 #define MMC_4BIT 0x0400
482 #define MMC_8BIT 0x0800
483 #define MMC_SECTOR_MODE 0x1000
484 #define MMC_DDR52 0x2000
485
486 /* SD card */
487 #define CHK_SD(sd_card) (((sd_card)->sd_type & 0xFF) == TYPE_SD)
488 #define CHK_SD_HS(sd_card) \
489 (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_HS))
490 #define CHK_SD_SDR50(sd_card) \
491 (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_SDR50))
492 #define CHK_SD_DDR50(sd_card) \
493 (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_DDR50))
494 #define CHK_SD_SDR104(sd_card) \
495 (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_SDR104))
496 #define CHK_SD_HCXC(sd_card) \
497 (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_HCXC))
498 #define CHK_SD30_SPEED(sd_card) \
499 (CHK_SD_SDR50(sd_card) || CHK_SD_DDR50(sd_card) ||\
500 CHK_SD_SDR104(sd_card))
501
502 #define SET_SD(sd_card) ((sd_card)->sd_type = TYPE_SD)
503 #define SET_SD_HS(sd_card) ((sd_card)->sd_type |= SD_HS)
504 #define SET_SD_SDR50(sd_card) ((sd_card)->sd_type |= SD_SDR50)
505 #define SET_SD_DDR50(sd_card) ((sd_card)->sd_type |= SD_DDR50)
506 #define SET_SD_SDR104(sd_card) ((sd_card)->sd_type |= SD_SDR104)
507 #define SET_SD_HCXC(sd_card) ((sd_card)->sd_type |= SD_HCXC)
508
509 #define CLR_SD_HS(sd_card) ((sd_card)->sd_type &= ~SD_HS)
510 #define CLR_SD_SDR50(sd_card) ((sd_card)->sd_type &= ~SD_SDR50)
511 #define CLR_SD_DDR50(sd_card) ((sd_card)->sd_type &= ~SD_DDR50)
512 #define CLR_SD_SDR104(sd_card) ((sd_card)->sd_type &= ~SD_SDR104)
513 #define CLR_SD_HCXC(sd_card) ((sd_card)->sd_type &= ~SD_HCXC)
514 #define CLR_SD30_SPEED(sd_card) \
515 ((sd_card)->sd_type &= ~(SD_SDR50|SD_DDR50|SD_SDR104))
516
517 /* MMC card */
518 #define CHK_MMC(sd_card) \
519 (((sd_card)->sd_type & 0xFF) == TYPE_MMC)
520 #define CHK_MMC_26M(sd_card) \
521 (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_26M))
522 #define CHK_MMC_52M(sd_card) \
523 (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_52M))
524 #define CHK_MMC_4BIT(sd_card) \
525 (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_4BIT))
526 #define CHK_MMC_8BIT(sd_card) \
527 (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_8BIT))
528 #define CHK_MMC_SECTOR_MODE(sd_card)\
529 (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_SECTOR_MODE))
530 #define CHK_MMC_DDR52(sd_card) \
531 (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_DDR52))
532
533 #define SET_MMC(sd_card) ((sd_card)->sd_type = TYPE_MMC)
534 #define SET_MMC_26M(sd_card) ((sd_card)->sd_type |= MMC_26M)
535 #define SET_MMC_52M(sd_card) ((sd_card)->sd_type |= MMC_52M)
536 #define SET_MMC_4BIT(sd_card) ((sd_card)->sd_type |= MMC_4BIT)
537 #define SET_MMC_8BIT(sd_card) ((sd_card)->sd_type |= MMC_8BIT)
538 #define SET_MMC_SECTOR_MODE(sd_card) ((sd_card)->sd_type |= MMC_SECTOR_MODE)
539 #define SET_MMC_DDR52(sd_card) ((sd_card)->sd_type |= MMC_DDR52)
540
541 #define CLR_MMC_26M(sd_card) ((sd_card)->sd_type &= ~MMC_26M)
542 #define CLR_MMC_52M(sd_card) ((sd_card)->sd_type &= ~MMC_52M)
543 #define CLR_MMC_4BIT(sd_card) ((sd_card)->sd_type &= ~MMC_4BIT)
544 #define CLR_MMC_8BIT(sd_card) ((sd_card)->sd_type &= ~MMC_8BIT)
545 #define CLR_MMC_SECTOR_MODE(sd_card) ((sd_card)->sd_type &= ~MMC_SECTOR_MODE)
546 #define CLR_MMC_DDR52(sd_card) ((sd_card)->sd_type &= ~MMC_DDR52)
547
548 #define CHK_MMC_HS(sd_card) \
549 (CHK_MMC_52M(sd_card) && CHK_MMC_26M(sd_card))
550 #define CLR_MMC_HS(sd_card) \
551 do { \
552 CLR_MMC_DDR52(sd_card); \
553 CLR_MMC_52M(sd_card); \
554 CLR_MMC_26M(sd_card); \
555 } while (0)
556
557 #define SD_SUPPORT_CLASS_TEN 0x01
558 #define SD_SUPPORT_1V8 0x02
559
560 #define SD_SET_CLASS_TEN(sd_card) \
561 ((sd_card)->sd_setting |= SD_SUPPORT_CLASS_TEN)
562 #define SD_CHK_CLASS_TEN(sd_card) \
563 ((sd_card)->sd_setting & SD_SUPPORT_CLASS_TEN)
564 #define SD_CLR_CLASS_TEN(sd_card) \
565 ((sd_card)->sd_setting &= ~SD_SUPPORT_CLASS_TEN)
566 #define SD_SET_1V8(sd_card) \
567 ((sd_card)->sd_setting |= SD_SUPPORT_1V8)
568 #define SD_CHK_1V8(sd_card) \
569 ((sd_card)->sd_setting & SD_SUPPORT_1V8)
570 #define SD_CLR_1V8(sd_card) \
571 ((sd_card)->sd_setting &= ~SD_SUPPORT_1V8)
572 #define CLR_RETRY_SD20_MODE(sd_card) \
573 ((sd_card)->retry_SD20_mode = 0)
574 #define SET_RETRY_SD20_MODE(sd_card) \
575 ((sd_card)->retry_SD20_mode = 1)
576 #define CHK_RETRY_SD20_MODE(sd_card) \
577 ((sd_card)->retry_SD20_mode == 1)
578
579 struct sd_info {
580 u16 sd_type;
581 u8 err_code;
582 u8 sd_data_buf_ready;
583 u32 sd_addr;
584 u32 capacity;
585
586 u8 raw_csd[16];
587 u8 raw_scr[8];
588
589 /* Sequential RW */
590 int seq_mode;
591 enum dma_data_direction pre_dir;
592 u32 pre_sec_addr;
593 u16 pre_sec_cnt;
594
595 int counter;
596
597 int sd_clock;
598
599 #ifdef SUPPORT_CPRM
600 int sd_pass_thru_en;
601 int pre_cmd_err;
602 u8 last_rsp_type;
603 u8 rsp[17];
604 #endif
605
606 u8 func_group1_mask;
607 u8 func_group2_mask;
608 u8 func_group3_mask;
609 u8 func_group4_mask;
610
611 u8 sd_switch_fail;
612 u8 sd_read_phase;
613 u8 retry_SD20_mode; /* sangdy2010-06-10 */
614 u8 sd_reset_fail; /* sangdy2010-07-01 */
615 u8 sd_send_status_en;
616
617 #ifdef SUPPORT_SD_LOCK
618 u8 sd_lock_status;
619 u8 sd_erase_status;
620 u8 sd_lock_notify;
621 #endif
622 };
623
624 #define MODE_512_SEQ 0x01
625 #define MODE_2K_SEQ 0x02
626
627 #define TYPE_MS 0x0000
628 #define TYPE_MSPRO 0x0001
629
630 #define MS_4BIT 0x0100
631 #define MS_8BIT 0x0200
632 #define MS_HG 0x0400
633 #define MS_XC 0x0800
634
635 #define HG8BIT (MS_HG | MS_8BIT)
636
637 #define CHK_MSPRO(ms_card) \
638 (((ms_card)->ms_type & 0xFF) == TYPE_MSPRO)
639 #define CHK_HG8BIT(ms_card) \
640 (CHK_MSPRO(ms_card) && (((ms_card)->ms_type & HG8BIT) == HG8BIT))
641 #define CHK_MSXC(ms_card) \
642 (CHK_MSPRO(ms_card) && ((ms_card)->ms_type & MS_XC))
643 #define CHK_MSHG(ms_card) \
644 (CHK_MSPRO(ms_card) && ((ms_card)->ms_type & MS_HG))
645
646 #define CHK_MS8BIT(ms_card) (((ms_card)->ms_type & MS_8BIT))
647 #define CHK_MS4BIT(ms_card) (((ms_card)->ms_type & MS_4BIT))
648
649 struct ms_delay_write_tag {
650 u16 old_phyblock;
651 u16 new_phyblock;
652 u16 logblock;
653 u8 pageoff;
654 u8 delay_write_flag;
655 };
656
657 struct ms_info {
658 u16 ms_type;
659 u8 block_shift;
660 u8 page_off;
661 u16 total_block;
662 u16 boot_block;
663 u32 capacity;
664
665 u8 check_ms_flow;
666 u8 switch_8bit_fail;
667 u8 err_code;
668
669 struct zone_entry *segment;
670 int segment_cnt;
671
672 int pro_under_formatting;
673 int format_status;
674 u16 progress;
675 u8 raw_sys_info[96];
676 #ifdef SUPPORT_PCGL_1P18
677 u8 raw_model_name[48];
678 #endif
679
680 u8 multi_flag;
681
682 /* Sequential RW */
683 u8 seq_mode;
684 enum dma_data_direction pre_dir;
685 u32 pre_sec_addr;
686 u16 pre_sec_cnt;
687 u32 total_sec_cnt;
688 u8 last_rw_int;
689
690 struct ms_delay_write_tag delay_write;
691
692 int counter;
693
694 int ms_clock;
695
696 #ifdef SUPPORT_MAGIC_GATE
697 u8 magic_gate_id[16];
698 u8 mg_entry_num;
699 int mg_auth; /* flag to indicate authentication process */
700 #endif
701 };
702
703 #define PRO_UNDER_FORMATTING(ms_card) \
704 ((ms_card)->pro_under_formatting)
705 #define SET_FORMAT_STATUS(ms_card, status) \
706 ((ms_card)->format_status = (status))
707 #define CHK_FORMAT_STATUS(ms_card, status) \
708 ((ms_card)->format_status == (status))
709
710 struct scsi_cmnd;
711
712 enum CHIP_STAT { STAT_INIT, STAT_IDLE, STAT_RUN, STAT_SS_PRE, STAT_SS,
713 STAT_SUSPEND };
714
715 struct rts51x_chip {
716 u16 vendor_id;
717 u16 product_id;
718 char max_lun;
719
720 struct scsi_cmnd *srb;
721 struct sense_data_t sense_buffer[MAX_ALLOWED_LUN_CNT];
722
723 #ifndef LED_AUTO_BLINK
724 int led_toggle_counter;
725 #endif
726 int ss_counter;
727 int idle_counter;
728 int auto_delink_counter;
729 enum CHIP_STAT chip_stat;
730
731 int resume_from_scsi;
732
733 /* Card information */
734 struct xd_info xd_card;
735 struct sd_info sd_card;
736 struct ms_info ms_card;
737
738 int cur_clk; /* current card clock */
739 int cur_card; /* Current card module */
740
741 u8 card_exist; /* card exist bit map (physical exist) */
742 u8 card_ready; /* card ready bit map (reset successfully) */
743 u8 card_fail; /* card reset fail bit map */
744 u8 card_ejected; /* card ejected bit map */
745 u8 card_wp; /* card write protected bit map */
746
747 u8 fake_card_ready;
748 /* flag to indicate whether to answer MediaChange */
749 unsigned long lun_mc;
750
751 /* card bus width */
752 u8 card_bus_width[MAX_ALLOWED_LUN_CNT];
753 /* card capacity */
754 u32 capacity[MAX_ALLOWED_LUN_CNT];
755
756 /* read/write card function pointer */
757 card_rw_func rw_card[MAX_ALLOWED_LUN_CNT];
758 /* read/write capacity, used for GPIO Toggle */
759 u32 rw_cap[MAX_ALLOWED_LUN_CNT];
760 /* card to lun mapping table */
761 u8 card2lun[32];
762 /* lun to card mapping table */
763 u8 lun2card[MAX_ALLOWED_LUN_CNT];
764
765 #ifdef _MSG_TRACE
766 struct trace_msg_t trace_msg[TRACE_ITEM_CNT];
767 int msg_idx;
768 #endif
769
770 int rw_need_retry;
771
772 /* ASIC or FPGA */
773 int asic_code;
774
775 /* QFN24 or LQFP48 */
776 int package;
777
778 /* Full Speed or High Speed */
779 int usb_speed;
780
781 /*sangdy:enable or disable UHS50 and MMC4.4 */
782 int uhs50_mmc44_en;
783
784 u8 ic_version;
785
786 /* Command buffer */
787 u8 *cmd_buf;
788 unsigned int cmd_idx;
789 /* Response buffer */
790 u8 *rsp_buf;
791
792 u16 card_status;
793
794 #ifdef SUPPORT_OCP
795 u16 ocp_stat;
796 #endif
797
798 struct rts51x_option option;
799 struct rts51x_usb *usb;
800
801 u8 rcc_read_response;
802 int reset_need_retry;
803 u8 rts5179;
804 };
805
806 #define UHS50_EN 0x0001
807 #define UHS50_DIS 0x0000
808 #define SET_UHS50(chip) ((chip)->uhs50_mmc44_en = UHS50_EN)
809 #define CLEAR_UHS50(chip) ((chip)->uhs50_mmc44_en = UHS50_DIS)
810 #define CHECK_UHS50(chip) (((chip)->uhs50_mmc44_en&0xff) == UHS50_EN)
811
812 #define RTS51X_GET_VID(chip) ((chip)->vendor_id)
813 #define RTS51X_GET_PID(chip) ((chip)->product_id)
814
815 #define RTS51X_SET_STAT(chip, stat) \
816 do { \
817 if ((stat) != STAT_IDLE) { \
818 (chip)->idle_counter = 0; \
819 } \
820 (chip)->chip_stat = (enum CHIP_STAT)(stat); \
821 } while (0)
822 #define RTS51X_CHK_STAT(chip, stat) ((chip)->chip_stat == (stat))
823 #define RTS51X_GET_STAT(chip) ((chip)->chip_stat)
824
825 #define CHECK_PID(chip, pid) (RTS51X_GET_PID(chip) == (pid))
826 #define CHECK_PKG(chip, pkg) ((chip)->package == (pkg))
827 #define CHECK_USB(chip, speed) ((chip)->usb_speed == (speed))
828
829 int rts51x_reset_chip(struct rts51x_chip *chip);
830 int rts51x_init_chip(struct rts51x_chip *chip);
831 int rts51x_release_chip(struct rts51x_chip *chip);
832 void rts51x_polling_func(struct rts51x_chip *chip);
833
rts51x_init_cmd(struct rts51x_chip * chip)834 static inline void rts51x_init_cmd(struct rts51x_chip *chip)
835 {
836 chip->cmd_idx = 0;
837 chip->cmd_buf[0] = 'R';
838 chip->cmd_buf[1] = 'T';
839 chip->cmd_buf[2] = 'C';
840 chip->cmd_buf[3] = 'R';
841 chip->cmd_buf[PACKET_TYPE] = BATCH_CMD;
842 }
843
844 void rts51x_add_cmd(struct rts51x_chip *chip,
845 u8 cmd_type, u16 reg_addr, u8 mask, u8 data);
846 int rts51x_send_cmd(struct rts51x_chip *chip, u8 flag, int timeout);
847 int rts51x_get_rsp(struct rts51x_chip *chip, int rsp_len, int timeout);
848
rts51x_read_rsp_buf(struct rts51x_chip * chip,int offset,u8 * buf,int buf_len)849 static inline void rts51x_read_rsp_buf(struct rts51x_chip *chip, int offset,
850 u8 *buf, int buf_len)
851 {
852 memcpy(buf, chip->rsp_buf + offset, buf_len);
853 }
854
rts51x_get_rsp_data(struct rts51x_chip * chip)855 static inline u8 *rts51x_get_rsp_data(struct rts51x_chip *chip)
856 {
857 return chip->rsp_buf;
858 }
859
860 int rts51x_get_card_status(struct rts51x_chip *chip, u16 *status);
861 int rts51x_write_register(struct rts51x_chip *chip, u16 addr, u8 mask, u8 data);
862 int rts51x_read_register(struct rts51x_chip *chip, u16 addr, u8 *data);
863 int rts51x_ep0_write_register(struct rts51x_chip *chip, u16 addr, u8 mask,
864 u8 data);
865 int rts51x_ep0_read_register(struct rts51x_chip *chip, u16 addr, u8 *data);
866 int rts51x_seq_write_register(struct rts51x_chip *chip, u16 addr, u16 len,
867 u8 *data);
868 int rts51x_seq_read_register(struct rts51x_chip *chip, u16 addr, u16 len,
869 u8 *data);
870 int rts51x_read_ppbuf(struct rts51x_chip *chip, u8 *buf, int buf_len);
871 int rts51x_write_ppbuf(struct rts51x_chip *chip, u8 *buf, int buf_len);
872 int rts51x_write_phy_register(struct rts51x_chip *chip, u8 addr, u8 val);
873 int rts51x_read_phy_register(struct rts51x_chip *chip, u8 addr, u8 *val);
874 void rts51x_do_before_power_down(struct rts51x_chip *chip);
875 void rts51x_clear_hw_error(struct rts51x_chip *chip);
876 void rts51x_prepare_run(struct rts51x_chip *chip);
877 void rts51x_trace_msg(struct rts51x_chip *chip, unsigned char *buf, int clear);
878 void rts51x_pp_status(struct rts51x_chip *chip, unsigned int lun, u8 *status,
879 u8 status_len);
880 void rts51x_read_status(struct rts51x_chip *chip, unsigned int lun,
881 u8 *rts51x_status, u8 status_len);
882 int rts51x_transfer_data_rcc(struct rts51x_chip *chip, unsigned int pipe,
883 void *buf, unsigned int len, int use_sg,
884 unsigned int *act_len, int timeout, u8 stage_flag);
885
886 #define RTS51X_WRITE_REG(chip, addr, mask, data) \
887 do { \
888 int _retval = rts51x_write_register((chip), \
889 (addr), (mask), (data)); \
890 if (_retval != STATUS_SUCCESS) { \
891 TRACE_RET((chip), _retval); \
892 } \
893 } while (0)
894
895 #define RTS51X_READ_REG(chip, addr, data) \
896 do { \
897 int _retval = rts51x_read_register((chip), \
898 (addr), (data)); \
899 if (_retval != STATUS_SUCCESS) { \
900 TRACE_RET((chip), _retval); \
901 } \
902 } while (0)
903
904 #endif /* __RTS51X_CHIP_H */
905