1 /* Driver for Realtek PCI-Express card reader 2 * Header file 3 * 4 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2, or (at your option) any 9 * later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 * 19 * Author: 20 * wwang (wei_wang@realsil.com.cn) 21 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China 22 */ 23 24 #ifndef __REALTEK_RTSX_SD_H 25 #define __REALTEK_RTSX_SD_H 26 27 #include "rtsx_chip.h" 28 29 #define SUPPORT_VOLTAGE 0x003C0000 30 31 /* Error Code */ 32 #define SD_NO_ERROR 0x0 33 #define SD_CRC_ERR 0x80 34 #define SD_TO_ERR 0x40 35 #define SD_NO_CARD 0x20 36 #define SD_BUSY 0x10 37 #define SD_STS_ERR 0x08 38 #define SD_RSP_TIMEOUT 0x04 39 #define SD_IO_ERR 0x02 40 41 /* MMC/SD Command Index */ 42 /* Basic command (class 0) */ 43 #define GO_IDLE_STATE 0 44 #define SEND_OP_COND 1 45 #define ALL_SEND_CID 2 46 #define SET_RELATIVE_ADDR 3 47 #define SEND_RELATIVE_ADDR 3 48 #define SET_DSR 4 49 #define IO_SEND_OP_COND 5 50 #define SWITCH 6 51 #define SELECT_CARD 7 52 #define DESELECT_CARD 7 53 /* CMD8 is "SEND_EXT_CSD" for MMC4.x Spec 54 * while is "SEND_IF_COND" for SD 2.0 55 */ 56 #define SEND_EXT_CSD 8 57 #define SEND_IF_COND 8 58 59 #define SEND_CSD 9 60 #define SEND_CID 10 61 #define VOLTAGE_SWITCH 11 62 #define READ_DAT_UTIL_STOP 11 63 #define STOP_TRANSMISSION 12 64 #define SEND_STATUS 13 65 #define GO_INACTIVE_STATE 15 66 67 #define SET_BLOCKLEN 16 68 #define READ_SINGLE_BLOCK 17 69 #define READ_MULTIPLE_BLOCK 18 70 #define SEND_TUNING_PATTERN 19 71 72 #define BUSTEST_R 14 73 #define BUSTEST_W 19 74 75 #define WRITE_BLOCK 24 76 #define WRITE_MULTIPLE_BLOCK 25 77 #define PROGRAM_CSD 27 78 79 #define ERASE_WR_BLK_START 32 80 #define ERASE_WR_BLK_END 33 81 #define ERASE_CMD 38 82 83 #define LOCK_UNLOCK 42 84 #define IO_RW_DIRECT 52 85 86 #define APP_CMD 55 87 #define GEN_CMD 56 88 89 #define SET_BUS_WIDTH 6 90 #define SD_STATUS 13 91 #define SEND_NUM_WR_BLOCKS 22 92 #define SET_WR_BLK_ERASE_COUNT 23 93 #define SD_APP_OP_COND 41 94 #define SET_CLR_CARD_DETECT 42 95 #define SEND_SCR 51 96 97 #define SD_READ_COMPLETE 0x00 98 #define SD_READ_TO 0x01 99 #define SD_READ_ADVENCE 0x02 100 101 #define SD_CHECK_MODE 0x00 102 #define SD_SWITCH_MODE 0x80 103 #define SD_FUNC_GROUP_1 0x01 104 #define SD_FUNC_GROUP_2 0x02 105 #define SD_FUNC_GROUP_3 0x03 106 #define SD_FUNC_GROUP_4 0x04 107 #define SD_CHECK_SPEC_V1_1 0xFF 108 109 #define NO_ARGUMENT 0x00 110 #define CHECK_PATTERN 0x000000AA 111 #define VOLTAGE_SUPPLY_RANGE 0x00000100 112 #define SUPPORT_HIGH_AND_EXTENDED_CAPACITY 0x40000000 113 #define SUPPORT_MAX_POWER_PERMANCE 0x10000000 114 #define SUPPORT_1V8 0x01000000 115 116 #define SWTICH_NO_ERR 0x00 117 #define CARD_NOT_EXIST 0x01 118 #define SPEC_NOT_SUPPORT 0x02 119 #define CHECK_MODE_ERR 0x03 120 #define CHECK_NOT_READY 0x04 121 #define SWITCH_CRC_ERR 0x05 122 #define SWITCH_MODE_ERR 0x06 123 #define SWITCH_PASS 0x07 124 125 #ifdef SUPPORT_SD_LOCK 126 #define SD_ERASE 0x08 127 #define SD_LOCK 0x04 128 #define SD_UNLOCK 0x00 129 #define SD_CLR_PWD 0x02 130 #define SD_SET_PWD 0x01 131 132 #define SD_PWD_LEN 0x10 133 134 #define SD_LOCKED 0x80 135 #define SD_LOCK_1BIT_MODE 0x40 136 #define SD_PWD_EXIST 0x20 137 #define SD_UNLOCK_POW_ON 0x01 138 #define SD_SDR_RST 0x02 139 140 #define SD_NOT_ERASE 0x00 141 #define SD_UNDER_ERASING 0x01 142 #define SD_COMPLETE_ERASE 0x02 143 144 #define SD_RW_FORBIDDEN 0x0F 145 146 #endif 147 148 #define HS_SUPPORT 0x01 149 #define SDR50_SUPPORT 0x02 150 #define SDR104_SUPPORT 0x03 151 #define DDR50_SUPPORT 0x04 152 153 #define HS_SUPPORT_MASK 0x02 154 #define SDR50_SUPPORT_MASK 0x04 155 #define SDR104_SUPPORT_MASK 0x08 156 #define DDR50_SUPPORT_MASK 0x10 157 158 #define HS_QUERY_SWITCH_OK 0x01 159 #define SDR50_QUERY_SWITCH_OK 0x02 160 #define SDR104_QUERY_SWITCH_OK 0x03 161 #define DDR50_QUERY_SWITCH_OK 0x04 162 163 #define HS_SWITCH_BUSY 0x02 164 #define SDR50_SWITCH_BUSY 0x04 165 #define SDR104_SWITCH_BUSY 0x08 166 #define DDR50_SWITCH_BUSY 0x10 167 168 #define FUNCTION_GROUP1_SUPPORT_OFFSET 0x0D 169 #define FUNCTION_GROUP1_QUERY_SWITCH_OFFSET 0x10 170 #define FUNCTION_GROUP1_CHECK_BUSY_OFFSET 0x1D 171 172 #define DRIVING_TYPE_A 0x01 173 #define DRIVING_TYPE_B 0x00 174 #define DRIVING_TYPE_C 0x02 175 #define DRIVING_TYPE_D 0x03 176 177 #define DRIVING_TYPE_A_MASK 0x02 178 #define DRIVING_TYPE_B_MASK 0x01 179 #define DRIVING_TYPE_C_MASK 0x04 180 #define DRIVING_TYPE_D_MASK 0x08 181 182 #define TYPE_A_QUERY_SWITCH_OK 0x01 183 #define TYPE_B_QUERY_SWITCH_OK 0x00 184 #define TYPE_C_QUERY_SWITCH_OK 0x02 185 #define TYPE_D_QUERY_SWITCH_OK 0x03 186 187 #define TYPE_A_SWITCH_BUSY 0x02 188 #define TYPE_B_SWITCH_BUSY 0x01 189 #define TYPE_C_SWITCH_BUSY 0x04 190 #define TYPE_D_SWITCH_BUSY 0x08 191 192 #define FUNCTION_GROUP3_SUPPORT_OFFSET 0x09 193 #define FUNCTION_GROUP3_QUERY_SWITCH_OFFSET 0x0F 194 #define FUNCTION_GROUP3_CHECK_BUSY_OFFSET 0x19 195 196 #define CURRENT_LIMIT_200 0x00 197 #define CURRENT_LIMIT_400 0x01 198 #define CURRENT_LIMIT_600 0x02 199 #define CURRENT_LIMIT_800 0x03 200 201 #define CURRENT_LIMIT_200_MASK 0x01 202 #define CURRENT_LIMIT_400_MASK 0x02 203 #define CURRENT_LIMIT_600_MASK 0x04 204 #define CURRENT_LIMIT_800_MASK 0x08 205 206 #define CURRENT_LIMIT_200_QUERY_SWITCH_OK 0x00 207 #define CURRENT_LIMIT_400_QUERY_SWITCH_OK 0x01 208 #define CURRENT_LIMIT_600_QUERY_SWITCH_OK 0x02 209 #define CURRENT_LIMIT_800_QUERY_SWITCH_OK 0x03 210 211 #define CURRENT_LIMIT_200_SWITCH_BUSY 0x01 212 #define CURRENT_LIMIT_400_SWITCH_BUSY 0x02 213 #define CURRENT_LIMIT_600_SWITCH_BUSY 0x04 214 #define CURRENT_LIMIT_800_SWITCH_BUSY 0x08 215 216 #define FUNCTION_GROUP4_SUPPORT_OFFSET 0x07 217 #define FUNCTION_GROUP4_QUERY_SWITCH_OFFSET 0x0F 218 #define FUNCTION_GROUP4_CHECK_BUSY_OFFSET 0x17 219 220 #define DATA_STRUCTURE_VER_OFFSET 0x11 221 222 #define MAX_PHASE 31 223 224 #define MMC_8BIT_BUS 0x0010 225 #define MMC_4BIT_BUS 0x0020 226 227 #define MMC_SWITCH_ERR 0x80 228 229 #define SD_IO_3V3 0 230 #define SD_IO_1V8 1 231 232 #define TUNE_TX 0x00 233 #define TUNE_RX 0x01 234 235 #define CHANGE_TX 0x00 236 #define CHANGE_RX 0x01 237 238 #define DCM_HIGH_FREQUENCY_MODE 0x00 239 #define DCM_LOW_FREQUENCY_MODE 0x01 240 241 #define DCM_HIGH_FREQUENCY_MODE_SET 0x0C 242 #define DCM_Low_FREQUENCY_MODE_SET 0x00 243 244 #define MULTIPLY_BY_1 0x00 245 #define MULTIPLY_BY_2 0x01 246 #define MULTIPLY_BY_3 0x02 247 #define MULTIPLY_BY_4 0x03 248 #define MULTIPLY_BY_5 0x04 249 #define MULTIPLY_BY_6 0x05 250 #define MULTIPLY_BY_7 0x06 251 #define MULTIPLY_BY_8 0x07 252 #define MULTIPLY_BY_9 0x08 253 #define MULTIPLY_BY_10 0x09 254 255 #define DIVIDE_BY_2 0x01 256 #define DIVIDE_BY_3 0x02 257 #define DIVIDE_BY_4 0x03 258 #define DIVIDE_BY_5 0x04 259 #define DIVIDE_BY_6 0x05 260 #define DIVIDE_BY_7 0x06 261 #define DIVIDE_BY_8 0x07 262 #define DIVIDE_BY_9 0x08 263 #define DIVIDE_BY_10 0x09 264 265 struct timing_phase_path { 266 int start; 267 int end; 268 int mid; 269 int len; 270 }; 271 272 int sd_select_card(struct rtsx_chip *chip, int select); 273 int sd_pull_ctl_enable(struct rtsx_chip *chip); 274 int reset_sd_card(struct rtsx_chip *chip); 275 int sd_switch_clock(struct rtsx_chip *chip); 276 void sd_stop_seq_mode(struct rtsx_chip *chip); 277 int sd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector, u16 sector_cnt); 278 void sd_cleanup_work(struct rtsx_chip *chip); 279 int sd_power_off_card3v3(struct rtsx_chip *chip); 280 int release_sd_card(struct rtsx_chip *chip); 281 #ifdef SUPPORT_CPRM 282 int soft_reset_sd_card(struct rtsx_chip *chip); 283 int ext_sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx, 284 u32 arg, u8 rsp_type, u8 *rsp, int rsp_len, int special_check); 285 int ext_sd_get_rsp(struct rtsx_chip *chip, int len, u8 *rsp, u8 rsp_type); 286 287 int sd_pass_thru_mode(struct scsi_cmnd *srb, struct rtsx_chip *chip); 288 int sd_execute_no_data(struct scsi_cmnd *srb, struct rtsx_chip *chip); 289 int sd_execute_read_data(struct scsi_cmnd *srb, struct rtsx_chip *chip); 290 int sd_execute_write_data(struct scsi_cmnd *srb, struct rtsx_chip *chip); 291 int sd_get_cmd_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip); 292 int sd_hw_rst(struct scsi_cmnd *srb, struct rtsx_chip *chip); 293 #endif 294 295 #endif /* __REALTEK_RTSX_SD_H */ 296